arch/x86/kernel/cpu/mcheck/therm_throt.c

   1 /*
   2  * Thermal throttle event support code (such as syslog messaging and rate
   3  * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
   4  *
   5  * This allows consistent reporting of CPU thermal throttle events.
   6  *
   7  * Maintains a counter in /sys that keeps track of the number of thermal
   8  * events, such that the user knows how bad the thermal problem might be
   9  * (since the logging to syslog is rate limited).
  10  *
  11  * Author: Dmitriy Zavin (dmitriyz@google.com)
  12  *
  13  * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
  14  *          Inspired by Ross Biro's and Al Borchers' counter code.
  15  */
  16 #include <linux/interrupt.h>
  17 #include <linux/notifier.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/kernel.h>
  20 #include <linux/percpu.h>
  21 #include <linux/export.h>
  22 #include <linux/types.h>
  23 #include <linux/init.h>
  24 #include <linux/smp.h>
  25 #include <linux/cpu.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/traps.h>
  29 #include <asm/apic.h>
  30 #include <asm/mce.h>
  31 #include <asm/msr.h>
  32 #include <asm/trace/irq_vectors.h>
  33
  34 /* How long to wait between reporting thermal events */
  35 #define CHECK_INTERVAL          (300 * HZ)
  36
  37 #define THERMAL_THROTTLING_EVENT        0
  38 #define POWER_LIMIT_EVENT               1
  39
  40 /*
  41  * Current thermal event state:
  42  */
  43 struct _thermal_state {
  44         bool                    new_event;
  45         int                     event;
  46         u64                     next_check;
  47         unsigned long           count;
  48         unsigned long           last_count;
  49 };
  50
  51 struct thermal_state {
  52         struct _thermal_state core_throttle;
  53         struct _thermal_state core_power_limit;
  54         struct _thermal_state package_throttle;
  55         struct _thermal_state package_power_limit;
  56         struct _thermal_state core_thresh0;
  57         struct _thermal_state core_thresh1;
  58         struct _thermal_state pkg_thresh0;
  59         struct _thermal_state pkg_thresh1;
  60 };
  61
  62 /* Callback to handle core threshold interrupts */
  63 int (*platform_thermal_notify)(__u64 msr_val);
  64 EXPORT_SYMBOL(platform_thermal_notify);
  65
  66 /* Callback to handle core package threshold_interrupts */
  67 int (*platform_thermal_package_notify)(__u64 msr_val);
  68 EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
  69
  70 /* Callback support of rate control, return true, if
  71  * callback has rate control */
  72 bool (*platform_thermal_package_rate_control)(void);
  73 EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
  74
  75
  76 static DEFINE_PER_CPU(struct thermal_state, thermal_state);
  77
  78 static atomic_t therm_throt_en  = ATOMIC_INIT(0);
  79
  80 static u32 lvtthmr_init __read_mostly;
  81
  82 #ifdef CONFIG_SYSFS
  83 #define define_therm_throt_device_one_ro(_name)                         \
  84         static DEVICE_ATTR(_name, 0444,                                 \
  85                            therm_throt_device_show_##_name,             \
  86                                    NULL)                                \
  87
  88 #define define_therm_throt_device_show_func(event, name)                \
  89                                                                         \
  90 static ssize_t therm_throt_device_show_##event##_##name(                \
  91                         struct device *dev,                             \
  92                         struct device_attribute *attr,                  \
  93                         char *buf)                                      \
  94 {                                                                       \
  95         unsigned int cpu = dev->id;                                     \
  96         ssize_t ret;                                                    \
  97                                                                         \
  98         preempt_disable();      /* CPU hotplug */                       \
  99         if (cpu_online(cpu)) {                                          \
 100                 ret = sprintf(buf, "%lu\n",                             \
 101                               per_cpu(thermal_state, cpu).event.name);  \
 102         } else                                                          \
 103                 ret = 0;                                                \
 104         preempt_enable();                                               \
 105                                                                         \
 106         return ret;                                                     \
 107 }
 108
 109 define_therm_throt_device_show_func(core_throttle, count);
 110 define_therm_throt_device_one_ro(core_throttle_count);
 111
 112 define_therm_throt_device_show_func(core_power_limit, count);
 113 define_therm_throt_device_one_ro(core_power_limit_count);
 114
 115 define_therm_throt_device_show_func(package_throttle, count);
 116 define_therm_throt_device_one_ro(package_throttle_count);
 117
 118 define_therm_throt_device_show_func(package_power_limit, count);
 119 define_therm_throt_device_one_ro(package_power_limit_count);
 120
 121 static struct attribute *thermal_throttle_attrs[] = {
 122         &dev_attr_core_throttle_count.attr,
 123         NULL
 124 };
 125
 126 static const struct attribute_group thermal_attr_group = {
 127         .attrs  = thermal_throttle_attrs,
 128         .name   = "thermal_throttle"
 129 };
 130 #endif /* CONFIG_SYSFS */
 131
 132 #define CORE_LEVEL      0
 133 #define PACKAGE_LEVEL   1
 134
 135 /***
 136  * therm_throt_process - Process thermal throttling event from interrupt
 137  * @curr: Whether the condition is current or not (boolean), since the
 138  *        thermal interrupt normally gets called both when the thermal
 139  *        event begins and once the event has ended.
 140  *
 141  * This function is called by the thermal interrupt after the
 142  * IRQ has been acknowledged.
 143  *
 144  * It will take care of rate limiting and printing messages to the syslog.
 145  */
 146 static void therm_throt_process(bool new_event, int event, int level)
 147 {
 148         struct _thermal_state *state;
 149         unsigned int this_cpu = smp_processor_id();
 150         bool old_event;
 151         u64 now;
 152         struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
 153
 154         now = get_jiffies_64();
 155         if (level == CORE_LEVEL) {
 156                 if (event == THERMAL_THROTTLING_EVENT)
 157                         state = &pstate->core_throttle;
 158                 else if (event == POWER_LIMIT_EVENT)
 159                         state = &pstate->core_power_limit;
 160                 else
 161                         return;
 162         } else if (level == PACKAGE_LEVEL) {
 163                 if (event == THERMAL_THROTTLING_EVENT)
 164                         state = &pstate->package_throttle;
 165                 else if (event == POWER_LIMIT_EVENT)
 166                         state = &pstate->package_power_limit;
 167                 else
 168                         return;
 169         } else
 170                 return;
 171
 172         old_event = state->new_event;
 173         state->new_event = new_event;
 174
 175         if (new_event)
 176                 state->count++;
 177
 178         if (time_before64(now, state->next_check) &&
 179                         state->count != state->last_count)
 180                 return;
 181
 182         state->next_check = now + CHECK_INTERVAL;
 183         state->last_count = state->count;
 184
 185         /* if we just entered the thermal event */
 186         if (new_event) {
 187                 if (event == THERMAL_THROTTLING_EVENT)
 188                         pr_warn("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
 189                                 this_cpu,
 190                                 level == CORE_LEVEL ? "Core" : "Package",
 191                                 state->count);
 192                 return;
 193         }
 194         if (old_event) {
 195                 if (event == THERMAL_THROTTLING_EVENT)
 196                         pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
 197                                 level == CORE_LEVEL ? "Core" : "Package");
 198                 return;
 199         }
 200 }
 201
 202 static int thresh_event_valid(int level, int event)
 203 {
 204         struct _thermal_state *state;
 205         unsigned int this_cpu = smp_processor_id();
 206         struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
 207         u64 now = get_jiffies_64();
 208
 209         if (level == PACKAGE_LEVEL)
 210                 state = (event == 0) ? &pstate->pkg_thresh0 :
 211                                                 &pstate->pkg_thresh1;
 212         else
 213                 state = (event == 0) ? &pstate->core_thresh0 :
 214                                                 &pstate->core_thresh1;
 215
 216         if (time_before64(now, state->next_check))
 217                 return 0;
 218
 219         state->next_check = now + CHECK_INTERVAL;
 220
 221         return 1;
 222 }
 223
 224 static bool int_pln_enable;
 225 static int __init int_pln_enable_setup(char *s)
 226 {
 227         int_pln_enable = true;
 228
 229         return 1;
 230 }
 231 __setup("int_pln_enable", int_pln_enable_setup);
 232
 233 #ifdef CONFIG_SYSFS
 234 /* Add/Remove thermal_throttle interface for CPU device: */
 235 static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
 236 {
 237         int err;
 238         struct cpuinfo_x86 *c = &cpu_data(cpu);
 239
 240         err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
 241         if (err)
 242                 return err;
 243
 244         if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 245                 err = sysfs_add_file_to_group(&dev->kobj,
 246                                               &dev_attr_core_power_limit_count.attr,
 247                                               thermal_attr_group.name);
 248         if (cpu_has(c, X86_FEATURE_PTS)) {
 249                 err = sysfs_add_file_to_group(&dev->kobj,
 250                                               &dev_attr_package_throttle_count.attr,
 251                                               thermal_attr_group.name);
 252                 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 253                         err = sysfs_add_file_to_group(&dev->kobj,
 254                                         &dev_attr_package_power_limit_count.attr,
 255                                         thermal_attr_group.name);
 256         }
 257
 258         return err;
 259 }
 260
 261 static void thermal_throttle_remove_dev(struct device *dev)
 262 {
 263         sysfs_remove_group(&dev->kobj, &thermal_attr_group);
 264 }
 265
 266 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
 267 static int thermal_throttle_online(unsigned int cpu)
 268 {
 269         struct device *dev = get_cpu_device(cpu);
 270
 271         return thermal_throttle_add_dev(dev, cpu);
 272 }
 273
 274 static int thermal_throttle_offline(unsigned int cpu)
 275 {
 276         struct device *dev = get_cpu_device(cpu);
 277
 278         thermal_throttle_remove_dev(dev);
 279         return 0;
 280 }
 281
 282 static __init int thermal_throttle_init_device(void)
 283 {
 284         int ret;
 285
 286         if (!atomic_read(&therm_throt_en))
 287                 return 0;
 288
 289         ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online",
 290                                 thermal_throttle_online,
 291                                 thermal_throttle_offline);
 292         return ret < 0 ? ret : 0;
 293 }
 294 device_initcall(thermal_throttle_init_device);
 295
 296 #endif /* CONFIG_SYSFS */
 297
 298 static void notify_package_thresholds(__u64 msr_val)
 299 {
 300         bool notify_thres_0 = false;
 301         bool notify_thres_1 = false;
 302
 303         if (!platform_thermal_package_notify)
 304                 return;
 305
 306         /* lower threshold check */
 307         if (msr_val & THERM_LOG_THRESHOLD0)
 308                 notify_thres_0 = true;
 309         /* higher threshold check */
 310         if (msr_val & THERM_LOG_THRESHOLD1)
 311                 notify_thres_1 = true;
 312
 313         if (!notify_thres_0 && !notify_thres_1)
 314                 return;
 315
 316         if (platform_thermal_package_rate_control &&
 317                 platform_thermal_package_rate_control()) {
 318                 /* Rate control is implemented in callback */
 319                 platform_thermal_package_notify(msr_val);
 320                 return;
 321         }
 322
 323         /* lower threshold reached */
 324         if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
 325                 platform_thermal_package_notify(msr_val);
 326         /* higher threshold reached */
 327         if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
 328                 platform_thermal_package_notify(msr_val);
 329 }
 330
 331 static void notify_thresholds(__u64 msr_val)
 332 {
 333         /* check whether the interrupt handler is defined;
 334          * otherwise simply return
 335          */
 336         if (!platform_thermal_notify)
 337                 return;
 338
 339         /* lower threshold reached */
 340         if ((msr_val & THERM_LOG_THRESHOLD0) &&
 341                         thresh_event_valid(CORE_LEVEL, 0))
 342                 platform_thermal_notify(msr_val);
 343         /* higher threshold reached */
 344         if ((msr_val & THERM_LOG_THRESHOLD1) &&
 345                         thresh_event_valid(CORE_LEVEL, 1))
 346                 platform_thermal_notify(msr_val);
 347 }
 348
 349 /* Thermal transition interrupt handler */
 350 static void intel_thermal_interrupt(void)
 351 {
 352         __u64 msr_val;
 353
 354         if (static_cpu_has(X86_FEATURE_HWP))
 355                 wrmsrl_safe(MSR_HWP_STATUS, 0);
 356
 357         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
 358
 359         /* Check for violation of core thermal thresholds*/
 360         notify_thresholds(msr_val);
 361
 362         therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
 363                             THERMAL_THROTTLING_EVENT,
 364                             CORE_LEVEL);
 365
 366         if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
 367                 therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
 368                                         POWER_LIMIT_EVENT,
 369                                         CORE_LEVEL);
 370
 371         if (this_cpu_has(X86_FEATURE_PTS)) {
 372                 rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
 373                 /* check violations of package thermal thresholds */
 374                 notify_package_thresholds(msr_val);
 375                 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
 376                                         THERMAL_THROTTLING_EVENT,
 377                                         PACKAGE_LEVEL);
 378                 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
 379                         therm_throt_process(msr_val &
 380                                         PACKAGE_THERM_STATUS_POWER_LIMIT,
 381                                         POWER_LIMIT_EVENT,
 382                                         PACKAGE_LEVEL);
 383         }
 384 }
 385
 386 static void unexpected_thermal_interrupt(void)
 387 {
 388         pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
 389                 smp_processor_id());
 390 }
 391
 392 static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
 393
 394 asmlinkage __visible void __irq_entry smp_thermal_interrupt(struct pt_regs *regs)
 395 {
 396         entering_irq();
 397         trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
 398         inc_irq_stat(irq_thermal_count);
 399         smp_thermal_vector();
 400         trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
 401         exiting_ack_irq();
 402 }
 403
 404 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
 405 static int intel_thermal_supported(struct cpuinfo_x86 *c)
 406 {
 407         if (!boot_cpu_has(X86_FEATURE_APIC))
 408                 return 0;
 409         if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
 410                 return 0;
 411         return 1;
 412 }
 413
 414 void __init mcheck_intel_therm_init(void)
 415 {
 416         /*
 417          * This function is only called on boot CPU. Save the init thermal
 418          * LVT value on BSP and use that value to restore APs' thermal LVT
 419          * entry BIOS programmed later
 420          */
 421         if (intel_thermal_supported(&boot_cpu_data))
 422                 lvtthmr_init = apic_read(APIC_LVTTHMR);
 423 }
 424
 425 void intel_init_thermal(struct cpuinfo_x86 *c)
 426 {
 427         unsigned int cpu = smp_processor_id();
 428         int tm2 = 0;
 429         u32 l, h;
 430
 431         if (!intel_thermal_supported(c))
 432                 return;
 433
 434         /*
 435          * First check if its enabled already, in which case there might
 436          * be some SMM goo which handles it, so we can't even put a handler
 437          * since it might be delivered via SMI already:
 438          */
 439         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 440
 441         h = lvtthmr_init;
 442         /*
 443          * The initial value of thermal LVT entries on all APs always reads
 444          * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
 445          * sequence to them and LVT registers are reset to 0s except for
 446          * the mask bits which are set to 1s when APs receive INIT IPI.
 447          * If BIOS takes over the thermal interrupt and sets its interrupt
 448          * delivery mode to SMI (not fixed), it restores the value that the
 449          * BIOS has programmed on AP based on BSP's info we saved since BIOS
 450          * is always setting the same value for all threads/cores.
 451          */
 452         if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
 453                 apic_write(APIC_LVTTHMR, lvtthmr_init);
 454
 455
 456         if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
 457                 if (system_state == SYSTEM_BOOTING)
 458                         pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
 459                 return;
 460         }
 461
 462         /* early Pentium M models use different method for enabling TM2 */
 463         if (cpu_has(c, X86_FEATURE_TM2)) {
 464                 if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
 465                         rdmsr(MSR_THERM2_CTL, l, h);
 466                         if (l & MSR_THERM2_CTL_TM_SELECT)
 467                                 tm2 = 1;
 468                 } else if (l & MSR_IA32_MISC_ENABLE_TM2)
 469                         tm2 = 1;
 470         }
 471
 472         /* We'll mask the thermal vector in the lapic till we're ready: */
 473         h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
 474         apic_write(APIC_LVTTHMR, h);
 475
 476         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
 477         if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
 478                 wrmsr(MSR_IA32_THERM_INTERRUPT,
 479                         (l | (THERM_INT_LOW_ENABLE
 480                         | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
 481         else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 482                 wrmsr(MSR_IA32_THERM_INTERRUPT,
 483                         l | (THERM_INT_LOW_ENABLE
 484                         | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
 485         else
 486                 wrmsr(MSR_IA32_THERM_INTERRUPT,
 487                       l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
 488
 489         if (cpu_has(c, X86_FEATURE_PTS)) {
 490                 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
 491                 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
 492                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
 493                                 (l | (PACKAGE_THERM_INT_LOW_ENABLE
 494                                 | PACKAGE_THERM_INT_HIGH_ENABLE))
 495                                 & ~PACKAGE_THERM_INT_PLN_ENABLE, h);
 496                 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
 497                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
 498                                 l | (PACKAGE_THERM_INT_LOW_ENABLE
 499                                 | PACKAGE_THERM_INT_HIGH_ENABLE
 500                                 | PACKAGE_THERM_INT_PLN_ENABLE), h);
 501                 else
 502                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
 503                               l | (PACKAGE_THERM_INT_LOW_ENABLE
 504                                 | PACKAGE_THERM_INT_HIGH_ENABLE), h);
 505         }
 506
 507         smp_thermal_vector = intel_thermal_interrupt;
 508
 509         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 510         wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 511
 512         /* Unmask the thermal vector: */
 513         l = apic_read(APIC_LVTTHMR);
 514         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
 515
 516         pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
 517                       tm2 ? "TM2" : "TM1");
 518
 519         /* enable thermal throttle processing */
 520         atomic_set(&therm_throt_en, 1);
 521 }