1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
64 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
71 u64 ctl; /* subevents to enable */
73 __u64 init : 1, /* initialise bank? */
76 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
79 /* One object for each MCE bank, shared by all CPUs */
81 struct device_attribute attr; /* device attribute */
82 char attrname[ATTR_LEN]; /* attribute name */
83 u8 bank; /* bank number */
85 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
87 struct mce_vendor_flags mce_flags __read_mostly;
89 struct mca_config mca_cfg __read_mostly = {
94 static DEFINE_PER_CPU(struct mce, mces_seen);
95 static unsigned long mce_need_notify;
98 * MCA banks polled by the period polling timer for corrected events.
99 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
101 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
102 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
106 * MCA banks controlled through firmware first for corrected errors.
107 * This is a global list of banks for which we won't enable CMCI and we
108 * won't poll. Firmware controls these banks and is responsible for
109 * reporting corrected errors through GHES. Uncorrected/recoverable
110 * errors are still notified through a machine check.
112 mce_banks_t mce_banks_ce_disabled;
114 static struct work_struct mce_work;
115 static struct irq_work mce_irq_work;
118 * CPU/chipset specific EDAC code can register a notifier call here to print
119 * MCE errors in a human-readable form.
121 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
123 /* Do initial initialization of a struct mce */
124 void mce_setup(struct mce *m)
126 memset(m, 0, sizeof(struct mce));
127 m->cpu = m->extcpu = smp_processor_id();
128 /* need the internal __ version to avoid deadlocks */
129 m->time = __ktime_get_real_seconds();
130 m->cpuvendor = boot_cpu_data.x86_vendor;
131 m->cpuid = cpuid_eax(1);
132 m->socketid = cpu_data(m->extcpu).phys_proc_id;
133 m->apicid = cpu_data(m->extcpu).initial_apicid;
134 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
135 m->ppin = cpu_data(m->extcpu).ppin;
136 m->microcode = boot_cpu_data.microcode;
139 DEFINE_PER_CPU(struct mce, injectm);
140 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
142 void mce_log(struct mce *m)
144 if (!mce_gen_pool_add(m))
145 irq_work_queue(&mce_irq_work);
147 EXPORT_SYMBOL_GPL(mce_log);
149 void mce_register_decode_chain(struct notifier_block *nb)
151 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST ||
152 nb->priority > MCE_PRIO_HIGHEST))
155 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
157 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
159 void mce_unregister_decode_chain(struct notifier_block *nb)
161 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
163 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
165 static void __print_mce(struct mce *m)
167 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
169 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
170 m->mcgstatus, m->bank, m->status);
173 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
174 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
177 if (m->cs == __KERNEL_CS)
178 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
182 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
184 pr_cont("ADDR %llx ", m->addr);
186 pr_cont("MISC %llx ", m->misc);
188 pr_cont("PPIN %llx ", m->ppin);
190 if (mce_flags.smca) {
192 pr_cont("SYND %llx ", m->synd);
194 pr_cont("IPID %llx ", m->ipid);
200 * Note this output is parsed by external tools and old fields
201 * should not be changed.
203 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
204 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
208 static void print_mce(struct mce *m)
212 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
213 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
216 #define PANIC_TIMEOUT 5 /* 5 seconds */
218 static atomic_t mce_panicked;
220 static int fake_panic;
221 static atomic_t mce_fake_panicked;
223 /* Panic in progress. Enable interrupts and wait for final IPI */
224 static void wait_for_panic(void)
226 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
230 while (timeout-- > 0)
232 if (panic_timeout == 0)
233 panic_timeout = mca_cfg.panic_timeout;
234 panic("Panicing machine check CPU died");
237 static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
239 struct llist_node *pending;
240 struct mce_evt_llist *l;
244 * Allow instrumentation around external facilities usage. Not that it
245 * matters a whole lot since the machine is going to panic anyway.
247 instrumentation_begin();
251 * Make sure only one CPU runs in machine check panic
253 if (atomic_inc_return(&mce_panicked) > 1)
260 /* Don't log too much for fake panic */
261 if (atomic_inc_return(&mce_fake_panicked) > 1)
264 pending = mce_gen_pool_prepare_records();
265 /* First print corrected ones that are still unlogged */
266 llist_for_each_entry(l, pending, llnode) {
267 struct mce *m = &l->mce;
268 if (!(m->status & MCI_STATUS_UC)) {
271 apei_err = apei_write_mce(m);
274 /* Now print uncorrected but with the final one last */
275 llist_for_each_entry(l, pending, llnode) {
276 struct mce *m = &l->mce;
277 if (!(m->status & MCI_STATUS_UC))
279 if (!final || mce_cmp(m, final)) {
282 apei_err = apei_write_mce(m);
288 apei_err = apei_write_mce(final);
291 pr_emerg(HW_ERR "Machine check: %s\n", exp);
293 if (panic_timeout == 0)
294 panic_timeout = mca_cfg.panic_timeout;
297 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
300 instrumentation_end();
303 /* Support code for software error injection */
305 static int msr_to_offset(u32 msr)
307 unsigned bank = __this_cpu_read(injectm.bank);
309 if (msr == mca_cfg.rip_msr)
310 return offsetof(struct mce, ip);
311 if (msr == mca_msr_reg(bank, MCA_STATUS))
312 return offsetof(struct mce, status);
313 if (msr == mca_msr_reg(bank, MCA_ADDR))
314 return offsetof(struct mce, addr);
315 if (msr == mca_msr_reg(bank, MCA_MISC))
316 return offsetof(struct mce, misc);
317 if (msr == MSR_IA32_MCG_STATUS)
318 return offsetof(struct mce, mcgstatus);
322 void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
325 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
326 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
327 regs->ip, (void *)regs->ip);
329 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
330 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
333 show_stack_regs(regs);
335 panic("MCA architectural violation!\n");
341 /* MSR access wrappers used for error injection */
342 noinstr u64 mce_rdmsrl(u32 msr)
344 DECLARE_ARGS(val, low, high);
346 if (__this_cpu_read(injectm.finished)) {
350 instrumentation_begin();
352 offset = msr_to_offset(msr);
356 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
358 instrumentation_end();
364 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
365 * architectural violation and needs to be reported to hw vendor. Panic
366 * the box to not allow any further progress.
368 asm volatile("1: rdmsr\n"
370 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE)
371 : EAX_EDX_RET(val, low, high) : "c" (msr));
374 return EAX_EDX_VAL(val, low, high);
377 static noinstr void mce_wrmsrl(u32 msr, u64 v)
381 if (__this_cpu_read(injectm.finished)) {
384 instrumentation_begin();
386 offset = msr_to_offset(msr);
388 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
390 instrumentation_end();
396 high = (u32)(v >> 32);
398 /* See comment in mce_rdmsrl() */
399 asm volatile("1: wrmsr\n"
401 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE)
402 : : "c" (msr), "a"(low), "d" (high) : "memory");
406 * Collect all global (w.r.t. this processor) status about this machine
407 * check into our "mce" struct so that we can use it later to assess
408 * the severity of the problem as we read per-bank specific details.
410 static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs)
413 * Enable instrumentation around mce_setup() which calls external
416 instrumentation_begin();
418 instrumentation_end();
420 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
423 * Get the address of the instruction at the time of
424 * the machine check error.
426 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
431 * When in VM86 mode make the cs look like ring 3
432 * always. This is a lie, but it's better than passing
433 * the additional vm86 bit around everywhere.
435 if (v8086_mode(regs))
438 /* Use accurate RIP reporting if available. */
440 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
444 int mce_available(struct cpuinfo_x86 *c)
446 if (mca_cfg.disabled)
448 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
451 static void mce_schedule_work(void)
453 if (!mce_gen_pool_empty())
454 schedule_work(&mce_work);
457 static void mce_irq_work_cb(struct irq_work *entry)
463 * Check if the address reported by the CPU is in a format we can parse.
464 * It would be possible to add code for most other cases, but all would
465 * be somewhat complicated (e.g. segment offset would require an instruction
466 * parser). So only support physical addresses up to page granularity for now.
468 int mce_usable_address(struct mce *m)
470 if (!(m->status & MCI_STATUS_ADDRV))
473 /* Checks after this one are Intel/Zhaoxin-specific: */
474 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
475 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
478 if (!(m->status & MCI_STATUS_MISCV))
481 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
484 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
489 EXPORT_SYMBOL_GPL(mce_usable_address);
491 bool mce_is_memory_error(struct mce *m)
493 switch (m->cpuvendor) {
495 case X86_VENDOR_HYGON:
496 return amd_mce_is_memory_error(m);
498 case X86_VENDOR_INTEL:
499 case X86_VENDOR_ZHAOXIN:
501 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
503 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
504 * indicating a memory error. Bit 8 is used for indicating a
505 * cache hierarchy error. The combination of bit 2 and bit 3
506 * is used for indicating a `generic' cache hierarchy error
507 * But we can't just blindly check the above bits, because if
508 * bit 11 is set, then it is a bus/interconnect error - and
509 * either way the above bits just gives more detail on what
510 * bus/interconnect error happened. Note that bit 12 can be
511 * ignored, as it's the "filter" bit.
513 return (m->status & 0xef80) == BIT(7) ||
514 (m->status & 0xef00) == BIT(8) ||
515 (m->status & 0xeffc) == 0xc;
521 EXPORT_SYMBOL_GPL(mce_is_memory_error);
523 static bool whole_page(struct mce *m)
525 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
528 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
531 bool mce_is_correctable(struct mce *m)
533 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
536 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
539 if (m->status & MCI_STATUS_UC)
544 EXPORT_SYMBOL_GPL(mce_is_correctable);
546 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
549 struct mce *m = (struct mce *)data;
554 /* Emit the trace record: */
557 set_bit(0, &mce_need_notify);
564 static struct notifier_block early_nb = {
565 .notifier_call = mce_early_notifier,
566 .priority = MCE_PRIO_EARLY,
569 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
572 struct mce *mce = (struct mce *)data;
575 if (!mce || !mce_usable_address(mce))
578 if (mce->severity != MCE_AO_SEVERITY &&
579 mce->severity != MCE_DEFERRED_SEVERITY)
582 pfn = mce->addr >> PAGE_SHIFT;
583 if (!memory_failure(pfn, 0)) {
585 mce->kflags |= MCE_HANDLED_UC;
591 static struct notifier_block mce_uc_nb = {
592 .notifier_call = uc_decode_notifier,
593 .priority = MCE_PRIO_UC,
596 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
599 struct mce *m = (struct mce *)data;
604 if (mca_cfg.print_all || !m->kflags)
610 static struct notifier_block mce_default_nb = {
611 .notifier_call = mce_default_notifier,
612 /* lowest prio, we want it to run last. */
613 .priority = MCE_PRIO_LOWEST,
617 * Read ADDR and MISC registers.
619 static noinstr void mce_read_aux(struct mce *m, int i)
621 if (m->status & MCI_STATUS_MISCV)
622 m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC));
624 if (m->status & MCI_STATUS_ADDRV) {
625 m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR));
628 * Mask the reported address by the reported granularity.
630 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
631 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
637 * Extract [55:<lsb>] where lsb is the least significant
638 * *valid* bit of the address bits.
640 if (mce_flags.smca) {
641 u8 lsb = (m->addr >> 56) & 0x3f;
643 m->addr &= GENMASK_ULL(55, lsb);
647 if (mce_flags.smca) {
648 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
650 if (m->status & MCI_STATUS_SYNDV)
651 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
655 DEFINE_PER_CPU(unsigned, mce_poll_count);
658 * Poll for corrected events or events that happened before reset.
659 * Those are just logged through /dev/mcelog.
661 * This is executed in standard interrupt context.
663 * Note: spec recommends to panic for fatal unsignalled
664 * errors here. However this would be quite problematic --
665 * we would need to reimplement the Monarch handling and
666 * it would mess up the exclusion between exception handler
667 * and poll handler -- * so we skip this for now.
668 * These cases should not happen anyways, or only when the CPU
669 * is already totally * confused. In this case it's likely it will
670 * not fully execute the machine check handler either.
672 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
674 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
675 bool error_seen = false;
679 this_cpu_inc(mce_poll_count);
681 mce_gather_info(&m, NULL);
683 if (flags & MCP_TIMESTAMP)
686 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
687 if (!mce_banks[i].ctl || !test_bit(i, *b))
695 m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
697 /* If this entry is not valid, ignore it */
698 if (!(m.status & MCI_STATUS_VAL))
702 * If we are logging everything (at CPU online) or this
703 * is a corrected error, then we must log it.
705 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
709 * Newer Intel systems that support software error
710 * recovery need to make additional checks. Other
711 * CPUs should skip over uncorrected errors, but log
715 if (m.status & MCI_STATUS_UC)
720 /* Log "not enabled" (speculative) errors */
721 if (!(m.status & MCI_STATUS_EN))
725 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
726 * UC == 1 && PCC == 0 && S == 0
728 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
732 * Skip anything else. Presumption is that our read of this
733 * bank is racing with a machine check. Leave the log alone
734 * for do_machine_check() to deal with it.
741 if (flags & MCP_DONTLOG)
745 m.severity = mce_severity(&m, NULL, NULL, false);
747 * Don't get the IP here because it's unlikely to
748 * have anything to do with the actual error location.
751 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
754 if (flags & MCP_QUEUE_LOG)
755 mce_gen_pool_add(&m);
761 * Clear state for this bank.
763 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
767 * Don't clear MCG_STATUS here because it's only defined for
775 EXPORT_SYMBOL_GPL(machine_check_poll);
778 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
779 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
780 * Vol 3B Table 15-20). But this confuses both the code that determines
781 * whether the machine check occurred in kernel or user mode, and also
782 * the severity assessment code. Pretend that EIPV was set, and take the
783 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
785 static __always_inline void
786 quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
790 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
792 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
793 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
794 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
796 (MCI_STATUS_UC|MCI_STATUS_EN|
797 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
798 MCI_STATUS_AR|MCACOD_INSTR))
801 m->mcgstatus |= MCG_STATUS_EIPV;
807 * Disable fast string copy and return from the MCE handler upon the first SRAR
808 * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake
810 * The fast string copy instructions ("REP; MOVS*") could consume an
811 * uncorrectable memory error in the cache line _right after_ the desired region
812 * to copy and raise an MCE with RIP pointing to the instruction _after_ the
814 * This mitigation addresses the issue completely with the caveat of performance
815 * degradation on the CPU affected. This is still better than the OS crashing on
816 * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a
817 * kernel context (e.g., copy_page).
819 * Returns true when fast string copy on CPU has been disabled.
821 static noinstr bool quirk_skylake_repmov(void)
823 u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
824 u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE);
828 * Apply the quirk only to local machine checks, i.e., no broadcast
831 if (!(mcgstatus & MCG_STATUS_LMCES) ||
832 !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING))
835 mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1));
837 /* Check for a software-recoverable data fetch error. */
839 (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN |
840 MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC |
841 MCI_STATUS_AR | MCI_STATUS_S)) ==
842 (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
843 MCI_STATUS_ADDRV | MCI_STATUS_MISCV |
844 MCI_STATUS_AR | MCI_STATUS_S)) {
845 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
846 mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
847 mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0);
849 instrumentation_begin();
850 pr_err_once("Erratum detected, disable fast string copy instructions.\n");
851 instrumentation_end();
860 * Do a quick check if any of the events requires a panic.
861 * This decides if we keep the events around or clear them.
863 static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
864 struct pt_regs *regs)
869 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
870 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
871 if (!(m->status & MCI_STATUS_VAL))
874 arch___set_bit(i, validp);
875 if (mce_flags.snb_ifu_quirk)
876 quirk_sandybridge_ifu(i, m, regs);
879 if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
889 * Variable to establish order between CPUs while scanning.
890 * Each CPU spins initially until executing is equal its number.
892 static atomic_t mce_executing;
895 * Defines order of CPUs on entry. First CPU becomes Monarch.
897 static atomic_t mce_callin;
900 * Track which CPUs entered the MCA broadcast synchronization and which not in
901 * order to print holdouts.
903 static cpumask_t mce_missing_cpus = CPU_MASK_ALL;
906 * Check if a timeout waiting for other CPUs happened.
908 static noinstr int mce_timed_out(u64 *t, const char *msg)
912 /* Enable instrumentation around calls to external facilities */
913 instrumentation_begin();
916 * The others already did panic for some reason.
917 * Bail out like in a timeout.
918 * rmb() to tell the compiler that system_state
919 * might have been modified by someone else.
922 if (atomic_read(&mce_panicked))
924 if (!mca_cfg.monarch_timeout)
926 if ((s64)*t < SPINUNIT) {
927 if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus))
928 pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n",
929 cpumask_pr_args(&mce_missing_cpus));
930 mce_panic(msg, NULL, NULL);
938 touch_nmi_watchdog();
940 instrumentation_end();
946 * The Monarch's reign. The Monarch is the CPU who entered
947 * the machine check handler first. It waits for the others to
948 * raise the exception too and then grades them. When any
949 * error is fatal panic. Only then let the others continue.
951 * The other CPUs entering the MCE handler will be controlled by the
952 * Monarch. They are called Subjects.
954 * This way we prevent any potential data corruption in a unrecoverable case
955 * and also makes sure always all CPU's errors are examined.
957 * Also this detects the case of a machine check event coming from outer
958 * space (not detected by any CPUs) In this case some external agent wants
959 * us to shut down, so panic too.
961 * The other CPUs might still decide to panic if the handler happens
962 * in a unrecoverable place, but in this case the system is in a semi-stable
963 * state and won't corrupt anything by itself. It's ok to let the others
964 * continue for a bit first.
966 * All the spin loops have timeouts; when a timeout happens a CPU
967 * typically elects itself to be Monarch.
969 static void mce_reign(void)
972 struct mce *m = NULL;
973 int global_worst = 0;
977 * This CPU is the Monarch and the other CPUs have run
978 * through their handlers.
979 * Grade the severity of the errors of all the CPUs.
981 for_each_possible_cpu(cpu) {
982 struct mce *mtmp = &per_cpu(mces_seen, cpu);
984 if (mtmp->severity > global_worst) {
985 global_worst = mtmp->severity;
986 m = &per_cpu(mces_seen, cpu);
991 * Cannot recover? Panic here then.
992 * This dumps all the mces in the log buffer and stops the
995 if (m && global_worst >= MCE_PANIC_SEVERITY) {
996 /* call mce_severity() to get "msg" for panic */
997 mce_severity(m, NULL, &msg, true);
998 mce_panic("Fatal machine check", m, msg);
1002 * For UC somewhere we let the CPU who detects it handle it.
1003 * Also must let continue the others, otherwise the handling
1004 * CPU could deadlock on a lock.
1008 * No machine check event found. Must be some external
1009 * source or one CPU is hung. Panic.
1011 if (global_worst <= MCE_KEEP_SEVERITY)
1012 mce_panic("Fatal machine check from unknown source", NULL, NULL);
1015 * Now clear all the mces_seen so that they don't reappear on
1018 for_each_possible_cpu(cpu)
1019 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
1022 static atomic_t global_nwo;
1025 * Start of Monarch synchronization. This waits until all CPUs have
1026 * entered the exception handler and then determines if any of them
1027 * saw a fatal event that requires panic. Then it executes them
1028 * in the entry order.
1029 * TBD double check parallel CPU hotunplug
1031 static noinstr int mce_start(int *no_way_out)
1033 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1034 int order, ret = -1;
1039 arch_atomic_add(*no_way_out, &global_nwo);
1041 * Rely on the implied barrier below, such that global_nwo
1042 * is updated before mce_callin.
1044 order = arch_atomic_inc_return(&mce_callin);
1045 arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus);
1047 /* Enable instrumentation around calls to external facilities */
1048 instrumentation_begin();
1051 * Wait for everyone.
1053 while (arch_atomic_read(&mce_callin) != num_online_cpus()) {
1054 if (mce_timed_out(&timeout,
1055 "Timeout: Not all CPUs entered broadcast exception handler")) {
1056 arch_atomic_set(&global_nwo, 0);
1063 * mce_callin should be read before global_nwo
1069 * Monarch: Starts executing now, the others wait.
1071 arch_atomic_set(&mce_executing, 1);
1074 * Subject: Now start the scanning loop one by one in
1075 * the original callin order.
1076 * This way when there are any shared banks it will be
1077 * only seen by one CPU before cleared, avoiding duplicates.
1079 while (arch_atomic_read(&mce_executing) < order) {
1080 if (mce_timed_out(&timeout,
1081 "Timeout: Subject CPUs unable to finish machine check processing")) {
1082 arch_atomic_set(&global_nwo, 0);
1090 * Cache the global no_way_out state.
1092 *no_way_out = arch_atomic_read(&global_nwo);
1097 instrumentation_end();
1103 * Synchronize between CPUs after main scanning loop.
1104 * This invokes the bulk of the Monarch processing.
1106 static noinstr int mce_end(int order)
1108 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1111 /* Allow instrumentation around external facilities. */
1112 instrumentation_begin();
1120 * Allow others to run.
1122 atomic_inc(&mce_executing);
1126 * Monarch: Wait for everyone to go through their scanning
1129 while (atomic_read(&mce_executing) <= num_online_cpus()) {
1130 if (mce_timed_out(&timeout,
1131 "Timeout: Monarch CPU unable to finish machine check processing"))
1141 * Subject: Wait for Monarch to finish.
1143 while (atomic_read(&mce_executing) != 0) {
1144 if (mce_timed_out(&timeout,
1145 "Timeout: Monarch CPU did not finish machine check processing"))
1151 * Don't reset anything. That's done by the Monarch.
1158 * Reset all global state.
1161 atomic_set(&global_nwo, 0);
1162 atomic_set(&mce_callin, 0);
1163 cpumask_setall(&mce_missing_cpus);
1167 * Let others run again.
1169 atomic_set(&mce_executing, 0);
1172 instrumentation_end();
1177 static __always_inline void mce_clear_state(unsigned long *toclear)
1181 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1182 if (arch_test_bit(i, toclear))
1183 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1188 * Cases where we avoid rendezvous handler timeout:
1189 * 1) If this CPU is offline.
1191 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1192 * skip those CPUs which remain looping in the 1st kernel - see
1193 * crash_nmi_callback().
1195 * Note: there still is a small window between kexec-ing and the new,
1196 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1197 * might not get handled properly.
1199 static noinstr bool mce_check_crashing_cpu(void)
1201 unsigned int cpu = smp_processor_id();
1203 if (arch_cpu_is_offline(cpu) ||
1204 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1207 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1209 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1210 if (mcgstatus & MCG_STATUS_LMCES)
1214 if (mcgstatus & MCG_STATUS_RIPV) {
1215 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1222 static __always_inline int
1223 __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1224 unsigned long *toclear, unsigned long *valid_banks, int no_way_out,
1227 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1228 struct mca_config *cfg = &mca_cfg;
1229 int severity, i, taint = 0;
1231 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1232 arch___clear_bit(i, toclear);
1233 if (!arch_test_bit(i, valid_banks))
1236 if (!mce_banks[i].ctl)
1243 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
1244 if (!(m->status & MCI_STATUS_VAL))
1248 * Corrected or non-signaled errors are handled by
1249 * machine_check_poll(). Leave them alone, unless this panics.
1251 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1255 /* Set taint even when machine check was not enabled. */
1258 severity = mce_severity(m, regs, NULL, true);
1261 * When machine check was for corrected/deferred handler don't
1262 * touch, unless we're panicking.
1264 if ((severity == MCE_KEEP_SEVERITY ||
1265 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1268 arch___set_bit(i, toclear);
1270 /* Machine check event was not enabled. Clear, but ignore. */
1271 if (severity == MCE_NO_SEVERITY)
1276 /* assuming valid severity level != 0 */
1277 m->severity = severity;
1280 * Enable instrumentation around the mce_log() call which is
1281 * done in #MC context, where instrumentation is disabled.
1283 instrumentation_begin();
1285 instrumentation_end();
1287 if (severity > *worst) {
1293 /* mce_clear_state will clear *final, save locally for use later */
1299 static void kill_me_now(struct callback_head *ch)
1301 struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me);
1307 static void kill_me_maybe(struct callback_head *cb)
1309 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1310 int flags = MF_ACTION_REQUIRED;
1314 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1317 flags |= MF_MUST_KILL;
1319 ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags);
1321 set_mce_nospec(p->mce_addr >> PAGE_SHIFT);
1327 * -EHWPOISON from memory_failure() means that it already sent SIGBUS
1328 * to the current process with the proper error info,
1329 * -EOPNOTSUPP means hwpoison_filter() filtered the error event,
1331 * In both cases, no further processing is required.
1333 if (ret == -EHWPOISON || ret == -EOPNOTSUPP)
1336 pr_err("Memory error not recovered");
1340 static void kill_me_never(struct callback_head *cb)
1342 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1345 pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr);
1346 if (!memory_failure(p->mce_addr >> PAGE_SHIFT, 0))
1347 set_mce_nospec(p->mce_addr >> PAGE_SHIFT);
1350 static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *))
1352 int count = ++current->mce_count;
1354 /* First call, save all the details */
1356 current->mce_addr = m->addr;
1357 current->mce_kflags = m->kflags;
1358 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1359 current->mce_whole_page = whole_page(m);
1360 current->mce_kill_me.func = func;
1363 /* Ten is likely overkill. Don't expect more than two faults before task_work() */
1365 mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
1367 /* Second or later call, make sure page address matches the one from first call */
1368 if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
1369 mce_panic("Consecutive machine checks to different user pages", m, msg);
1371 /* Do not call task_work_add() more than once */
1375 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1378 /* Handle unconfigured int18 (should never happen) */
1379 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1381 instrumentation_begin();
1382 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1383 smp_processor_id());
1384 instrumentation_end();
1388 * The actual machine check handler. This only handles real exceptions when
1389 * something got corrupted coming in through int 18.
1391 * This is executed in #MC context not subject to normal locking rules.
1392 * This implies that most kernel services cannot be safely used. Don't even
1393 * think about putting a printk in there!
1395 * On Intel systems this is entered on all CPUs in parallel through
1396 * MCE broadcast. However some CPUs might be broken beyond repair,
1397 * so be always careful when synchronizing with others.
1399 * Tracing and kprobes are disabled: if we interrupted a kernel context
1400 * with IF=1, we need to minimize stack usage. There are also recursion
1401 * issues: if the machine check was due to a failure of the memory
1402 * backing the user stack, tracing that reads the user stack will cause
1403 * potentially infinite recursion.
1405 * Currently, the #MC handler calls out to a number of external facilities
1406 * and, therefore, allows instrumentation around them. The optimal thing to
1407 * have would be to do the absolutely minimal work required in #MC context
1408 * and have instrumentation disabled only around that. Further processing can
1409 * then happen in process context where instrumentation is allowed. Achieving
1410 * that requires careful auditing and modifications. Until then, the code
1411 * allows instrumentation temporarily, where required. *
1413 noinstr void do_machine_check(struct pt_regs *regs)
1415 int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0;
1416 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 };
1417 DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 };
1418 struct mce m, *final;
1421 if (unlikely(mce_flags.p5))
1422 return pentium_machine_check(regs);
1423 else if (unlikely(mce_flags.winchip))
1424 return winchip_machine_check(regs);
1425 else if (unlikely(!mca_cfg.initialized))
1426 return unexpected_machine_check(regs);
1428 if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov())
1432 * Establish sequential order between the CPUs entering the machine
1438 * If no_way_out gets set, there is no safe way to recover from this
1444 * If kill_current_task is not set, there might be a way to recover from this
1447 kill_current_task = 0;
1450 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1455 this_cpu_inc(mce_exception_count);
1457 mce_gather_info(&m, regs);
1460 final = this_cpu_ptr(&mces_seen);
1463 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1468 * When no restart IP might need to kill or panic.
1469 * Assume the worst for now, but if we find the
1470 * severity is MCE_AR_SEVERITY we have other options.
1472 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1473 kill_current_task = 1;
1475 * Check if this MCE is signaled to only this logical processor,
1476 * on Intel, Zhaoxin only.
1478 if (m.cpuvendor == X86_VENDOR_INTEL ||
1479 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1480 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1483 * Local machine check may already know that we have to panic.
1484 * Broadcast machine check begins rendezvous in mce_start()
1485 * Go through all banks in exclusion of the other CPUs. This way we
1486 * don't report duplicated events on shared banks because the first one
1487 * to see it will clear it.
1491 mce_panic("Fatal local machine check", &m, msg);
1493 order = mce_start(&no_way_out);
1496 taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1499 mce_clear_state(toclear);
1502 * Do most of the synchronization with other CPUs.
1503 * When there's any problem use only local no_way_out state.
1506 if (mce_end(order) < 0) {
1508 no_way_out = worst >= MCE_PANIC_SEVERITY;
1511 mce_panic("Fatal machine check on current CPU", &m, msg);
1515 * If there was a fatal machine check we should have
1516 * already called mce_panic earlier in this function.
1517 * Since we re-read the banks, we might have found
1518 * something new. Check again to see if we found a
1519 * fatal error. We call "mce_severity()" again to
1520 * make sure we have the right "msg".
1522 if (worst >= MCE_PANIC_SEVERITY) {
1523 mce_severity(&m, regs, &msg, true);
1524 mce_panic("Local fatal machine check!", &m, msg);
1529 * Enable instrumentation around the external facilities like task_work_add()
1530 * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this
1531 * properly would need a lot more involved reorganization.
1533 instrumentation_begin();
1536 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1538 if (worst != MCE_AR_SEVERITY && !kill_current_task)
1541 /* Fault was in user mode and we need to take some action */
1542 if ((m.cs & 3) == 3) {
1543 /* If this triggers there is no way to recover. Die hard. */
1544 BUG_ON(!on_thread_stack() || !user_mode(regs));
1546 if (kill_current_task)
1547 queue_task_work(&m, msg, kill_me_now);
1549 queue_task_work(&m, msg, kill_me_maybe);
1553 * Handle an MCE which has happened in kernel space but from
1554 * which the kernel can recover: ex_has_fault_handler() has
1555 * already verified that the rIP at which the error happened is
1556 * a rIP from which the kernel can recover (by jumping to
1557 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1558 * corresponding exception handler which would do that is the
1561 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1562 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1563 mce_panic("Failed kernel mode recovery", &m, msg);
1566 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1567 queue_task_work(&m, msg, kill_me_never);
1571 instrumentation_end();
1574 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1576 EXPORT_SYMBOL_GPL(do_machine_check);
1578 #ifndef CONFIG_MEMORY_FAILURE
1579 int memory_failure(unsigned long pfn, int flags)
1581 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1582 BUG_ON(flags & MF_ACTION_REQUIRED);
1583 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1584 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1592 * Periodic polling timer for "silent" machine check errors. If the
1593 * poller finds an MCE, poll 2x faster. When the poller finds no more
1594 * errors, poll 2x slower (up to check_interval seconds).
1596 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1598 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1599 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1601 static unsigned long mce_adjust_timer_default(unsigned long interval)
1606 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1608 static void __start_timer(struct timer_list *t, unsigned long interval)
1610 unsigned long when = jiffies + interval;
1611 unsigned long flags;
1613 local_irq_save(flags);
1615 if (!timer_pending(t) || time_before(when, t->expires))
1616 mod_timer(t, round_jiffies(when));
1618 local_irq_restore(flags);
1621 static void mce_timer_fn(struct timer_list *t)
1623 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1626 WARN_ON(cpu_t != t);
1628 iv = __this_cpu_read(mce_next_interval);
1630 if (mce_available(this_cpu_ptr(&cpu_info))) {
1631 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1633 if (mce_intel_cmci_poll()) {
1634 iv = mce_adjust_timer(iv);
1640 * Alert userspace if needed. If we logged an MCE, reduce the polling
1641 * interval, otherwise increase the polling interval.
1643 if (mce_notify_irq())
1644 iv = max(iv / 2, (unsigned long) HZ/100);
1646 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1649 __this_cpu_write(mce_next_interval, iv);
1650 __start_timer(t, iv);
1654 * Ensure that the timer is firing in @interval from now.
1656 void mce_timer_kick(unsigned long interval)
1658 struct timer_list *t = this_cpu_ptr(&mce_timer);
1659 unsigned long iv = __this_cpu_read(mce_next_interval);
1661 __start_timer(t, interval);
1664 __this_cpu_write(mce_next_interval, interval);
1667 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1668 static void mce_timer_delete_all(void)
1672 for_each_online_cpu(cpu)
1673 del_timer_sync(&per_cpu(mce_timer, cpu));
1677 * Notify the user(s) about new machine check events.
1678 * Can be called from interrupt context, but not from machine check/NMI
1681 int mce_notify_irq(void)
1683 /* Not more than two messages every minute */
1684 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1686 if (test_and_clear_bit(0, &mce_need_notify)) {
1689 if (__ratelimit(&ratelimit))
1690 pr_info(HW_ERR "Machine check events logged\n");
1696 EXPORT_SYMBOL_GPL(mce_notify_irq);
1698 static void __mcheck_cpu_mce_banks_init(void)
1700 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1701 u8 n_banks = this_cpu_read(mce_num_banks);
1704 for (i = 0; i < n_banks; i++) {
1705 struct mce_bank *b = &mce_banks[i];
1708 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1709 * the required vendor quirks before
1710 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1718 * Initialize Machine Checks for a CPU.
1720 static void __mcheck_cpu_cap_init(void)
1725 rdmsrl(MSR_IA32_MCG_CAP, cap);
1727 b = cap & MCG_BANKCNT_MASK;
1729 if (b > MAX_NR_BANKS) {
1730 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1731 smp_processor_id(), MAX_NR_BANKS, b);
1735 this_cpu_write(mce_num_banks, b);
1737 __mcheck_cpu_mce_banks_init();
1739 /* Use accurate RIP reporting if available. */
1740 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1741 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1743 if (cap & MCG_SER_P)
1747 static void __mcheck_cpu_init_generic(void)
1749 enum mcp_flags m_fl = 0;
1750 mce_banks_t all_banks;
1753 if (!mca_cfg.bootlog)
1757 * Log the machine checks left over from the previous reset. Log them
1758 * only, do not start processing them. That will happen in mcheck_late_init()
1759 * when all consumers have been registered on the notifier chain.
1761 bitmap_fill(all_banks, MAX_NR_BANKS);
1762 machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks);
1764 cr4_set_bits(X86_CR4_MCE);
1766 rdmsrl(MSR_IA32_MCG_CAP, cap);
1767 if (cap & MCG_CTL_P)
1768 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1771 static void __mcheck_cpu_init_clear_banks(void)
1773 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1776 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1777 struct mce_bank *b = &mce_banks[i];
1781 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
1782 wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1787 * Do a final check to see if there are any unused/RAZ banks.
1789 * This must be done after the banks have been initialized and any quirks have
1792 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1793 * Otherwise, a user who disables a bank will not be able to re-enable it
1794 * without a system reboot.
1796 static void __mcheck_cpu_check_banks(void)
1798 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1802 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1803 struct mce_bank *b = &mce_banks[i];
1808 rdmsrl(mca_msr_reg(i, MCA_CTL), msrval);
1813 /* Add per CPU specific workarounds here */
1814 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1816 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1817 struct mca_config *cfg = &mca_cfg;
1819 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1820 pr_info("unknown CPU type - not enabling MCE support\n");
1824 /* This should be disabled by the BIOS, but isn't always */
1825 if (c->x86_vendor == X86_VENDOR_AMD) {
1826 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1828 * disable GART TBL walk error reporting, which
1829 * trips off incorrectly with the IOMMU & 3ware
1832 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1834 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1836 * Lots of broken BIOS around that don't clear them
1837 * by default and leave crap in there. Don't log:
1842 * Various K7s with broken bank 0 around. Always disable
1845 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1846 mce_banks[0].ctl = 0;
1849 * overflow_recov is supported for F15h Models 00h-0fh
1850 * even though we don't have a CPUID bit for it.
1852 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1853 mce_flags.overflow_recov = 1;
1857 if (c->x86_vendor == X86_VENDOR_INTEL) {
1859 * SDM documents that on family 6 bank 0 should not be written
1860 * because it aliases to another special BIOS controlled
1862 * But it's not aliased anymore on model 0x1a+
1863 * Don't ignore bank 0 completely because there could be a
1864 * valid event later, merely don't write CTL0.
1867 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1868 mce_banks[0].init = false;
1871 * All newer Intel systems support MCE broadcasting. Enable
1872 * synchronization with a one second timeout.
1874 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1875 cfg->monarch_timeout < 0)
1876 cfg->monarch_timeout = USEC_PER_SEC;
1879 * There are also broken BIOSes on some Pentium M and
1882 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1885 if (c->x86 == 6 && c->x86_model == 45)
1886 mce_flags.snb_ifu_quirk = 1;
1889 * Skylake, Cascacde Lake and Cooper Lake require a quirk on
1892 if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X)
1893 mce_flags.skx_repmov_quirk = 1;
1896 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1898 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1899 * synchronization with a one second timeout.
1901 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1902 if (cfg->monarch_timeout < 0)
1903 cfg->monarch_timeout = USEC_PER_SEC;
1907 if (cfg->monarch_timeout < 0)
1908 cfg->monarch_timeout = 0;
1909 if (cfg->bootlog != 0)
1910 cfg->panic_timeout = 30;
1915 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1920 switch (c->x86_vendor) {
1921 case X86_VENDOR_INTEL:
1922 intel_p5_mcheck_init(c);
1925 case X86_VENDOR_CENTAUR:
1926 winchip_mcheck_init(c);
1927 mce_flags.winchip = 1;
1937 * Init basic CPU features needed for early decoding of MCEs.
1939 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1941 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1942 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1943 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1944 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1945 mce_flags.amd_threshold = 1;
1949 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1951 struct mca_config *cfg = &mca_cfg;
1954 * All newer Centaur CPUs support MCE broadcasting. Enable
1955 * synchronization with a one second timeout.
1957 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1959 if (cfg->monarch_timeout < 0)
1960 cfg->monarch_timeout = USEC_PER_SEC;
1964 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1966 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1969 * These CPUs have MCA bank 8 which reports only one error type called
1970 * SVAD (System View Address Decoder). The reporting of that error is
1971 * controlled by IA32_MC8.CTL.0.
1973 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1974 * virtual machines start and result in a system panic. Always disable
1975 * bank 8 SVAD error by default.
1977 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1978 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1979 if (this_cpu_read(mce_num_banks) > 8)
1980 mce_banks[8].ctl = 0;
1985 mce_adjust_timer = cmci_intel_adjust_timer;
1988 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1993 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1995 switch (c->x86_vendor) {
1996 case X86_VENDOR_INTEL:
1997 mce_intel_feature_init(c);
1998 mce_adjust_timer = cmci_intel_adjust_timer;
2001 case X86_VENDOR_AMD: {
2002 mce_amd_feature_init(c);
2006 case X86_VENDOR_HYGON:
2007 mce_hygon_feature_init(c);
2010 case X86_VENDOR_CENTAUR:
2011 mce_centaur_feature_init(c);
2014 case X86_VENDOR_ZHAOXIN:
2015 mce_zhaoxin_feature_init(c);
2023 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
2025 switch (c->x86_vendor) {
2026 case X86_VENDOR_INTEL:
2027 mce_intel_feature_clear(c);
2030 case X86_VENDOR_ZHAOXIN:
2031 mce_zhaoxin_feature_clear(c);
2039 static void mce_start_timer(struct timer_list *t)
2041 unsigned long iv = check_interval * HZ;
2043 if (mca_cfg.ignore_ce || !iv)
2046 this_cpu_write(mce_next_interval, iv);
2047 __start_timer(t, iv);
2050 static void __mcheck_cpu_setup_timer(void)
2052 struct timer_list *t = this_cpu_ptr(&mce_timer);
2054 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2057 static void __mcheck_cpu_init_timer(void)
2059 struct timer_list *t = this_cpu_ptr(&mce_timer);
2061 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2065 bool filter_mce(struct mce *m)
2067 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
2068 return amd_filter_mce(m);
2069 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2070 return intel_filter_mce(m);
2075 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
2077 irqentry_state_t irq_state;
2079 WARN_ON_ONCE(user_mode(regs));
2082 * Only required when from kernel mode. See
2083 * mce_check_crashing_cpu() for details.
2085 if (mca_cfg.initialized && mce_check_crashing_cpu())
2088 irq_state = irqentry_nmi_enter(regs);
2090 do_machine_check(regs);
2092 irqentry_nmi_exit(regs, irq_state);
2095 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2097 irqentry_enter_from_user_mode(regs);
2099 do_machine_check(regs);
2101 irqentry_exit_to_user_mode(regs);
2104 #ifdef CONFIG_X86_64
2105 /* MCE hit kernel mode */
2106 DEFINE_IDTENTRY_MCE(exc_machine_check)
2110 dr7 = local_db_save();
2111 exc_machine_check_kernel(regs);
2112 local_db_restore(dr7);
2115 /* The user mode variant. */
2116 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2120 dr7 = local_db_save();
2121 exc_machine_check_user(regs);
2122 local_db_restore(dr7);
2125 /* 32bit unified entry point */
2126 DEFINE_IDTENTRY_RAW(exc_machine_check)
2130 dr7 = local_db_save();
2131 if (user_mode(regs))
2132 exc_machine_check_user(regs);
2134 exc_machine_check_kernel(regs);
2135 local_db_restore(dr7);
2140 * Called for each booted CPU to set up machine checks.
2141 * Must be called with preempt off:
2143 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2145 if (mca_cfg.disabled)
2148 if (__mcheck_cpu_ancient_init(c))
2151 if (!mce_available(c))
2154 __mcheck_cpu_cap_init();
2156 if (__mcheck_cpu_apply_quirks(c) < 0) {
2157 mca_cfg.disabled = 1;
2161 if (mce_gen_pool_init()) {
2162 mca_cfg.disabled = 1;
2163 pr_emerg("Couldn't allocate MCE records pool!\n");
2167 mca_cfg.initialized = 1;
2169 __mcheck_cpu_init_early(c);
2170 __mcheck_cpu_init_generic();
2171 __mcheck_cpu_init_vendor(c);
2172 __mcheck_cpu_init_clear_banks();
2173 __mcheck_cpu_check_banks();
2174 __mcheck_cpu_setup_timer();
2178 * Called for each booted CPU to clear some machine checks opt-ins
2180 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2182 if (mca_cfg.disabled)
2185 if (!mce_available(c))
2189 * Possibly to clear general settings generic to x86
2190 * __mcheck_cpu_clear_generic(c);
2192 __mcheck_cpu_clear_vendor(c);
2196 static void __mce_disable_bank(void *arg)
2198 int bank = *((int *)arg);
2199 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2200 cmci_disable_bank(bank);
2203 void mce_disable_bank(int bank)
2205 if (bank >= this_cpu_read(mce_num_banks)) {
2207 "Ignoring request to disable invalid MCA bank %d.\n",
2211 set_bit(bank, mce_banks_ce_disabled);
2212 on_each_cpu(__mce_disable_bank, &bank, 1);
2216 * mce=off Disables machine check
2217 * mce=no_cmci Disables CMCI
2218 * mce=no_lmce Disables LMCE
2219 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2220 * mce=print_all Print all machine check logs to console
2221 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2222 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2223 * monarchtimeout is how long to wait for other CPUs on machine
2224 * check, or 0 to not wait
2225 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2227 * mce=nobootlog Don't log MCEs from before booting.
2228 * mce=bios_cmci_threshold Don't program the CMCI threshold
2229 * mce=recovery force enable copy_mc_fragile()
2231 static int __init mcheck_enable(char *str)
2233 struct mca_config *cfg = &mca_cfg;
2241 if (!strcmp(str, "off"))
2243 else if (!strcmp(str, "no_cmci"))
2244 cfg->cmci_disabled = true;
2245 else if (!strcmp(str, "no_lmce"))
2246 cfg->lmce_disabled = 1;
2247 else if (!strcmp(str, "dont_log_ce"))
2248 cfg->dont_log_ce = true;
2249 else if (!strcmp(str, "print_all"))
2250 cfg->print_all = true;
2251 else if (!strcmp(str, "ignore_ce"))
2252 cfg->ignore_ce = true;
2253 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2254 cfg->bootlog = (str[0] == 'b');
2255 else if (!strcmp(str, "bios_cmci_threshold"))
2256 cfg->bios_cmci_threshold = 1;
2257 else if (!strcmp(str, "recovery"))
2259 else if (isdigit(str[0]))
2260 get_option(&str, &(cfg->monarch_timeout));
2262 pr_info("mce argument %s ignored. Please use /sys\n", str);
2267 __setup("mce", mcheck_enable);
2269 int __init mcheck_init(void)
2271 mce_register_decode_chain(&early_nb);
2272 mce_register_decode_chain(&mce_uc_nb);
2273 mce_register_decode_chain(&mce_default_nb);
2275 INIT_WORK(&mce_work, mce_gen_pool_process);
2276 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2282 * mce_syscore: PM support
2286 * Disable machine checks on suspend and shutdown. We can't really handle
2289 static void mce_disable_error_reporting(void)
2291 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2294 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2295 struct mce_bank *b = &mce_banks[i];
2298 wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
2303 static void vendor_disable_error_reporting(void)
2306 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2307 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2308 * is bad, since it will inhibit reporting for all shared resources on
2309 * the socket like the last level cache (LLC), the integrated memory
2310 * controller (iMC), etc.
2312 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2313 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2314 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2315 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2318 mce_disable_error_reporting();
2321 static int mce_syscore_suspend(void)
2323 vendor_disable_error_reporting();
2327 static void mce_syscore_shutdown(void)
2329 vendor_disable_error_reporting();
2333 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2334 * Only one CPU is active at this time, the others get re-added later using
2337 static void mce_syscore_resume(void)
2339 __mcheck_cpu_init_generic();
2340 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2341 __mcheck_cpu_init_clear_banks();
2344 static struct syscore_ops mce_syscore_ops = {
2345 .suspend = mce_syscore_suspend,
2346 .shutdown = mce_syscore_shutdown,
2347 .resume = mce_syscore_resume,
2351 * mce_device: Sysfs support
2354 static void mce_cpu_restart(void *data)
2356 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2358 __mcheck_cpu_init_generic();
2359 __mcheck_cpu_init_clear_banks();
2360 __mcheck_cpu_init_timer();
2363 /* Reinit MCEs after user configuration changes */
2364 static void mce_restart(void)
2366 mce_timer_delete_all();
2367 on_each_cpu(mce_cpu_restart, NULL, 1);
2370 /* Toggle features for corrected errors */
2371 static void mce_disable_cmci(void *data)
2373 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2378 static void mce_enable_ce(void *all)
2380 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2385 __mcheck_cpu_init_timer();
2388 static struct bus_type mce_subsys = {
2389 .name = "machinecheck",
2390 .dev_name = "machinecheck",
2393 DEFINE_PER_CPU(struct device *, mce_device);
2395 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2397 return container_of(attr, struct mce_bank_dev, attr);
2400 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2403 u8 bank = attr_to_bank(attr)->bank;
2406 if (bank >= per_cpu(mce_num_banks, s->id))
2409 b = &per_cpu(mce_banks_array, s->id)[bank];
2414 return sprintf(buf, "%llx\n", b->ctl);
2417 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2418 const char *buf, size_t size)
2420 u8 bank = attr_to_bank(attr)->bank;
2424 if (kstrtou64(buf, 0, &new) < 0)
2427 if (bank >= per_cpu(mce_num_banks, s->id))
2430 b = &per_cpu(mce_banks_array, s->id)[bank];
2441 static ssize_t set_ignore_ce(struct device *s,
2442 struct device_attribute *attr,
2443 const char *buf, size_t size)
2447 if (kstrtou64(buf, 0, &new) < 0)
2450 mutex_lock(&mce_sysfs_mutex);
2451 if (mca_cfg.ignore_ce ^ !!new) {
2453 /* disable ce features */
2454 mce_timer_delete_all();
2455 on_each_cpu(mce_disable_cmci, NULL, 1);
2456 mca_cfg.ignore_ce = true;
2458 /* enable ce features */
2459 mca_cfg.ignore_ce = false;
2460 on_each_cpu(mce_enable_ce, (void *)1, 1);
2463 mutex_unlock(&mce_sysfs_mutex);
2468 static ssize_t set_cmci_disabled(struct device *s,
2469 struct device_attribute *attr,
2470 const char *buf, size_t size)
2474 if (kstrtou64(buf, 0, &new) < 0)
2477 mutex_lock(&mce_sysfs_mutex);
2478 if (mca_cfg.cmci_disabled ^ !!new) {
2481 on_each_cpu(mce_disable_cmci, NULL, 1);
2482 mca_cfg.cmci_disabled = true;
2485 mca_cfg.cmci_disabled = false;
2486 on_each_cpu(mce_enable_ce, NULL, 1);
2489 mutex_unlock(&mce_sysfs_mutex);
2494 static ssize_t store_int_with_restart(struct device *s,
2495 struct device_attribute *attr,
2496 const char *buf, size_t size)
2498 unsigned long old_check_interval = check_interval;
2499 ssize_t ret = device_store_ulong(s, attr, buf, size);
2501 if (check_interval == old_check_interval)
2504 mutex_lock(&mce_sysfs_mutex);
2506 mutex_unlock(&mce_sysfs_mutex);
2511 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2512 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2513 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2515 static struct dev_ext_attribute dev_attr_check_interval = {
2516 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2520 static struct dev_ext_attribute dev_attr_ignore_ce = {
2521 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2525 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2526 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2527 &mca_cfg.cmci_disabled
2530 static struct device_attribute *mce_device_attrs[] = {
2531 &dev_attr_check_interval.attr,
2532 #ifdef CONFIG_X86_MCELOG_LEGACY
2535 &dev_attr_monarch_timeout.attr,
2536 &dev_attr_dont_log_ce.attr,
2537 &dev_attr_print_all.attr,
2538 &dev_attr_ignore_ce.attr,
2539 &dev_attr_cmci_disabled.attr,
2543 static cpumask_var_t mce_device_initialized;
2545 static void mce_device_release(struct device *dev)
2550 /* Per CPU device init. All of the CPUs still share the same bank device: */
2551 static int mce_device_create(unsigned int cpu)
2557 if (!mce_available(&boot_cpu_data))
2560 dev = per_cpu(mce_device, cpu);
2564 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2568 dev->bus = &mce_subsys;
2569 dev->release = &mce_device_release;
2571 err = device_register(dev);
2577 for (i = 0; mce_device_attrs[i]; i++) {
2578 err = device_create_file(dev, mce_device_attrs[i]);
2582 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2583 err = device_create_file(dev, &mce_bank_devs[j].attr);
2587 cpumask_set_cpu(cpu, mce_device_initialized);
2588 per_cpu(mce_device, cpu) = dev;
2593 device_remove_file(dev, &mce_bank_devs[j].attr);
2596 device_remove_file(dev, mce_device_attrs[i]);
2598 device_unregister(dev);
2603 static void mce_device_remove(unsigned int cpu)
2605 struct device *dev = per_cpu(mce_device, cpu);
2608 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2611 for (i = 0; mce_device_attrs[i]; i++)
2612 device_remove_file(dev, mce_device_attrs[i]);
2614 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2615 device_remove_file(dev, &mce_bank_devs[i].attr);
2617 device_unregister(dev);
2618 cpumask_clear_cpu(cpu, mce_device_initialized);
2619 per_cpu(mce_device, cpu) = NULL;
2622 /* Make sure there are no machine checks on offlined CPUs. */
2623 static void mce_disable_cpu(void)
2625 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2628 if (!cpuhp_tasks_frozen)
2631 vendor_disable_error_reporting();
2634 static void mce_reenable_cpu(void)
2636 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2639 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2642 if (!cpuhp_tasks_frozen)
2644 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2645 struct mce_bank *b = &mce_banks[i];
2648 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
2652 static int mce_cpu_dead(unsigned int cpu)
2654 mce_intel_hcpu_update(cpu);
2656 /* intentionally ignoring frozen here */
2657 if (!cpuhp_tasks_frozen)
2662 static int mce_cpu_online(unsigned int cpu)
2664 struct timer_list *t = this_cpu_ptr(&mce_timer);
2667 mce_device_create(cpu);
2669 ret = mce_threshold_create_device(cpu);
2671 mce_device_remove(cpu);
2679 static int mce_cpu_pre_down(unsigned int cpu)
2681 struct timer_list *t = this_cpu_ptr(&mce_timer);
2685 mce_threshold_remove_device(cpu);
2686 mce_device_remove(cpu);
2690 static __init void mce_init_banks(void)
2694 for (i = 0; i < MAX_NR_BANKS; i++) {
2695 struct mce_bank_dev *b = &mce_bank_devs[i];
2696 struct device_attribute *a = &b->attr;
2700 sysfs_attr_init(&a->attr);
2701 a->attr.name = b->attrname;
2702 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2704 a->attr.mode = 0644;
2705 a->show = show_bank;
2706 a->store = set_bank;
2711 * When running on XEN, this initcall is ordered against the XEN mcelog
2714 * device_initcall(xen_late_init_mcelog);
2715 * device_initcall_sync(mcheck_init_device);
2717 static __init int mcheck_init_device(void)
2722 * Check if we have a spare virtual bit. This will only become
2723 * a problem if/when we move beyond 5-level page tables.
2725 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2727 if (!mce_available(&boot_cpu_data)) {
2732 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2739 err = subsys_system_register(&mce_subsys, NULL);
2743 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2749 * Invokes mce_cpu_online() on all CPUs which are online when
2750 * the state is installed.
2752 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2753 mce_cpu_online, mce_cpu_pre_down);
2755 goto err_out_online;
2757 register_syscore_ops(&mce_syscore_ops);
2762 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2765 free_cpumask_var(mce_device_initialized);
2768 pr_err("Unable to init MCE device (rc: %d)\n", err);
2772 device_initcall_sync(mcheck_init_device);
2775 * Old style boot options parsing. Only for compatibility.
2777 static int __init mcheck_disable(char *str)
2779 mca_cfg.disabled = 1;
2782 __setup("nomce", mcheck_disable);
2784 #ifdef CONFIG_DEBUG_FS
2785 struct dentry *mce_get_debugfs_dir(void)
2787 static struct dentry *dmce;
2790 dmce = debugfs_create_dir("mce", NULL);
2795 static void mce_reset(void)
2797 atomic_set(&mce_fake_panicked, 0);
2798 atomic_set(&mce_executing, 0);
2799 atomic_set(&mce_callin, 0);
2800 atomic_set(&global_nwo, 0);
2801 cpumask_setall(&mce_missing_cpus);
2804 static int fake_panic_get(void *data, u64 *val)
2810 static int fake_panic_set(void *data, u64 val)
2817 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2820 static void __init mcheck_debugfs_init(void)
2822 struct dentry *dmce;
2824 dmce = mce_get_debugfs_dir();
2825 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2829 static void __init mcheck_debugfs_init(void) { }
2832 static int __init mcheck_late_init(void)
2834 if (mca_cfg.recovery)
2835 enable_copy_mc_fragile();
2837 mcheck_debugfs_init();
2840 * Flush out everything that has been logged during early boot, now that
2841 * everything has been initialized (workqueues, decoders, ...).
2843 mce_schedule_work();
2847 late_initcall(mcheck_late_init);