1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/pgtable.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/semaphore.h>
11 #include <linux/thread_info.h>
12 #include <linux/init.h>
13 #include <linux/uaccess.h>
14 #include <linux/workqueue.h>
15 #include <linux/delay.h>
16 #include <linux/cpuhotplug.h>
18 #include <asm/cpufeature.h>
22 #include <asm/intel-family.h>
23 #include <asm/microcode_intel.h>
24 #include <asm/hwcap2.h>
26 #include <asm/cpu_device_id.h>
27 #include <asm/cmdline.h>
28 #include <asm/traps.h>
29 #include <asm/resctrl.h>
31 #include <asm/thermal.h>
34 #include <linux/topology.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/mpspec.h>
44 enum split_lock_detect_state {
52 * Default to sld_off because most systems do not support split lock detection.
53 * sld_state_setup() will switch this to sld_warn on systems that support
54 * split lock/bus lock detect, unless there is a command line override.
56 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
57 static u64 msr_test_ctrl_cache __ro_after_init;
60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
61 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
64 static bool cpu_model_supports_sld __ro_after_init;
67 * Processors which have self-snooping capability can handle conflicting
68 * memory type across CPUs by snooping its own cache. However, there exists
69 * CPU models in which having conflicting memory types still leads to
70 * unpredictable behavior, machine check errors, or hangs. Clear this
71 * feature to prevent its use on machines with known erratas.
73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
75 switch (c->x86_model) {
76 case INTEL_FAM6_CORE_YONAH:
77 case INTEL_FAM6_CORE2_MEROM:
78 case INTEL_FAM6_CORE2_MEROM_L:
79 case INTEL_FAM6_CORE2_PENRYN:
80 case INTEL_FAM6_CORE2_DUNNINGTON:
81 case INTEL_FAM6_NEHALEM:
82 case INTEL_FAM6_NEHALEM_G:
83 case INTEL_FAM6_NEHALEM_EP:
84 case INTEL_FAM6_NEHALEM_EX:
85 case INTEL_FAM6_WESTMERE:
86 case INTEL_FAM6_WESTMERE_EP:
87 case INTEL_FAM6_SANDYBRIDGE:
88 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
92 static bool ring3mwait_disabled __read_mostly;
94 static int __init ring3mwait_disable(char *__unused)
96 ring3mwait_disabled = true;
99 __setup("ring3mwait=disable", ring3mwait_disable);
101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
104 * Ring 3 MONITOR/MWAIT feature cannot be detected without
105 * cpu model and family comparison.
109 switch (c->x86_model) {
110 case INTEL_FAM6_XEON_PHI_KNL:
111 case INTEL_FAM6_XEON_PHI_KNM:
117 if (ring3mwait_disabled)
120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
121 this_cpu_or(msr_misc_features_shadow,
122 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
124 if (c == &boot_cpu_data)
125 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
129 * Early microcode releases for the Spectre v2 mitigation were broken.
130 * Information taken from;
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
136 struct sku_microcode {
141 static const struct sku_microcode spectre_bad_microcodes[] = {
142 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
143 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
144 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
145 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
146 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
147 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
148 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
149 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
150 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
151 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
152 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
153 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
154 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
155 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
156 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
157 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
158 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
159 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
160 /* Observed in the wild */
161 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
162 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
170 * We know that the hypervisor lie to us on the microcode version so
171 * we may as well hope that it is running the correct version.
173 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
179 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
180 if (c->x86_model == spectre_bad_microcodes[i].model &&
181 c->x86_stepping == spectre_bad_microcodes[i].stepping)
182 return (c->microcode <= spectre_bad_microcodes[i].microcode);
187 int intel_cpu_collect_info(struct ucode_cpu_info *uci)
190 unsigned int family, model;
191 struct cpu_signature csig = { 0 };
192 unsigned int eax, ebx, ecx, edx;
194 memset(uci, 0, sizeof(*uci));
198 native_cpuid(&eax, &ebx, &ecx, &edx);
201 family = x86_family(eax);
202 model = x86_model(eax);
204 if (model >= 5 || family > 6) {
205 /* get processor flags from MSR 0x17 */
206 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
207 csig.pf = 1 << ((val[1] >> 18) & 7);
210 csig.rev = intel_get_microcode_revision();
217 EXPORT_SYMBOL_GPL(intel_cpu_collect_info);
219 static void early_init_intel(struct cpuinfo_x86 *c)
223 /* Unmask CPUID levels if masked: */
224 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
225 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
226 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
227 c->cpuid_level = cpuid_eax(0);
232 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
233 (c->x86 == 0x6 && c->x86_model >= 0x0e))
234 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
236 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
237 c->microcode = intel_get_microcode_revision();
239 /* Now if any of them are set, check the blacklist and clear the lot */
240 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
241 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
242 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
243 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
244 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
245 setup_clear_cpu_cap(X86_FEATURE_IBRS);
246 setup_clear_cpu_cap(X86_FEATURE_IBPB);
247 setup_clear_cpu_cap(X86_FEATURE_STIBP);
248 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
249 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
250 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
251 setup_clear_cpu_cap(X86_FEATURE_SSBD);
252 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
256 * Atom erratum AAE44/AAF40/AAG38/AAH41:
258 * A race condition between speculative fetches and invalidating
259 * a large page. This is worked around in microcode, but we
260 * need the microcode to have already been loaded... so if it is
261 * not, recommend a BIOS update and disable large pages.
263 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
264 c->microcode < 0x20e) {
265 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
266 clear_cpu_cap(c, X86_FEATURE_PSE);
270 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
272 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
273 if (c->x86 == 15 && c->x86_cache_alignment == 64)
274 c->x86_cache_alignment = 128;
277 /* CPUID workaround for 0F33/0F34 CPU */
278 if (c->x86 == 0xF && c->x86_model == 0x3
279 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
280 c->x86_phys_bits = 36;
283 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
284 * with P/T states and does not stop in deep C-states.
286 * It is also reliable across cores and sockets. (but not across
287 * cabinets - we turn it off in that case explicitly.)
289 if (c->x86_power & (1 << 8)) {
290 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
291 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
294 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
296 switch (c->x86_model) {
297 case INTEL_FAM6_ATOM_SALTWELL_MID:
298 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
299 case INTEL_FAM6_ATOM_SILVERMONT_MID:
300 case INTEL_FAM6_ATOM_AIRMONT_NP:
301 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
309 * There is a known erratum on Pentium III and Core Solo
311 * " Page with PAT set to WC while associated MTRR is UC
312 * may consolidate to UC "
313 * Because of this erratum, it is better to stick with
314 * setting WC in MTRR rather than using PAT on these CPUs.
316 * Enable PAT WC only on P4, Core 2 or later CPUs.
318 if (c->x86 == 6 && c->x86_model < 15)
319 clear_cpu_cap(c, X86_FEATURE_PAT);
322 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
323 * clear the fast string and enhanced fast string CPU capabilities.
325 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
326 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
327 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
328 pr_info("Disabled fast string operations\n");
329 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
330 setup_clear_cpu_cap(X86_FEATURE_ERMS);
335 * Intel Quark Core DevMan_001.pdf section 6.4.11
336 * "The operating system also is required to invalidate (i.e., flush)
337 * the TLB when any changes are made to any of the page table entries.
338 * The operating system must reload CR3 to cause the TLB to be flushed"
340 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
341 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
344 if (c->x86 == 5 && c->x86_model == 9) {
345 pr_info("Disabling PGE capability bit\n");
346 setup_clear_cpu_cap(X86_FEATURE_PGE);
349 if (c->cpuid_level >= 0x00000001) {
350 u32 eax, ebx, ecx, edx;
352 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
354 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
355 * apicids which are reserved per package. Store the resulting
356 * shift value for the package management code.
358 if (edx & (1U << 28))
359 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
362 check_memory_type_self_snoop_errata(c);
365 * Get the number of SMT siblings early from the extended topology
366 * leaf, if available. Otherwise try the legacy SMT detection.
368 if (detect_extended_topology_early(c) < 0)
372 static void bsp_init_intel(struct cpuinfo_x86 *c)
374 resctrl_cpu_detect(c);
379 * Early probe support logic for ppro memory erratum #50
381 * This is called before we do cpu ident work
384 int ppro_with_ram_bug(void)
386 /* Uses data from early_cpu_detect now */
387 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
388 boot_cpu_data.x86 == 6 &&
389 boot_cpu_data.x86_model == 1 &&
390 boot_cpu_data.x86_stepping < 8) {
391 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
397 static void intel_smp_check(struct cpuinfo_x86 *c)
399 /* calling is from identify_secondary_cpu() ? */
404 * Mask B, Pentium, but not Pentium MMX
407 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
410 * Remember we have B step Pentia with bugs
412 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
413 "with B stepping processors.\n");
418 static int __init forcepae_setup(char *__unused)
423 __setup("forcepae", forcepae_setup);
425 static void intel_workarounds(struct cpuinfo_x86 *c)
427 #ifdef CONFIG_X86_F00F_BUG
429 * All models of Pentium and Pentium with MMX technology CPUs
430 * have the F0 0F bug, which lets nonprivileged users lock up the
431 * system. Announce that the fault handler will be checking for it.
432 * The Quark is also family 5, but does not have the same bug.
434 clear_cpu_bug(c, X86_BUG_F00F);
435 if (c->x86 == 5 && c->x86_model < 9) {
436 static int f00f_workaround_enabled;
438 set_cpu_bug(c, X86_BUG_F00F);
439 if (!f00f_workaround_enabled) {
440 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
441 f00f_workaround_enabled = 1;
447 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
450 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
451 clear_cpu_cap(c, X86_FEATURE_SEP);
454 * PAE CPUID issue: many Pentium M report no PAE but may have a
455 * functionally usable PAE implementation.
456 * Forcefully enable PAE if kernel parameter "forcepae" is present.
459 pr_warn("PAE forced!\n");
460 set_cpu_cap(c, X86_FEATURE_PAE);
461 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
465 * P4 Xeon erratum 037 workaround.
466 * Hardware prefetcher may cause stale data to be loaded into the cache.
468 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
469 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
470 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
471 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
472 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
477 * See if we have a good local APIC by checking for buggy Pentia,
478 * i.e. all B steppings and the C2 stepping of P54C when using their
479 * integrated APIC (see 11AP erratum in "Pentium Processor
480 * Specification Update").
482 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
483 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
484 set_cpu_bug(c, X86_BUG_11AP);
487 #ifdef CONFIG_X86_INTEL_USERCOPY
489 * Set up the preferred alignment for movsl bulk memory moves
492 case 4: /* 486: untested */
494 case 5: /* Old Pentia: untested */
496 case 6: /* PII/PIII only like movsl with 8-byte alignment */
499 case 15: /* P4 is OK down to 8-byte alignment */
508 static void intel_workarounds(struct cpuinfo_x86 *c)
513 static void srat_detect_node(struct cpuinfo_x86 *c)
517 int cpu = smp_processor_id();
519 /* Don't do the funky fallback heuristics the AMD version employs
521 node = numa_cpu_node(cpu);
522 if (node == NUMA_NO_NODE || !node_online(node)) {
523 /* reuse the value from init_cpu_to_node() */
524 node = cpu_to_node(cpu);
526 numa_set_node(cpu, node);
530 #define MSR_IA32_TME_ACTIVATE 0x982
532 /* Helpers to access TME_ACTIVATE MSR */
533 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
534 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
536 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
537 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
539 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
541 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
542 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
544 /* Values for mktme_status (SW only construct) */
545 #define MKTME_ENABLED 0
546 #define MKTME_DISABLED 1
547 #define MKTME_UNINITIALIZED 2
548 static int mktme_status = MKTME_UNINITIALIZED;
550 static void detect_tme(struct cpuinfo_x86 *c)
552 u64 tme_activate, tme_policy, tme_crypto_algs;
553 int keyid_bits = 0, nr_keyids = 0;
554 static u64 tme_activate_cpu0 = 0;
556 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
558 if (mktme_status != MKTME_UNINITIALIZED) {
559 if (tme_activate != tme_activate_cpu0) {
561 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
562 pr_err_once("x86/tme: MKTME is not usable\n");
563 mktme_status = MKTME_DISABLED;
565 /* Proceed. We may need to exclude bits from x86_phys_bits. */
568 tme_activate_cpu0 = tme_activate;
571 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
572 pr_info_once("x86/tme: not enabled by BIOS\n");
573 mktme_status = MKTME_DISABLED;
577 if (mktme_status != MKTME_UNINITIALIZED)
578 goto detect_keyid_bits;
580 pr_info("x86/tme: enabled by BIOS\n");
582 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
583 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
584 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
586 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
587 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
588 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
590 mktme_status = MKTME_DISABLED;
593 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
594 nr_keyids = (1UL << keyid_bits) - 1;
596 pr_info_once("x86/mktme: enabled by BIOS\n");
597 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
599 pr_info_once("x86/mktme: disabled by BIOS\n");
602 if (mktme_status == MKTME_UNINITIALIZED) {
603 /* MKTME is usable */
604 mktme_status = MKTME_ENABLED;
608 * KeyID bits effectively lower the number of physical address
609 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
611 c->x86_phys_bits -= keyid_bits;
614 static void init_cpuid_fault(struct cpuinfo_x86 *c)
618 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
619 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
620 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
624 static void init_intel_misc_features(struct cpuinfo_x86 *c)
628 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
631 /* Clear all MISC features */
632 this_cpu_write(msr_misc_features_shadow, 0);
634 /* Check features and update capabilities and shadow control bits */
636 probe_xeon_phi_r3mwait(c);
638 msr = this_cpu_read(msr_misc_features_shadow);
639 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
642 static void split_lock_init(void);
643 static void bus_lock_init(void);
645 static void init_intel(struct cpuinfo_x86 *c)
649 intel_workarounds(c);
652 * Detect the extended topology information if available. This
653 * will reinitialise the initial_apicid which will be used
654 * in init_intel_cacheinfo()
656 detect_extended_topology(c);
658 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
660 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
663 detect_num_cpu_cores(c);
669 init_intel_cacheinfo(c);
671 if (c->cpuid_level > 9) {
672 unsigned eax = cpuid_eax(10);
673 /* Check for version and the number of counters */
674 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
675 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
678 if (cpu_has(c, X86_FEATURE_XMM2))
679 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
681 if (boot_cpu_has(X86_FEATURE_DS)) {
684 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
686 set_cpu_cap(c, X86_FEATURE_BTS);
688 set_cpu_cap(c, X86_FEATURE_PEBS);
691 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
692 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
693 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
695 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
696 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
697 set_cpu_bug(c, X86_BUG_MONITOR);
701 c->x86_cache_alignment = c->x86_clflush_size * 2;
703 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
706 * Names for the Pentium II/Celeron processors
707 * detectable only by also checking the cache size.
708 * Dixon is NOT a Celeron.
711 unsigned int l2 = c->x86_cache_size;
714 switch (c->x86_model) {
717 p = "Celeron (Covington)";
719 p = "Mobile Pentium II (Dixon)";
724 p = "Celeron (Mendocino)";
725 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
731 p = "Celeron (Coppermine)";
736 strcpy(c->x86_model_id, p);
740 set_cpu_cap(c, X86_FEATURE_P4);
742 set_cpu_cap(c, X86_FEATURE_P3);
745 /* Work around errata */
748 init_ia32_feat_ctl(c);
750 if (cpu_has(c, X86_FEATURE_TME))
753 init_intel_misc_features(c);
758 intel_init_thermal(c);
762 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
765 * Intel PIII Tualatin. This comes in two flavours.
766 * One has 256kb of cache, the other 512. We have no way
767 * to determine which, so we use a boottime override
768 * for the 512kb model, and assume 256 otherwise.
770 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
774 * Intel Quark SoC X1000 contains a 4-way set associative
775 * 16K cache with a 16 byte cache line and 256 lines per tag
777 if ((c->x86 == 5) && (c->x86_model == 9))
783 #define TLB_INST_4K 0x01
784 #define TLB_INST_4M 0x02
785 #define TLB_INST_2M_4M 0x03
787 #define TLB_INST_ALL 0x05
788 #define TLB_INST_1G 0x06
790 #define TLB_DATA_4K 0x11
791 #define TLB_DATA_4M 0x12
792 #define TLB_DATA_2M_4M 0x13
793 #define TLB_DATA_4K_4M 0x14
795 #define TLB_DATA_1G 0x16
797 #define TLB_DATA0_4K 0x21
798 #define TLB_DATA0_4M 0x22
799 #define TLB_DATA0_2M_4M 0x23
802 #define STLB_4K_2M 0x42
804 static const struct _tlb_table intel_tlb_table[] = {
805 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
806 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
807 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
808 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
809 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
810 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
811 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
812 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
813 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
814 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
815 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
816 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
817 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
818 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
819 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
820 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
821 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
822 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
823 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
824 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
825 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
826 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
827 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
828 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
829 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
830 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
831 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
832 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
833 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
834 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
835 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
836 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
837 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
838 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
839 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
840 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
844 static void intel_tlb_lookup(const unsigned char desc)
850 /* look up this descriptor in the table */
851 for (k = 0; intel_tlb_table[k].descriptor != desc &&
852 intel_tlb_table[k].descriptor != 0; k++)
855 if (intel_tlb_table[k].tlb_type == 0)
858 switch (intel_tlb_table[k].tlb_type) {
860 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
861 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
862 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
863 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
866 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
867 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
868 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
869 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
870 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
871 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
872 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
873 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
874 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
875 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
876 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
877 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
880 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
881 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
882 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
883 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
884 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
885 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
888 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
889 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
892 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
893 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
896 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
897 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
898 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
899 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
903 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
904 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
908 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
909 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
912 case TLB_DATA0_2M_4M:
913 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
914 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
915 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
916 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
919 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
920 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
921 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
922 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
925 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
926 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
931 static void intel_detect_tlb(struct cpuinfo_x86 *c)
934 unsigned int regs[4];
935 unsigned char *desc = (unsigned char *)regs;
937 if (c->cpuid_level < 2)
940 /* Number of times to iterate */
941 n = cpuid_eax(2) & 0xFF;
943 for (i = 0 ; i < n ; i++) {
944 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
946 /* If bit 31 is set, this is an unknown format */
947 for (j = 0 ; j < 3 ; j++)
948 if (regs[j] & (1 << 31))
951 /* Byte 0 is level count, not a descriptor */
952 for (j = 1 ; j < 16 ; j++)
953 intel_tlb_lookup(desc[j]);
957 static const struct cpu_dev intel_cpu_dev = {
959 .c_ident = { "GenuineIntel" },
962 { .family = 4, .model_names =
964 [0] = "486 DX-25/33",
975 { .family = 5, .model_names =
977 [0] = "Pentium 60/66 A-step",
978 [1] = "Pentium 60/66",
979 [2] = "Pentium 75 - 200",
980 [3] = "OverDrive PODP5V83",
982 [7] = "Mobile Pentium 75 - 200",
983 [8] = "Mobile Pentium MMX",
984 [9] = "Quark SoC X1000",
987 { .family = 6, .model_names =
989 [0] = "Pentium Pro A-step",
991 [3] = "Pentium II (Klamath)",
992 [4] = "Pentium II (Deschutes)",
993 [5] = "Pentium II (Deschutes)",
994 [6] = "Mobile Pentium II",
995 [7] = "Pentium III (Katmai)",
996 [8] = "Pentium III (Coppermine)",
997 [10] = "Pentium III (Cascades)",
998 [11] = "Pentium III (Tualatin)",
1001 { .family = 15, .model_names =
1003 [0] = "Pentium 4 (Unknown)",
1004 [1] = "Pentium 4 (Willamette)",
1005 [2] = "Pentium 4 (Northwood)",
1006 [4] = "Pentium 4 (Foster)",
1007 [5] = "Pentium 4 (Foster)",
1011 .legacy_cache_size = intel_size_cache,
1013 .c_detect_tlb = intel_detect_tlb,
1014 .c_early_init = early_init_intel,
1015 .c_bsp_init = bsp_init_intel,
1016 .c_init = init_intel,
1017 .c_x86_vendor = X86_VENDOR_INTEL,
1020 cpu_dev_register(intel_cpu_dev);
1023 #define pr_fmt(fmt) "x86/split lock detection: " fmt
1025 static const struct {
1027 enum split_lock_detect_state state;
1028 } sld_options[] __initconst = {
1030 { "warn", sld_warn },
1031 { "fatal", sld_fatal },
1032 { "ratelimit:", sld_ratelimit },
1035 static struct ratelimit_state bld_ratelimit;
1037 static DEFINE_SEMAPHORE(buslock_sem);
1039 static inline bool match_option(const char *arg, int arglen, const char *opt)
1041 int len = strlen(opt), ratelimit;
1043 if (strncmp(arg, opt, len))
1047 * Min ratelimit is 1 bus lock/sec.
1048 * Max ratelimit is 1000 bus locks/sec.
1050 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
1051 ratelimit > 0 && ratelimit <= 1000) {
1052 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
1053 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
1057 return len == arglen;
1060 static bool split_lock_verify_msr(bool on)
1064 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1067 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1069 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1070 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1072 rdmsrl(MSR_TEST_CTRL, tmp);
1076 static void __init sld_state_setup(void)
1078 enum split_lock_detect_state state = sld_warn;
1082 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1083 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1086 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1089 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1090 if (match_option(arg, ret, sld_options[i].option)) {
1091 state = sld_options[i].state;
1099 static void __init __split_lock_setup(void)
1101 if (!split_lock_verify_msr(false)) {
1102 pr_info("MSR access failed: Disabled\n");
1106 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1108 if (!split_lock_verify_msr(true)) {
1109 pr_info("MSR access failed: Disabled\n");
1113 /* Restore the MSR to its cached value. */
1114 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1116 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1120 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1121 * is not implemented as one thread could undo the setting of the other
1122 * thread immediately after dropping the lock anyway.
1124 static void sld_update_msr(bool on)
1126 u64 test_ctrl_val = msr_test_ctrl_cache;
1129 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1131 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1134 static void split_lock_init(void)
1137 * #DB for bus lock handles ratelimit and #AC for split lock is
1140 if (sld_state == sld_ratelimit) {
1141 split_lock_verify_msr(false);
1145 if (cpu_model_supports_sld)
1146 split_lock_verify_msr(sld_state != sld_off);
1149 static void __split_lock_reenable(struct work_struct *work)
1151 sld_update_msr(true);
1156 * If a CPU goes offline with pending delayed work to re-enable split lock
1157 * detection then the delayed work will be executed on some other CPU. That
1158 * handles releasing the buslock_sem, but because it executes on a
1159 * different CPU probably won't re-enable split lock detection. This is a
1160 * problem on HT systems since the sibling CPU on the same core may then be
1161 * left running with split lock detection disabled.
1163 * Unconditionally re-enable detection here.
1165 static int splitlock_cpu_offline(unsigned int cpu)
1167 sld_update_msr(true);
1172 static DECLARE_DELAYED_WORK(split_lock_reenable, __split_lock_reenable);
1174 static void split_lock_warn(unsigned long ip)
1178 if (!current->reported_split_lock)
1179 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1180 current->comm, current->pid, ip);
1181 current->reported_split_lock = 1;
1183 /* misery factor #1, sleep 10ms before trying to execute split lock */
1184 if (msleep_interruptible(10) > 0)
1186 /* Misery factor #2, only allow one buslocked disabled core at a time */
1187 if (down_interruptible(&buslock_sem) == -EINTR)
1190 schedule_delayed_work_on(cpu, &split_lock_reenable, 2);
1192 /* Disable split lock detection on this CPU to make progress */
1193 sld_update_msr(false);
1197 bool handle_guest_split_lock(unsigned long ip)
1199 if (sld_state == sld_warn) {
1200 split_lock_warn(ip);
1204 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1205 current->comm, current->pid,
1206 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1208 current->thread.error_code = 0;
1209 current->thread.trap_nr = X86_TRAP_AC;
1210 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1213 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1215 static void bus_lock_init(void)
1220 * Warn and fatal are handled by #AC for split lock if #AC for
1221 * split lock is supported.
1223 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) ||
1224 (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1225 (sld_state == sld_warn || sld_state == sld_fatal)) ||
1226 sld_state == sld_off)
1230 * Enable #DB for bus lock. All bus locks are handled in #DB except
1231 * split locks are handled in #AC in the fatal case.
1233 rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1234 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1235 wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1238 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1240 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1242 split_lock_warn(regs->ip);
1246 void handle_bus_lock(struct pt_regs *regs)
1248 switch (sld_state) {
1252 /* Enforce no more than bld_ratelimit bus locks/sec. */
1253 while (!__ratelimit(&bld_ratelimit))
1255 /* Warn on the bus lock. */
1258 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1259 current->comm, current->pid, regs->ip);
1262 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1268 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should
1269 * only be trusted if it is confirmed that a CPU model implements a
1270 * specific feature at a particular bit position.
1272 * The possible driver data field values:
1274 * - 0: CPU models that are known to have the per-core split-lock detection
1275 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1277 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1278 * bit 5 to enumerate the per-core split-lock detection feature.
1280 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1281 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1282 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1283 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1284 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
1285 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
1286 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
1287 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1),
1288 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1),
1289 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 1),
1290 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 1),
1291 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 1),
1292 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 1),
1296 static void __init split_lock_setup(struct cpuinfo_x86 *c)
1298 const struct x86_cpu_id *m;
1301 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1304 m = x86_match_cpu(split_lock_cpu_ids);
1308 switch (m->driver_data) {
1312 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1314 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1315 if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))
1322 cpu_model_supports_sld = true;
1323 __split_lock_setup();
1326 static void sld_state_show(void)
1328 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1329 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1332 switch (sld_state) {
1334 pr_info("disabled\n");
1337 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1338 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1339 if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1340 "x86/splitlock", NULL, splitlock_cpu_offline) < 0)
1341 pr_warn("No splitlock CPU offline handler\n");
1342 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1343 pr_info("#DB: warning on user-space bus_locks\n");
1347 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1348 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1349 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1350 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1351 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1352 " from non-WB" : "");
1356 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1357 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1362 void __init sld_setup(struct cpuinfo_x86 *c)
1364 split_lock_setup(c);
1369 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
1372 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1374 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1375 * a hybrid processor. If the processor is not hybrid, returns 0.
1377 u8 get_this_hybrid_cpu_type(void)
1379 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1382 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;