1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/pgtable.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/thread_info.h>
11 #include <linux/init.h>
12 #include <linux/uaccess.h>
13 #include <linux/delay.h>
15 #include <asm/cpufeature.h>
19 #include <asm/intel-family.h>
20 #include <asm/microcode_intel.h>
21 #include <asm/hwcap2.h>
23 #include <asm/cpu_device_id.h>
24 #include <asm/cmdline.h>
25 #include <asm/traps.h>
26 #include <asm/resctrl.h>
28 #include <asm/thermal.h>
31 #include <linux/topology.h>
36 #ifdef CONFIG_X86_LOCAL_APIC
37 #include <asm/mpspec.h>
41 enum split_lock_detect_state {
49 * Default to sld_off because most systems do not support split lock detection.
50 * sld_state_setup() will switch this to sld_warn on systems that support
51 * split lock/bus lock detect, unless there is a command line override.
53 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
54 static u64 msr_test_ctrl_cache __ro_after_init;
57 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
58 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
59 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
61 static bool cpu_model_supports_sld __ro_after_init;
64 * Processors which have self-snooping capability can handle conflicting
65 * memory type across CPUs by snooping its own cache. However, there exists
66 * CPU models in which having conflicting memory types still leads to
67 * unpredictable behavior, machine check errors, or hangs. Clear this
68 * feature to prevent its use on machines with known erratas.
70 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
72 switch (c->x86_model) {
73 case INTEL_FAM6_CORE_YONAH:
74 case INTEL_FAM6_CORE2_MEROM:
75 case INTEL_FAM6_CORE2_MEROM_L:
76 case INTEL_FAM6_CORE2_PENRYN:
77 case INTEL_FAM6_CORE2_DUNNINGTON:
78 case INTEL_FAM6_NEHALEM:
79 case INTEL_FAM6_NEHALEM_G:
80 case INTEL_FAM6_NEHALEM_EP:
81 case INTEL_FAM6_NEHALEM_EX:
82 case INTEL_FAM6_WESTMERE:
83 case INTEL_FAM6_WESTMERE_EP:
84 case INTEL_FAM6_SANDYBRIDGE:
85 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
89 static bool ring3mwait_disabled __read_mostly;
91 static int __init ring3mwait_disable(char *__unused)
93 ring3mwait_disabled = true;
96 __setup("ring3mwait=disable", ring3mwait_disable);
98 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
101 * Ring 3 MONITOR/MWAIT feature cannot be detected without
102 * cpu model and family comparison.
106 switch (c->x86_model) {
107 case INTEL_FAM6_XEON_PHI_KNL:
108 case INTEL_FAM6_XEON_PHI_KNM:
114 if (ring3mwait_disabled)
117 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
118 this_cpu_or(msr_misc_features_shadow,
119 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
121 if (c == &boot_cpu_data)
122 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
126 * Early microcode releases for the Spectre v2 mitigation were broken.
127 * Information taken from;
128 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
129 * - https://kb.vmware.com/s/article/52345
130 * - Microcode revisions observed in the wild
131 * - Release note from 20180108 microcode release
133 struct sku_microcode {
138 static const struct sku_microcode spectre_bad_microcodes[] = {
139 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
140 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
141 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
142 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
143 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
144 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
145 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
146 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
147 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
148 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
149 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
150 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
151 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
152 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
153 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
154 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
155 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
156 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
157 /* Observed in the wild */
158 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
159 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
162 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
167 * We know that the hypervisor lie to us on the microcode version so
168 * we may as well hope that it is running the correct version.
170 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
176 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
177 if (c->x86_model == spectre_bad_microcodes[i].model &&
178 c->x86_stepping == spectre_bad_microcodes[i].stepping)
179 return (c->microcode <= spectre_bad_microcodes[i].microcode);
184 static void early_init_intel(struct cpuinfo_x86 *c)
188 /* Unmask CPUID levels if masked: */
189 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
190 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
191 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
192 c->cpuid_level = cpuid_eax(0);
197 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
198 (c->x86 == 0x6 && c->x86_model >= 0x0e))
199 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
201 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
202 c->microcode = intel_get_microcode_revision();
204 /* Now if any of them are set, check the blacklist and clear the lot */
205 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
206 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
207 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
208 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
209 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
210 setup_clear_cpu_cap(X86_FEATURE_IBRS);
211 setup_clear_cpu_cap(X86_FEATURE_IBPB);
212 setup_clear_cpu_cap(X86_FEATURE_STIBP);
213 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
214 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
215 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
216 setup_clear_cpu_cap(X86_FEATURE_SSBD);
217 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
221 * Atom erratum AAE44/AAF40/AAG38/AAH41:
223 * A race condition between speculative fetches and invalidating
224 * a large page. This is worked around in microcode, but we
225 * need the microcode to have already been loaded... so if it is
226 * not, recommend a BIOS update and disable large pages.
228 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
229 c->microcode < 0x20e) {
230 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
231 clear_cpu_cap(c, X86_FEATURE_PSE);
235 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
237 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
238 if (c->x86 == 15 && c->x86_cache_alignment == 64)
239 c->x86_cache_alignment = 128;
242 /* CPUID workaround for 0F33/0F34 CPU */
243 if (c->x86 == 0xF && c->x86_model == 0x3
244 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
245 c->x86_phys_bits = 36;
248 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
249 * with P/T states and does not stop in deep C-states.
251 * It is also reliable across cores and sockets. (but not across
252 * cabinets - we turn it off in that case explicitly.)
254 if (c->x86_power & (1 << 8)) {
255 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
256 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
259 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
261 switch (c->x86_model) {
262 case INTEL_FAM6_ATOM_SALTWELL_MID:
263 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
264 case INTEL_FAM6_ATOM_SILVERMONT_MID:
265 case INTEL_FAM6_ATOM_AIRMONT_NP:
266 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
274 * There is a known erratum on Pentium III and Core Solo
276 * " Page with PAT set to WC while associated MTRR is UC
277 * may consolidate to UC "
278 * Because of this erratum, it is better to stick with
279 * setting WC in MTRR rather than using PAT on these CPUs.
281 * Enable PAT WC only on P4, Core 2 or later CPUs.
283 if (c->x86 == 6 && c->x86_model < 15)
284 clear_cpu_cap(c, X86_FEATURE_PAT);
287 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
288 * clear the fast string and enhanced fast string CPU capabilities.
290 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
291 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
292 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
293 pr_info("Disabled fast string operations\n");
294 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
295 setup_clear_cpu_cap(X86_FEATURE_ERMS);
300 * Intel Quark Core DevMan_001.pdf section 6.4.11
301 * "The operating system also is required to invalidate (i.e., flush)
302 * the TLB when any changes are made to any of the page table entries.
303 * The operating system must reload CR3 to cause the TLB to be flushed"
305 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
306 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
309 if (c->x86 == 5 && c->x86_model == 9) {
310 pr_info("Disabling PGE capability bit\n");
311 setup_clear_cpu_cap(X86_FEATURE_PGE);
314 if (c->cpuid_level >= 0x00000001) {
315 u32 eax, ebx, ecx, edx;
317 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
319 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
320 * apicids which are reserved per package. Store the resulting
321 * shift value for the package management code.
323 if (edx & (1U << 28))
324 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
327 check_memory_type_self_snoop_errata(c);
330 * Get the number of SMT siblings early from the extended topology
331 * leaf, if available. Otherwise try the legacy SMT detection.
333 if (detect_extended_topology_early(c) < 0)
337 static void bsp_init_intel(struct cpuinfo_x86 *c)
339 resctrl_cpu_detect(c);
344 * Early probe support logic for ppro memory erratum #50
346 * This is called before we do cpu ident work
349 int ppro_with_ram_bug(void)
351 /* Uses data from early_cpu_detect now */
352 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
353 boot_cpu_data.x86 == 6 &&
354 boot_cpu_data.x86_model == 1 &&
355 boot_cpu_data.x86_stepping < 8) {
356 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
362 static void intel_smp_check(struct cpuinfo_x86 *c)
364 /* calling is from identify_secondary_cpu() ? */
369 * Mask B, Pentium, but not Pentium MMX
372 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
375 * Remember we have B step Pentia with bugs
377 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
378 "with B stepping processors.\n");
383 static int __init forcepae_setup(char *__unused)
388 __setup("forcepae", forcepae_setup);
390 static void intel_workarounds(struct cpuinfo_x86 *c)
392 #ifdef CONFIG_X86_F00F_BUG
394 * All models of Pentium and Pentium with MMX technology CPUs
395 * have the F0 0F bug, which lets nonprivileged users lock up the
396 * system. Announce that the fault handler will be checking for it.
397 * The Quark is also family 5, but does not have the same bug.
399 clear_cpu_bug(c, X86_BUG_F00F);
400 if (c->x86 == 5 && c->x86_model < 9) {
401 static int f00f_workaround_enabled;
403 set_cpu_bug(c, X86_BUG_F00F);
404 if (!f00f_workaround_enabled) {
405 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
406 f00f_workaround_enabled = 1;
412 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
415 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
416 clear_cpu_cap(c, X86_FEATURE_SEP);
419 * PAE CPUID issue: many Pentium M report no PAE but may have a
420 * functionally usable PAE implementation.
421 * Forcefully enable PAE if kernel parameter "forcepae" is present.
424 pr_warn("PAE forced!\n");
425 set_cpu_cap(c, X86_FEATURE_PAE);
426 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
430 * P4 Xeon erratum 037 workaround.
431 * Hardware prefetcher may cause stale data to be loaded into the cache.
433 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
434 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
435 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
436 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
437 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
442 * See if we have a good local APIC by checking for buggy Pentia,
443 * i.e. all B steppings and the C2 stepping of P54C when using their
444 * integrated APIC (see 11AP erratum in "Pentium Processor
445 * Specification Update").
447 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
448 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
449 set_cpu_bug(c, X86_BUG_11AP);
452 #ifdef CONFIG_X86_INTEL_USERCOPY
454 * Set up the preferred alignment for movsl bulk memory moves
457 case 4: /* 486: untested */
459 case 5: /* Old Pentia: untested */
461 case 6: /* PII/PIII only like movsl with 8-byte alignment */
464 case 15: /* P4 is OK down to 8-byte alignment */
473 static void intel_workarounds(struct cpuinfo_x86 *c)
478 static void srat_detect_node(struct cpuinfo_x86 *c)
482 int cpu = smp_processor_id();
484 /* Don't do the funky fallback heuristics the AMD version employs
486 node = numa_cpu_node(cpu);
487 if (node == NUMA_NO_NODE || !node_online(node)) {
488 /* reuse the value from init_cpu_to_node() */
489 node = cpu_to_node(cpu);
491 numa_set_node(cpu, node);
495 #define MSR_IA32_TME_ACTIVATE 0x982
497 /* Helpers to access TME_ACTIVATE MSR */
498 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
499 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
501 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
502 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
504 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
506 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
507 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
509 /* Values for mktme_status (SW only construct) */
510 #define MKTME_ENABLED 0
511 #define MKTME_DISABLED 1
512 #define MKTME_UNINITIALIZED 2
513 static int mktme_status = MKTME_UNINITIALIZED;
515 static void detect_tme(struct cpuinfo_x86 *c)
517 u64 tme_activate, tme_policy, tme_crypto_algs;
518 int keyid_bits = 0, nr_keyids = 0;
519 static u64 tme_activate_cpu0 = 0;
521 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
523 if (mktme_status != MKTME_UNINITIALIZED) {
524 if (tme_activate != tme_activate_cpu0) {
526 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
527 pr_err_once("x86/tme: MKTME is not usable\n");
528 mktme_status = MKTME_DISABLED;
530 /* Proceed. We may need to exclude bits from x86_phys_bits. */
533 tme_activate_cpu0 = tme_activate;
536 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
537 pr_info_once("x86/tme: not enabled by BIOS\n");
538 mktme_status = MKTME_DISABLED;
542 if (mktme_status != MKTME_UNINITIALIZED)
543 goto detect_keyid_bits;
545 pr_info("x86/tme: enabled by BIOS\n");
547 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
548 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
549 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
551 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
552 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
553 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
555 mktme_status = MKTME_DISABLED;
558 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
559 nr_keyids = (1UL << keyid_bits) - 1;
561 pr_info_once("x86/mktme: enabled by BIOS\n");
562 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
564 pr_info_once("x86/mktme: disabled by BIOS\n");
567 if (mktme_status == MKTME_UNINITIALIZED) {
568 /* MKTME is usable */
569 mktme_status = MKTME_ENABLED;
573 * KeyID bits effectively lower the number of physical address
574 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
576 c->x86_phys_bits -= keyid_bits;
579 static void init_cpuid_fault(struct cpuinfo_x86 *c)
583 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
584 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
585 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
589 static void init_intel_misc_features(struct cpuinfo_x86 *c)
593 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
596 /* Clear all MISC features */
597 this_cpu_write(msr_misc_features_shadow, 0);
599 /* Check features and update capabilities and shadow control bits */
601 probe_xeon_phi_r3mwait(c);
603 msr = this_cpu_read(msr_misc_features_shadow);
604 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
607 static void split_lock_init(void);
608 static void bus_lock_init(void);
610 static void init_intel(struct cpuinfo_x86 *c)
614 intel_workarounds(c);
617 * Detect the extended topology information if available. This
618 * will reinitialise the initial_apicid which will be used
619 * in init_intel_cacheinfo()
621 detect_extended_topology(c);
623 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
625 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
628 detect_num_cpu_cores(c);
634 init_intel_cacheinfo(c);
636 if (c->cpuid_level > 9) {
637 unsigned eax = cpuid_eax(10);
638 /* Check for version and the number of counters */
639 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
640 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
643 if (cpu_has(c, X86_FEATURE_XMM2))
644 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
646 if (boot_cpu_has(X86_FEATURE_DS)) {
649 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
651 set_cpu_cap(c, X86_FEATURE_BTS);
653 set_cpu_cap(c, X86_FEATURE_PEBS);
656 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
657 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
658 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
660 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
661 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
662 set_cpu_bug(c, X86_BUG_MONITOR);
666 c->x86_cache_alignment = c->x86_clflush_size * 2;
668 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
671 * Names for the Pentium II/Celeron processors
672 * detectable only by also checking the cache size.
673 * Dixon is NOT a Celeron.
676 unsigned int l2 = c->x86_cache_size;
679 switch (c->x86_model) {
682 p = "Celeron (Covington)";
684 p = "Mobile Pentium II (Dixon)";
689 p = "Celeron (Mendocino)";
690 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
696 p = "Celeron (Coppermine)";
701 strcpy(c->x86_model_id, p);
705 set_cpu_cap(c, X86_FEATURE_P4);
707 set_cpu_cap(c, X86_FEATURE_P3);
710 /* Work around errata */
713 init_ia32_feat_ctl(c);
715 if (cpu_has(c, X86_FEATURE_TME))
718 init_intel_misc_features(c);
723 intel_init_thermal(c);
727 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
730 * Intel PIII Tualatin. This comes in two flavours.
731 * One has 256kb of cache, the other 512. We have no way
732 * to determine which, so we use a boottime override
733 * for the 512kb model, and assume 256 otherwise.
735 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
739 * Intel Quark SoC X1000 contains a 4-way set associative
740 * 16K cache with a 16 byte cache line and 256 lines per tag
742 if ((c->x86 == 5) && (c->x86_model == 9))
748 #define TLB_INST_4K 0x01
749 #define TLB_INST_4M 0x02
750 #define TLB_INST_2M_4M 0x03
752 #define TLB_INST_ALL 0x05
753 #define TLB_INST_1G 0x06
755 #define TLB_DATA_4K 0x11
756 #define TLB_DATA_4M 0x12
757 #define TLB_DATA_2M_4M 0x13
758 #define TLB_DATA_4K_4M 0x14
760 #define TLB_DATA_1G 0x16
762 #define TLB_DATA0_4K 0x21
763 #define TLB_DATA0_4M 0x22
764 #define TLB_DATA0_2M_4M 0x23
767 #define STLB_4K_2M 0x42
769 static const struct _tlb_table intel_tlb_table[] = {
770 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
771 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
772 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
773 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
774 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
775 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
776 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
777 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
778 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
779 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
780 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
781 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
782 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
783 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
784 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
785 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
786 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
787 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
788 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
789 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
790 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
791 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
792 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
793 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
794 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
795 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
796 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
797 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
798 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
799 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
800 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
801 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
802 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
803 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
804 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
805 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
809 static void intel_tlb_lookup(const unsigned char desc)
815 /* look up this descriptor in the table */
816 for (k = 0; intel_tlb_table[k].descriptor != desc &&
817 intel_tlb_table[k].descriptor != 0; k++)
820 if (intel_tlb_table[k].tlb_type == 0)
823 switch (intel_tlb_table[k].tlb_type) {
825 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
826 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
827 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
828 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
831 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
832 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
833 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
834 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
835 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
836 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
837 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
838 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
839 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
840 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
841 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
842 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
845 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
846 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
847 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
848 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
849 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
850 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
853 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
854 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
857 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
858 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
861 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
862 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
863 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
864 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
868 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
869 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
873 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
874 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
877 case TLB_DATA0_2M_4M:
878 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
879 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
880 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
881 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
884 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
885 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
886 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
887 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
890 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
891 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
896 static void intel_detect_tlb(struct cpuinfo_x86 *c)
899 unsigned int regs[4];
900 unsigned char *desc = (unsigned char *)regs;
902 if (c->cpuid_level < 2)
905 /* Number of times to iterate */
906 n = cpuid_eax(2) & 0xFF;
908 for (i = 0 ; i < n ; i++) {
909 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
911 /* If bit 31 is set, this is an unknown format */
912 for (j = 0 ; j < 3 ; j++)
913 if (regs[j] & (1 << 31))
916 /* Byte 0 is level count, not a descriptor */
917 for (j = 1 ; j < 16 ; j++)
918 intel_tlb_lookup(desc[j]);
922 static const struct cpu_dev intel_cpu_dev = {
924 .c_ident = { "GenuineIntel" },
927 { .family = 4, .model_names =
929 [0] = "486 DX-25/33",
940 { .family = 5, .model_names =
942 [0] = "Pentium 60/66 A-step",
943 [1] = "Pentium 60/66",
944 [2] = "Pentium 75 - 200",
945 [3] = "OverDrive PODP5V83",
947 [7] = "Mobile Pentium 75 - 200",
948 [8] = "Mobile Pentium MMX",
949 [9] = "Quark SoC X1000",
952 { .family = 6, .model_names =
954 [0] = "Pentium Pro A-step",
956 [3] = "Pentium II (Klamath)",
957 [4] = "Pentium II (Deschutes)",
958 [5] = "Pentium II (Deschutes)",
959 [6] = "Mobile Pentium II",
960 [7] = "Pentium III (Katmai)",
961 [8] = "Pentium III (Coppermine)",
962 [10] = "Pentium III (Cascades)",
963 [11] = "Pentium III (Tualatin)",
966 { .family = 15, .model_names =
968 [0] = "Pentium 4 (Unknown)",
969 [1] = "Pentium 4 (Willamette)",
970 [2] = "Pentium 4 (Northwood)",
971 [4] = "Pentium 4 (Foster)",
972 [5] = "Pentium 4 (Foster)",
976 .legacy_cache_size = intel_size_cache,
978 .c_detect_tlb = intel_detect_tlb,
979 .c_early_init = early_init_intel,
980 .c_bsp_init = bsp_init_intel,
981 .c_init = init_intel,
982 .c_x86_vendor = X86_VENDOR_INTEL,
985 cpu_dev_register(intel_cpu_dev);
988 #define pr_fmt(fmt) "x86/split lock detection: " fmt
990 static const struct {
992 enum split_lock_detect_state state;
993 } sld_options[] __initconst = {
995 { "warn", sld_warn },
996 { "fatal", sld_fatal },
997 { "ratelimit:", sld_ratelimit },
1000 static struct ratelimit_state bld_ratelimit;
1002 static inline bool match_option(const char *arg, int arglen, const char *opt)
1004 int len = strlen(opt), ratelimit;
1006 if (strncmp(arg, opt, len))
1010 * Min ratelimit is 1 bus lock/sec.
1011 * Max ratelimit is 1000 bus locks/sec.
1013 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
1014 ratelimit > 0 && ratelimit <= 1000) {
1015 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
1016 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
1020 return len == arglen;
1023 static bool split_lock_verify_msr(bool on)
1027 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1030 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1032 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1033 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1035 rdmsrl(MSR_TEST_CTRL, tmp);
1039 static void __init sld_state_setup(void)
1041 enum split_lock_detect_state state = sld_warn;
1045 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1046 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1049 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1052 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1053 if (match_option(arg, ret, sld_options[i].option)) {
1054 state = sld_options[i].state;
1062 static void __init __split_lock_setup(void)
1064 if (!split_lock_verify_msr(false)) {
1065 pr_info("MSR access failed: Disabled\n");
1069 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1071 if (!split_lock_verify_msr(true)) {
1072 pr_info("MSR access failed: Disabled\n");
1076 /* Restore the MSR to its cached value. */
1077 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1079 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1083 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1084 * is not implemented as one thread could undo the setting of the other
1085 * thread immediately after dropping the lock anyway.
1087 static void sld_update_msr(bool on)
1089 u64 test_ctrl_val = msr_test_ctrl_cache;
1092 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1094 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1097 static void split_lock_init(void)
1100 * #DB for bus lock handles ratelimit and #AC for split lock is
1103 if (sld_state == sld_ratelimit) {
1104 split_lock_verify_msr(false);
1108 if (cpu_model_supports_sld)
1109 split_lock_verify_msr(sld_state != sld_off);
1112 static void split_lock_warn(unsigned long ip)
1114 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1115 current->comm, current->pid, ip);
1118 * Disable the split lock detection for this task so it can make
1119 * progress and set TIF_SLD so the detection is re-enabled via
1120 * switch_to_sld() when the task is scheduled out.
1122 sld_update_msr(false);
1123 set_tsk_thread_flag(current, TIF_SLD);
1126 bool handle_guest_split_lock(unsigned long ip)
1128 if (sld_state == sld_warn) {
1129 split_lock_warn(ip);
1133 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1134 current->comm, current->pid,
1135 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1137 current->thread.error_code = 0;
1138 current->thread.trap_nr = X86_TRAP_AC;
1139 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1142 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1144 static void bus_lock_init(void)
1148 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1151 rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1153 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1154 (sld_state == sld_warn || sld_state == sld_fatal)) ||
1155 sld_state == sld_off) {
1157 * Warn and fatal are handled by #AC for split lock if #AC for
1158 * split lock is supported.
1160 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1162 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1165 wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1168 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1170 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1172 split_lock_warn(regs->ip);
1176 void handle_bus_lock(struct pt_regs *regs)
1178 switch (sld_state) {
1182 /* Enforce no more than bld_ratelimit bus locks/sec. */
1183 while (!__ratelimit(&bld_ratelimit))
1185 /* Warn on the bus lock. */
1188 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1189 current->comm, current->pid, regs->ip);
1192 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1198 * This function is called only when switching between tasks with
1199 * different split-lock detection modes. It sets the MSR for the
1200 * mode of the new task. This is right most of the time, but since
1201 * the MSR is shared by hyperthreads on a physical core there can
1202 * be glitches when the two threads need different modes.
1204 void switch_to_sld(unsigned long tifn)
1206 sld_update_msr(!(tifn & _TIF_SLD));
1210 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should
1211 * only be trusted if it is confirmed that a CPU model implements a
1212 * specific feature at a particular bit position.
1214 * The possible driver data field values:
1216 * - 0: CPU models that are known to have the per-core split-lock detection
1217 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1219 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1220 * bit 5 to enumerate the per-core split-lock detection feature.
1222 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1223 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1224 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1225 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1226 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
1227 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
1228 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
1229 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1),
1230 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1),
1231 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 1),
1232 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 1),
1233 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 1),
1237 static void __init split_lock_setup(struct cpuinfo_x86 *c)
1239 const struct x86_cpu_id *m;
1242 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1245 m = x86_match_cpu(split_lock_cpu_ids);
1249 switch (m->driver_data) {
1253 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1255 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1256 if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))
1263 cpu_model_supports_sld = true;
1264 __split_lock_setup();
1267 static void sld_state_show(void)
1269 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1270 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1273 switch (sld_state) {
1275 pr_info("disabled\n");
1278 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1279 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1280 else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1281 pr_info("#DB: warning on user-space bus_locks\n");
1284 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1285 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1286 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1287 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1288 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1289 " from non-WB" : "");
1293 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1294 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1299 void __init sld_setup(struct cpuinfo_x86 *c)
1301 split_lock_setup(c);
1306 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
1309 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1311 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1312 * a hybrid processor. If the processor is not hybrid, returns 0.
1314 u8 get_this_hybrid_cpu_type(void)
1316 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1319 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;