1 // SPDX-License-Identifier: GPL-2.0+
3 * Hygon Processor Support for Linux
5 * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
7 * Author: Pu Wen <puwen@hygon.cn>
14 #include <asm/cacheinfo.h>
15 #include <asm/spec-ctrl.h>
16 #include <asm/delay.h>
20 #define APICID_SOCKET_ID_BIT 6
23 * nodes_per_socket: Stores the number of nodes per socket.
24 * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
26 static u32 nodes_per_socket = 1;
30 * To workaround broken NUMA config. Read the comment in
33 static int nearby_node(int apicid)
37 for (i = apicid - 1; i >= 0; i--) {
38 node = __apicid_to_node[i];
39 if (node != NUMA_NO_NODE && node_online(node))
42 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
43 node = __apicid_to_node[i];
44 if (node != NUMA_NO_NODE && node_online(node))
47 return first_node(node_online_map); /* Shouldn't happen */
51 static void hygon_get_topology_early(struct cpuinfo_x86 *c)
53 if (cpu_has(c, X86_FEATURE_TOPOEXT))
54 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
58 * Fixup core topology information for
59 * (1) Hygon multi-node processors
60 * Assumption: Number of cores in each internal node is the same.
61 * (2) Hygon processors supporting compute units
63 static void hygon_get_topology(struct cpuinfo_x86 *c)
65 int cpu = smp_processor_id();
67 /* get information required for multi-node processors */
68 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
70 u32 eax, ebx, ecx, edx;
72 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
74 c->cpu_die_id = ecx & 0xff;
76 c->cpu_core_id = ebx & 0xff;
78 if (smp_num_siblings > 1)
79 c->x86_max_cores /= smp_num_siblings;
82 * In case leaf B is available, use it to derive
83 * topology information.
85 err = detect_extended_topology(c);
87 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
89 /* Socket ID is ApicId[6] for these processors. */
90 c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
92 cacheinfo_hygon_init_llc_id(c, cpu);
93 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
96 rdmsrl(MSR_FAM10H_NODE_ID, value);
97 c->cpu_die_id = value & 7;
99 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
103 if (nodes_per_socket > 1)
104 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
108 * On Hygon setup the lower bits of the APIC id distinguish the cores.
109 * Assumes number of cores is a power of two.
111 static void hygon_detect_cmp(struct cpuinfo_x86 *c)
114 int cpu = smp_processor_id();
116 bits = c->x86_coreid_bits;
117 /* Low order bits define the core id (index of core in socket) */
118 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
119 /* Convert the initial APIC ID into the socket ID */
120 c->phys_proc_id = c->initial_apicid >> bits;
121 /* use socket ID also for last level cache */
122 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
125 static void srat_detect_node(struct cpuinfo_x86 *c)
128 int cpu = smp_processor_id();
130 unsigned int apicid = c->apicid;
132 node = numa_cpu_node(cpu);
133 if (node == NUMA_NO_NODE)
134 node = per_cpu(cpu_llc_id, cpu);
137 * On multi-fabric platform (e.g. Numascale NumaChip) a
138 * platform-specific handler needs to be called to fixup some
141 if (x86_cpuinit.fixup_cpu_id)
142 x86_cpuinit.fixup_cpu_id(c, node);
144 if (!node_online(node)) {
146 * Two possibilities here:
148 * - The CPU is missing memory and no node was created. In
149 * that case try picking one from a nearby CPU.
151 * - The APIC IDs differ from the HyperTransport node IDs.
152 * Assume they are all increased by a constant offset, but
153 * in the same order as the HT nodeids. If that doesn't
154 * result in a usable node fall back to the path for the
157 * This workaround operates directly on the mapping between
158 * APIC ID and NUMA node, assuming certain relationship
159 * between APIC ID, HT node ID and NUMA topology. As going
160 * through CPU mapping may alter the outcome, directly
161 * access __apicid_to_node[].
163 int ht_nodeid = c->initial_apicid;
165 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
166 node = __apicid_to_node[ht_nodeid];
167 /* Pick a nearby node */
168 if (!node_online(node))
169 node = nearby_node(apicid);
171 numa_set_node(cpu, node);
175 static void early_init_hygon_mc(struct cpuinfo_x86 *c)
178 unsigned int bits, ecx;
180 /* Multi core CPU? */
181 if (c->extended_cpuid_level < 0x80000008)
184 ecx = cpuid_ecx(0x80000008);
186 c->x86_max_cores = (ecx & 0xff) + 1;
188 /* CPU telling us the core id bits shift? */
189 bits = (ecx >> 12) & 0xF;
191 /* Otherwise recompute */
193 while ((1 << bits) < c->x86_max_cores)
197 c->x86_coreid_bits = bits;
201 static void bsp_init_hygon(struct cpuinfo_x86 *c)
203 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
206 rdmsrl(MSR_K7_HWCR, val);
207 if (!(val & BIT(24)))
208 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
211 if (cpu_has(c, X86_FEATURE_MWAITX))
214 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
217 ecx = cpuid_ecx(0x8000001e);
218 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
219 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
222 rdmsrl(MSR_FAM10H_NODE_ID, value);
223 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
226 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
227 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
229 * Try to cache the base value so further operations can
230 * avoid RMW. If that faults, do not enable SSBD.
232 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
233 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
234 setup_force_cpu_cap(X86_FEATURE_SSBD);
235 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
240 static void early_init_hygon(struct cpuinfo_x86 *c)
244 early_init_hygon_mc(c);
246 set_cpu_cap(c, X86_FEATURE_K8);
248 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
251 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
252 * with P/T states and does not stop in deep C-states
254 if (c->x86_power & (1 << 8)) {
255 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
256 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
259 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
260 if (c->x86_power & BIT(12))
261 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
263 /* Bit 14 indicates the Runtime Average Power Limit interface. */
264 if (c->x86_power & BIT(14))
265 set_cpu_cap(c, X86_FEATURE_RAPL);
268 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
271 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
273 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we
274 * can safely set X86_FEATURE_EXTD_APICID unconditionally.
276 if (boot_cpu_has(X86_FEATURE_APIC))
277 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
281 * This is only needed to tell the kernel whether to use VMCALL
282 * and VMMCALL. VMMCALL is never executed except under virt, so
283 * we can set it unconditionally.
285 set_cpu_cap(c, X86_FEATURE_VMMCALL);
287 hygon_get_topology_early(c);
290 static void init_hygon(struct cpuinfo_x86 *c)
295 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
296 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
298 clear_cpu_cap(c, 0*32+31);
300 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
302 /* get apicid instead of initial apic id from cpuid */
303 c->apicid = hard_smp_processor_id();
305 set_cpu_cap(c, X86_FEATURE_ZEN);
306 set_cpu_cap(c, X86_FEATURE_CPB);
308 cpu_detect_cache_sizes(c);
311 hygon_get_topology(c);
314 init_hygon_cacheinfo(c);
316 if (cpu_has(c, X86_FEATURE_XMM2)) {
318 * Use LFENCE for execution serialization. On families which
319 * don't have that MSR, LFENCE is already serializing.
320 * msr_set_bit() uses the safe accessors, too, even if the MSR
323 msr_set_bit(MSR_F10H_DECFG,
324 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
326 /* A serializing LFENCE stops RDTSC speculation */
327 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
331 * Hygon processors have APIC timer running in deep C states.
333 set_cpu_cap(c, X86_FEATURE_ARAT);
335 /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
336 if (!cpu_has(c, X86_FEATURE_XENPV))
337 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
339 check_null_seg_clears_base(c);
342 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
344 u32 ebx, eax, ecx, edx;
347 if (c->extended_cpuid_level < 0x80000006)
350 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
352 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
353 tlb_lli_4k[ENTRIES] = ebx & mask;
355 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
356 if (!((eax >> 16) & mask))
357 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
359 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
361 /* a 4M entry uses two 2M entries */
362 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
364 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
366 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
367 tlb_lli_2m[ENTRIES] = eax & 0xff;
369 tlb_lli_2m[ENTRIES] = eax & mask;
371 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
374 static const struct cpu_dev hygon_cpu_dev = {
376 .c_ident = { "HygonGenuine" },
377 .c_early_init = early_init_hygon,
378 .c_detect_tlb = cpu_detect_tlb_hygon,
379 .c_bsp_init = bsp_init_hygon,
380 .c_init = init_hygon,
381 .c_x86_vendor = X86_VENDOR_HYGON,
384 cpu_dev_register(hygon_cpu_dev);