1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
36 #include <asm/fpu/internal.h>
38 #include <linux/numa.h>
44 #include <asm/microcode.h>
45 #include <asm/microcode_intel.h>
46 #include <asm/intel-family.h>
47 #include <asm/cpu_device_id.h>
49 #ifdef CONFIG_X86_LOCAL_APIC
50 #include <asm/uv/uv.h>
55 /* all of these masks are initialized in setup_cpu_local_masks() */
56 cpumask_var_t cpu_initialized_mask;
57 cpumask_var_t cpu_callout_mask;
58 cpumask_var_t cpu_callin_mask;
60 /* representing cpus for which sibling maps can be computed */
61 cpumask_var_t cpu_sibling_setup_mask;
63 /* correctly size the local cpu masks */
64 void __init setup_cpu_local_masks(void)
66 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
67 alloc_bootmem_cpumask_var(&cpu_callin_mask);
68 alloc_bootmem_cpumask_var(&cpu_callout_mask);
69 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
72 static void default_init(struct cpuinfo_x86 *c)
75 cpu_detect_cache_sizes(c);
77 /* Not much we can do here... */
78 /* Check if at least it has cpuid */
79 if (c->cpuid_level == -1) {
80 /* No cpuid. It must be an ancient CPU */
82 strcpy(c->x86_model_id, "486");
84 strcpy(c->x86_model_id, "386");
89 static const struct cpu_dev default_cpu = {
90 .c_init = default_init,
91 .c_vendor = "Unknown",
92 .c_x86_vendor = X86_VENDOR_UNKNOWN,
95 static const struct cpu_dev *this_cpu = &default_cpu;
97 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(struct gdt_page, gdt_page) = { .gdt = {
100 * We need valid kernel segments for data and code in long mode too
101 * IRET will check the segment types kkeil 2000/10/28
102 * Also sysret mandates a special GDT layout
104 * TLS descriptors are currently at a different place compared to i386.
105 * Hopefully nobody expects them at a fixed place (Wine?)
107 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
112 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
119 * Segments used for calling PnP BIOS have byte granularity.
120 * They code segments and data segments have fixed 64k limits,
121 * the transfer segment sizes are set at run time.
124 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
126 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
128 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
130 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
134 * The APM segments have byte granularity and their bases
135 * are set at run time. All have 64k limits.
138 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
140 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
142 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
144 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
146 GDT_STACK_CANARY_INIT
149 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
151 static int __init x86_mpx_setup(char *s)
153 /* require an exact match without trailing characters */
157 /* do not emit a message if the feature is not present */
158 if (!boot_cpu_has(X86_FEATURE_MPX))
161 setup_clear_cpu_cap(X86_FEATURE_MPX);
162 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
165 __setup("nompx", x86_mpx_setup);
168 static int __init x86_pcid_setup(char *s)
170 /* require an exact match without trailing characters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_PCID))
178 setup_clear_cpu_cap(X86_FEATURE_PCID);
179 pr_info("nopcid: PCID feature disabled\n");
182 __setup("nopcid", x86_pcid_setup);
185 static int __init x86_noinvpcid_setup(char *s)
187 /* noinvpcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_INVPCID))
195 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
196 pr_info("noinvpcid: INVPCID feature disabled\n");
199 early_param("noinvpcid", x86_noinvpcid_setup);
202 static int cachesize_override = -1;
203 static int disable_x86_serial_nr = 1;
205 static int __init cachesize_setup(char *str)
207 get_option(&str, &cachesize_override);
210 __setup("cachesize=", cachesize_setup);
212 static int __init x86_sep_setup(char *s)
214 setup_clear_cpu_cap(X86_FEATURE_SEP);
217 __setup("nosep", x86_sep_setup);
219 /* Standard macro to see if a specific flag is changeable */
220 static inline int flag_is_changeable_p(u32 flag)
225 * Cyrix and IDT cpus allow disabling of CPUID
226 * so the code below may return different results
227 * when it is executed before and after enabling
228 * the CPUID. Add "volatile" to not allow gcc to
229 * optimize the subsequent calls to this function.
231 asm volatile ("pushfl \n\t"
242 : "=&r" (f1), "=&r" (f2)
245 return ((f1^f2) & flag) != 0;
248 /* Probe for the CPUID instruction */
249 int have_cpuid_p(void)
251 return flag_is_changeable_p(X86_EFLAGS_ID);
254 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
256 unsigned long lo, hi;
258 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
261 /* Disable processor serial number: */
263 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
265 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267 printk(KERN_NOTICE "CPU serial number disabled.\n");
268 clear_cpu_cap(c, X86_FEATURE_PN);
270 /* Disabling the serial number may affect the cpuid level */
271 c->cpuid_level = cpuid_eax(0);
274 static int __init x86_serial_nr_setup(char *s)
276 disable_x86_serial_nr = 0;
279 __setup("serialnumber", x86_serial_nr_setup);
281 static inline int flag_is_changeable_p(u32 flag)
285 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
290 static __init int setup_disable_smep(char *arg)
292 setup_clear_cpu_cap(X86_FEATURE_SMEP);
295 __setup("nosmep", setup_disable_smep);
297 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
299 if (cpu_has(c, X86_FEATURE_SMEP))
300 cr4_set_bits(X86_CR4_SMEP);
303 static __init int setup_disable_smap(char *arg)
305 setup_clear_cpu_cap(X86_FEATURE_SMAP);
308 __setup("nosmap", setup_disable_smap);
310 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
312 unsigned long eflags = native_save_fl();
314 /* This should have been cleared long ago */
315 BUG_ON(eflags & X86_EFLAGS_AC);
317 if (cpu_has(c, X86_FEATURE_SMAP)) {
318 #ifdef CONFIG_X86_SMAP
319 cr4_set_bits(X86_CR4_SMAP);
321 cr4_clear_bits(X86_CR4_SMAP);
326 static void setup_pcid(struct cpuinfo_x86 *c)
328 if (cpu_has(c, X86_FEATURE_PCID)) {
329 if (cpu_has(c, X86_FEATURE_PGE) || kaiser_enabled) {
330 cr4_set_bits(X86_CR4_PCIDE);
332 * INVPCID has two "groups" of types:
333 * 1/2: Invalidate an individual address
334 * 3/4: Invalidate all contexts
336 * 1/2 take a PCID, but 3/4 do not. So, 3/4
337 * ignore the PCID argument in the descriptor.
338 * But, we have to be careful not to call 1/2
339 * with an actual non-zero PCID in them before
340 * we do the above cr4_set_bits().
342 if (cpu_has(c, X86_FEATURE_INVPCID))
343 set_cpu_cap(c, X86_FEATURE_INVPCID_SINGLE);
346 * flush_tlb_all(), as currently implemented, won't
347 * work if PCID is on but PGE is not. Since that
348 * combination doesn't exist on real hardware, there's
349 * no reason to try to fully support it, but it's
350 * polite to avoid corrupting data if we're on
351 * an improperly configured VM.
353 clear_cpu_cap(c, X86_FEATURE_PCID);
360 * Some CPU features depend on higher CPUID levels, which may not always
361 * be available due to CPUID level capping or broken virtualization
362 * software. Add those features to this table to auto-disable them.
364 struct cpuid_dependent_feature {
369 static const struct cpuid_dependent_feature
370 cpuid_dependent_features[] = {
371 { X86_FEATURE_MWAIT, 0x00000005 },
372 { X86_FEATURE_DCA, 0x00000009 },
373 { X86_FEATURE_XSAVE, 0x0000000d },
377 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
379 const struct cpuid_dependent_feature *df;
381 for (df = cpuid_dependent_features; df->feature; df++) {
383 if (!cpu_has(c, df->feature))
386 * Note: cpuid_level is set to -1 if unavailable, but
387 * extended_extended_level is set to 0 if unavailable
388 * and the legitimate extended levels are all negative
389 * when signed; hence the weird messing around with
392 if (!((s32)df->level < 0 ?
393 (u32)df->level > (u32)c->extended_cpuid_level :
394 (s32)df->level > (s32)c->cpuid_level))
397 clear_cpu_cap(c, df->feature);
402 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
403 x86_cap_flag(df->feature), df->level);
408 * Naming convention should be: <Name> [(<Codename>)]
409 * This table only is used unless init_<vendor>() below doesn't set it;
410 * in particular, if CPUID levels 0x80000002..4 are supported, this
414 /* Look up CPU names by table lookup. */
415 static const char *table_lookup_model(struct cpuinfo_x86 *c)
418 const struct legacy_cpu_model_info *info;
420 if (c->x86_model >= 16)
421 return NULL; /* Range check */
426 info = this_cpu->legacy_models;
428 while (info->family) {
429 if (info->family == c->x86)
430 return info->model_names[c->x86_model];
434 return NULL; /* Not found */
437 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
438 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
440 void load_percpu_segment(int cpu)
443 loadsegment(fs, __KERNEL_PERCPU);
446 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
448 load_stack_canary_segment();
452 * Current gdt points %fs at the "master" per-cpu area: after this,
453 * it's on the real one.
455 void switch_to_new_gdt(int cpu)
457 struct desc_ptr gdt_descr;
459 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
460 gdt_descr.size = GDT_SIZE - 1;
461 load_gdt(&gdt_descr);
462 /* Reload the per-cpu base */
464 load_percpu_segment(cpu);
467 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
469 static void get_model_name(struct cpuinfo_x86 *c)
474 if (c->extended_cpuid_level < 0x80000004)
477 v = (unsigned int *)c->x86_model_id;
478 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
479 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
480 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
481 c->x86_model_id[48] = 0;
483 /* Trim whitespace */
484 p = q = s = &c->x86_model_id[0];
490 /* Note the last non-whitespace index */
500 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
502 unsigned int n, dummy, ebx, ecx, edx, l2size;
504 n = c->extended_cpuid_level;
506 if (n >= 0x80000005) {
507 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
508 c->x86_cache_size = (ecx>>24) + (edx>>24);
510 /* On K8 L1 TLB is inclusive, so don't count it */
515 if (n < 0x80000006) /* Some chips just has a large L1. */
518 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
522 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
524 /* do processor-specific cache resizing */
525 if (this_cpu->legacy_cache_size)
526 l2size = this_cpu->legacy_cache_size(c, l2size);
528 /* Allow user to override all this if necessary. */
529 if (cachesize_override != -1)
530 l2size = cachesize_override;
533 return; /* Again, no L2 cache is possible */
536 c->x86_cache_size = l2size;
539 u16 __read_mostly tlb_lli_4k[NR_INFO];
540 u16 __read_mostly tlb_lli_2m[NR_INFO];
541 u16 __read_mostly tlb_lli_4m[NR_INFO];
542 u16 __read_mostly tlb_lld_4k[NR_INFO];
543 u16 __read_mostly tlb_lld_2m[NR_INFO];
544 u16 __read_mostly tlb_lld_4m[NR_INFO];
545 u16 __read_mostly tlb_lld_1g[NR_INFO];
547 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
549 if (this_cpu->c_detect_tlb)
550 this_cpu->c_detect_tlb(c);
552 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
553 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
554 tlb_lli_4m[ENTRIES]);
556 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
557 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
558 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
561 void detect_ht(struct cpuinfo_x86 *c)
564 u32 eax, ebx, ecx, edx;
565 int index_msb, core_bits;
568 if (!cpu_has(c, X86_FEATURE_HT))
571 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
574 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
577 cpuid(1, &eax, &ebx, &ecx, &edx);
579 smp_num_siblings = (ebx & 0xff0000) >> 16;
581 if (smp_num_siblings == 1) {
582 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
586 if (smp_num_siblings <= 1)
589 index_msb = get_count_order(smp_num_siblings);
590 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
592 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
594 index_msb = get_count_order(smp_num_siblings);
596 core_bits = get_count_order(c->x86_max_cores);
598 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
599 ((1 << core_bits) - 1);
602 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
603 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
605 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
612 static void get_cpu_vendor(struct cpuinfo_x86 *c)
614 char *v = c->x86_vendor_id;
617 for (i = 0; i < X86_VENDOR_NUM; i++) {
621 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
622 (cpu_devs[i]->c_ident[1] &&
623 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
625 this_cpu = cpu_devs[i];
626 c->x86_vendor = this_cpu->c_x86_vendor;
632 "CPU: vendor_id '%s' unknown, using generic init.\n" \
633 "CPU: Your system may be unstable.\n", v);
635 c->x86_vendor = X86_VENDOR_UNKNOWN;
636 this_cpu = &default_cpu;
639 void cpu_detect(struct cpuinfo_x86 *c)
641 /* Get vendor name */
642 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
643 (unsigned int *)&c->x86_vendor_id[0],
644 (unsigned int *)&c->x86_vendor_id[8],
645 (unsigned int *)&c->x86_vendor_id[4]);
648 /* Intel-defined flags: level 0x00000001 */
649 if (c->cpuid_level >= 0x00000001) {
650 u32 junk, tfms, cap0, misc;
652 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
653 c->x86 = (tfms >> 8) & 0xf;
654 c->x86_model = (tfms >> 4) & 0xf;
655 c->x86_stepping = tfms & 0xf;
658 c->x86 += (tfms >> 20) & 0xff;
660 c->x86_model += ((tfms >> 16) & 0xf) << 4;
662 if (cap0 & (1<<19)) {
663 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
664 c->x86_cache_alignment = c->x86_clflush_size;
669 static void apply_forced_caps(struct cpuinfo_x86 *c)
673 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
674 c->x86_capability[i] &= ~cpu_caps_cleared[i];
675 c->x86_capability[i] |= cpu_caps_set[i];
679 static void init_speculation_control(struct cpuinfo_x86 *c)
682 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
683 * and they also have a different bit for STIBP support. Also,
684 * a hypervisor might have set the individual AMD bits even on
685 * Intel CPUs, for finer-grained selection of what's available.
687 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
688 set_cpu_cap(c, X86_FEATURE_IBRS);
689 set_cpu_cap(c, X86_FEATURE_IBPB);
690 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
693 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
694 set_cpu_cap(c, X86_FEATURE_STIBP);
696 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
697 cpu_has(c, X86_FEATURE_VIRT_SSBD))
698 set_cpu_cap(c, X86_FEATURE_SSBD);
700 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
701 set_cpu_cap(c, X86_FEATURE_IBRS);
702 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
705 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
706 set_cpu_cap(c, X86_FEATURE_IBPB);
708 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
709 set_cpu_cap(c, X86_FEATURE_STIBP);
710 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
713 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
714 set_cpu_cap(c, X86_FEATURE_SSBD);
715 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
716 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
720 void get_cpu_cap(struct cpuinfo_x86 *c)
722 u32 eax, ebx, ecx, edx;
724 /* Intel-defined flags: level 0x00000001 */
725 if (c->cpuid_level >= 0x00000001) {
726 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
728 c->x86_capability[CPUID_1_ECX] = ecx;
729 c->x86_capability[CPUID_1_EDX] = edx;
732 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
733 if (c->cpuid_level >= 0x00000006)
734 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
736 /* Additional Intel-defined flags: level 0x00000007 */
737 if (c->cpuid_level >= 0x00000007) {
738 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
739 c->x86_capability[CPUID_7_0_EBX] = ebx;
740 c->x86_capability[CPUID_7_ECX] = ecx;
741 c->x86_capability[CPUID_7_EDX] = edx;
744 /* Extended state features: level 0x0000000d */
745 if (c->cpuid_level >= 0x0000000d) {
746 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
748 c->x86_capability[CPUID_D_1_EAX] = eax;
751 /* Additional Intel-defined flags: level 0x0000000F */
752 if (c->cpuid_level >= 0x0000000F) {
754 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
755 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
756 c->x86_capability[CPUID_F_0_EDX] = edx;
758 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
759 /* will be overridden if occupancy monitoring exists */
760 c->x86_cache_max_rmid = ebx;
762 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
763 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
764 c->x86_capability[CPUID_F_1_EDX] = edx;
766 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) {
767 c->x86_cache_max_rmid = ecx;
768 c->x86_cache_occ_scale = ebx;
771 c->x86_cache_max_rmid = -1;
772 c->x86_cache_occ_scale = -1;
776 /* AMD-defined flags: level 0x80000001 */
777 eax = cpuid_eax(0x80000000);
778 c->extended_cpuid_level = eax;
780 if ((eax & 0xffff0000) == 0x80000000) {
781 if (eax >= 0x80000001) {
782 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
784 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
785 c->x86_capability[CPUID_8000_0001_EDX] = edx;
789 if (c->extended_cpuid_level >= 0x80000007) {
790 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
792 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
796 if (c->extended_cpuid_level >= 0x80000008) {
797 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
799 c->x86_virt_bits = (eax >> 8) & 0xff;
800 c->x86_phys_bits = eax & 0xff;
801 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
804 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
805 c->x86_phys_bits = 36;
808 c->x86_cache_bits = c->x86_phys_bits;
810 if (c->extended_cpuid_level >= 0x8000000a)
811 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
813 init_scattered_cpuid_features(c);
814 init_speculation_control(c);
817 * Clear/Set all flags overridden by options, after probe.
818 * This needs to happen each time we re-probe, which may happen
819 * several times during CPU initialization.
821 apply_forced_caps(c);
824 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
830 * First of all, decide if this is a 486 or higher
831 * It's a 486 if we can modify the AC flag
833 if (flag_is_changeable_p(X86_EFLAGS_AC))
838 for (i = 0; i < X86_VENDOR_NUM; i++)
839 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
840 c->x86_vendor_id[0] = 0;
841 cpu_devs[i]->c_identify(c);
842 if (c->x86_vendor_id[0]) {
850 #define NO_SPECULATION BIT(0)
851 #define NO_MELTDOWN BIT(1)
852 #define NO_SSB BIT(2)
853 #define NO_L1TF BIT(3)
854 #define NO_MDS BIT(4)
855 #define MSBDS_ONLY BIT(5)
856 #define NO_SWAPGS BIT(6)
857 #define NO_ITLB_MULTIHIT BIT(7)
859 #define VULNWL(_vendor, _family, _model, _whitelist) \
860 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
862 #define VULNWL_INTEL(model, whitelist) \
863 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
865 #define VULNWL_AMD(family, whitelist) \
866 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
868 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
869 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
870 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
871 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
872 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
875 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
876 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
877 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
878 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
879 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
881 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
882 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
883 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
884 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
885 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
886 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
888 VULNWL_INTEL(CORE_YONAH, NO_SSB),
890 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
892 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
893 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
894 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
897 * Technically, swapgs isn't serializing on AMD (despite it previously
898 * being documented as such in the APM). But according to AMD, %gs is
899 * updated non-speculatively, and the issuing of %gs-relative memory
900 * operands will be blocked until the %gs update completes, which is
901 * good enough for our purposes.
904 /* AMD Family 0xf - 0x12 */
905 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
906 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
907 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
908 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
910 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
911 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
915 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
916 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
917 INTEL_FAM6_##model, steppings, \
918 X86_FEATURE_ANY, issues)
922 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
923 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
924 VULNBL_INTEL_STEPPINGS(HASWELL_CORE, X86_STEPPING_ANY, SRBDS),
925 VULNBL_INTEL_STEPPINGS(HASWELL_ULT, X86_STEPPING_ANY, SRBDS),
926 VULNBL_INTEL_STEPPINGS(HASWELL_GT3E, X86_STEPPING_ANY, SRBDS),
927 VULNBL_INTEL_STEPPINGS(BROADWELL_GT3E, X86_STEPPING_ANY, SRBDS),
928 VULNBL_INTEL_STEPPINGS(BROADWELL_CORE, X86_STEPPING_ANY, SRBDS),
929 VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS),
930 VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP, X86_STEPPING_ANY, SRBDS),
931 VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPINGS(0x0, 0xC), SRBDS),
932 VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPINGS(0x0, 0xD), SRBDS),
936 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
938 const struct x86_cpu_id *m = x86_match_cpu(table);
940 return m && !!(m->driver_data & which);
943 u64 x86_read_arch_cap_msr(void)
947 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
948 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
953 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
955 u64 ia32_cap = x86_read_arch_cap_msr();
957 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
958 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
959 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
960 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
962 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
965 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
966 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
968 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
969 !(ia32_cap & ARCH_CAP_SSB_NO) &&
970 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
971 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
973 if (ia32_cap & ARCH_CAP_IBRS_ALL)
974 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
976 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
977 !(ia32_cap & ARCH_CAP_MDS_NO)) {
978 setup_force_cpu_bug(X86_BUG_MDS);
979 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
980 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
983 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
984 setup_force_cpu_bug(X86_BUG_SWAPGS);
987 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
988 * - TSX is supported or
989 * - TSX_CTRL is present
991 * TSX_CTRL check is needed for cases when TSX could be disabled before
992 * the kernel boot e.g. kexec.
993 * TSX_CTRL check alone is not sufficient for cases when the microcode
994 * update is not present or running as guest that don't get TSX_CTRL.
996 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
997 (cpu_has(c, X86_FEATURE_RTM) ||
998 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
999 setup_force_cpu_bug(X86_BUG_TAA);
1002 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1003 * in the vulnerability blacklist.
1005 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1006 cpu_has(c, X86_FEATURE_RDSEED)) &&
1007 cpu_matches(cpu_vuln_blacklist, SRBDS))
1008 setup_force_cpu_bug(X86_BUG_SRBDS);
1010 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1013 /* Rogue Data Cache Load? No! */
1014 if (ia32_cap & ARCH_CAP_RDCL_NO)
1017 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1019 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1022 setup_force_cpu_bug(X86_BUG_L1TF);
1026 * Do minimum CPU detection early.
1027 * Fields really needed: vendor, cpuid_level, family, model, mask,
1029 * The others are not touched to avoid unwanted side effects.
1031 * WARNING: this function is only called on the BP. Don't add code here
1032 * that is supposed to run on all CPUs.
1034 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1036 #ifdef CONFIG_X86_64
1037 c->x86_clflush_size = 64;
1038 c->x86_phys_bits = 36;
1039 c->x86_virt_bits = 48;
1041 c->x86_clflush_size = 32;
1042 c->x86_phys_bits = 32;
1043 c->x86_virt_bits = 32;
1045 c->x86_cache_alignment = c->x86_clflush_size;
1047 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1048 c->extended_cpuid_level = 0;
1050 if (!have_cpuid_p())
1051 identify_cpu_without_cpuid(c);
1053 /* cyrix could have cpuid enabled via c_identify()*/
1054 if (have_cpuid_p()) {
1059 if (this_cpu->c_early_init)
1060 this_cpu->c_early_init(c);
1063 filter_cpuid_features(c, false);
1065 if (this_cpu->c_bsp_init)
1066 this_cpu->c_bsp_init(c);
1069 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1071 cpu_set_bug_bits(c);
1073 fpu__init_system(c);
1075 #ifdef CONFIG_X86_32
1077 * Regardless of whether PCID is enumerated, the SDM says
1078 * that it can't be enabled in 32-bit mode.
1080 setup_clear_cpu_cap(X86_FEATURE_PCID);
1084 void __init early_cpu_init(void)
1086 const struct cpu_dev *const *cdev;
1089 #ifdef CONFIG_PROCESSOR_SELECT
1090 printk(KERN_INFO "KERNEL supported cpus:\n");
1093 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1094 const struct cpu_dev *cpudev = *cdev;
1096 if (count >= X86_VENDOR_NUM)
1098 cpu_devs[count] = cpudev;
1101 #ifdef CONFIG_PROCESSOR_SELECT
1105 for (j = 0; j < 2; j++) {
1106 if (!cpudev->c_ident[j])
1108 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
1109 cpudev->c_ident[j]);
1114 early_identify_cpu(&boot_cpu_data);
1118 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1119 * unfortunately, that's not true in practice because of early VIA
1120 * chips and (more importantly) broken virtualizers that are not easy
1121 * to detect. In the latter case it doesn't even *fail* reliably, so
1122 * probing for it doesn't even work. Disable it completely on 32-bit
1123 * unless we can find a reliable way to detect all the broken cases.
1124 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1126 static void detect_nopl(struct cpuinfo_x86 *c)
1128 #ifdef CONFIG_X86_32
1129 clear_cpu_cap(c, X86_FEATURE_NOPL);
1131 set_cpu_cap(c, X86_FEATURE_NOPL);
1135 static void generic_identify(struct cpuinfo_x86 *c)
1137 c->extended_cpuid_level = 0;
1139 if (!have_cpuid_p())
1140 identify_cpu_without_cpuid(c);
1142 /* cyrix could have cpuid enabled via c_identify()*/
1143 if (!have_cpuid_p())
1152 if (c->cpuid_level >= 0x00000001) {
1153 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1154 #ifdef CONFIG_X86_32
1156 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1158 c->apicid = c->initial_apicid;
1161 c->phys_proc_id = c->initial_apicid;
1164 get_model_name(c); /* Default name */
1169 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1172 * The heavy lifting of max_rmid and cache_occ_scale are handled
1173 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1174 * in case CQM bits really aren't there in this CPU.
1176 if (c != &boot_cpu_data) {
1177 boot_cpu_data.x86_cache_max_rmid =
1178 min(boot_cpu_data.x86_cache_max_rmid,
1179 c->x86_cache_max_rmid);
1184 * This does the hard work of actually picking apart the CPU stuff...
1186 static void identify_cpu(struct cpuinfo_x86 *c)
1190 c->loops_per_jiffy = loops_per_jiffy;
1191 c->x86_cache_size = 0;
1192 c->x86_vendor = X86_VENDOR_UNKNOWN;
1193 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1194 c->x86_vendor_id[0] = '\0'; /* Unset */
1195 c->x86_model_id[0] = '\0'; /* Unset */
1196 c->x86_max_cores = 1;
1197 c->x86_coreid_bits = 0;
1198 #ifdef CONFIG_X86_64
1199 c->x86_clflush_size = 64;
1200 c->x86_phys_bits = 36;
1201 c->x86_virt_bits = 48;
1203 c->cpuid_level = -1; /* CPUID not detected */
1204 c->x86_clflush_size = 32;
1205 c->x86_phys_bits = 32;
1206 c->x86_virt_bits = 32;
1208 c->x86_cache_alignment = c->x86_clflush_size;
1209 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1211 generic_identify(c);
1213 if (this_cpu->c_identify)
1214 this_cpu->c_identify(c);
1216 /* Clear/Set all flags overridden by options, after probe */
1217 apply_forced_caps(c);
1219 #ifdef CONFIG_X86_64
1220 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1224 * Vendor-specific initialization. In this section we
1225 * canonicalize the feature flags, meaning if there are
1226 * features a certain CPU supports which CPUID doesn't
1227 * tell us, CPUID claiming incorrect flags, or other bugs,
1228 * we handle them here.
1230 * At the end of this section, c->x86_capability better
1231 * indicate the features this CPU genuinely supports!
1233 if (this_cpu->c_init)
1234 this_cpu->c_init(c);
1236 /* Disable the PN if appropriate */
1237 squash_the_stupid_serial_number(c);
1239 /* Set up SMEP/SMAP */
1247 * The vendor-specific functions might have changed features.
1248 * Now we do "generic changes."
1251 /* Filter out anything that depends on CPUID levels we don't have */
1252 filter_cpuid_features(c, true);
1254 /* If the model name is still unset, do table lookup. */
1255 if (!c->x86_model_id[0]) {
1257 p = table_lookup_model(c);
1259 strcpy(c->x86_model_id, p);
1261 /* Last resort... */
1262 sprintf(c->x86_model_id, "%02x/%02x",
1263 c->x86, c->x86_model);
1266 #ifdef CONFIG_X86_64
1272 x86_init_cache_qos(c);
1275 * Clear/Set all flags overriden by options, need do it
1276 * before following smp all cpus cap AND.
1278 apply_forced_caps(c);
1281 * On SMP, boot_cpu_data holds the common feature set between
1282 * all CPUs; so make sure that we indicate which features are
1283 * common between the CPUs. The first time this routine gets
1284 * executed, c == &boot_cpu_data.
1286 if (c != &boot_cpu_data) {
1287 /* AND the already accumulated flags with these */
1288 for (i = 0; i < NCAPINTS; i++)
1289 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1291 /* OR, i.e. replicate the bug flags */
1292 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1293 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1296 /* Init Machine Check Exception if available. */
1299 select_idle_routine(c);
1302 numa_add_cpu(smp_processor_id());
1307 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1308 * on 32-bit kernels:
1310 #ifdef CONFIG_X86_32
1311 void enable_sep_cpu(void)
1313 struct tss_struct *tss;
1317 tss = &per_cpu(cpu_tss, cpu);
1319 if (!boot_cpu_has(X86_FEATURE_SEP))
1323 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1324 * see the big comment in struct x86_hw_tss's definition.
1327 tss->x86_tss.ss1 = __KERNEL_CS;
1328 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1330 wrmsr(MSR_IA32_SYSENTER_ESP,
1331 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1334 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1341 void __init identify_boot_cpu(void)
1343 identify_cpu(&boot_cpu_data);
1344 init_amd_e400_c1e_mask();
1345 #ifdef CONFIG_X86_32
1349 cpu_detect_tlb(&boot_cpu_data);
1354 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1356 BUG_ON(c == &boot_cpu_data);
1358 #ifdef CONFIG_X86_32
1362 x86_spec_ctrl_setup_ap();
1371 static const struct msr_range msr_range_array[] = {
1372 { 0x00000000, 0x00000418},
1373 { 0xc0000000, 0xc000040b},
1374 { 0xc0010000, 0xc0010142},
1375 { 0xc0011000, 0xc001103b},
1378 static void __print_cpu_msr(void)
1380 unsigned index_min, index_max;
1385 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1386 index_min = msr_range_array[i].min;
1387 index_max = msr_range_array[i].max;
1389 for (index = index_min; index < index_max; index++) {
1390 if (rdmsrl_safe(index, &val))
1392 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1397 static int show_msr;
1399 static __init int setup_show_msr(char *arg)
1403 get_option(&arg, &num);
1409 __setup("show_msr=", setup_show_msr);
1411 static __init int setup_noclflush(char *arg)
1413 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1414 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1417 __setup("noclflush", setup_noclflush);
1419 void print_cpu_info(struct cpuinfo_x86 *c)
1421 const char *vendor = NULL;
1423 if (c->x86_vendor < X86_VENDOR_NUM) {
1424 vendor = this_cpu->c_vendor;
1426 if (c->cpuid_level >= 0)
1427 vendor = c->x86_vendor_id;
1430 if (vendor && !strstr(c->x86_model_id, vendor))
1431 printk(KERN_CONT "%s ", vendor);
1433 if (c->x86_model_id[0])
1434 printk(KERN_CONT "%s", c->x86_model_id);
1436 printk(KERN_CONT "%d86", c->x86);
1438 printk(KERN_CONT " (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1440 if (c->x86_stepping || c->cpuid_level >= 0)
1441 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1443 printk(KERN_CONT ")\n");
1448 void print_cpu_msr(struct cpuinfo_x86 *c)
1450 if (c->cpu_index < show_msr)
1454 static __init int setup_disablecpuid(char *arg)
1458 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1459 setup_clear_cpu_cap(bit);
1465 __setup("clearcpuid=", setup_disablecpuid);
1467 #ifdef CONFIG_X86_64
1468 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1469 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1470 (unsigned long) debug_idt_table };
1472 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1473 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1476 * The following percpu variables are hot. Align current_task to
1477 * cacheline size such that they fall in the same cacheline.
1479 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1481 EXPORT_PER_CPU_SYMBOL(current_task);
1483 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1484 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1486 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1488 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1489 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1492 * Special IST stacks which the CPU switches to when it calls
1493 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1494 * limit), all of them are 4K, except the debug stack which
1497 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1498 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1499 [DEBUG_STACK - 1] = DEBUG_STKSZ
1502 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(char, exception_stacks
1503 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1505 /* May not be marked __init: used by software suspend */
1506 void syscall_init(void)
1509 * LSTAR and STAR live in a bit strange symbiosis.
1510 * They both write to the same internal register. STAR allows to
1511 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1513 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1514 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1516 #ifdef CONFIG_IA32_EMULATION
1517 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1519 * This only works on Intel CPUs.
1520 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1521 * This does not cause SYSENTER to jump to the wrong location, because
1522 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1524 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1525 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1526 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1528 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1529 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1530 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1531 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1534 /* Flags to clear on syscall */
1535 wrmsrl(MSR_SYSCALL_MASK,
1536 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1537 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1541 * Copies of the original ist values from the tss are only accessed during
1542 * debugging, no special alignment required.
1544 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1546 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1547 DEFINE_PER_CPU(int, debug_stack_usage);
1549 int is_debug_stack(unsigned long addr)
1551 return __this_cpu_read(debug_stack_usage) ||
1552 (addr <= __this_cpu_read(debug_stack_addr) &&
1553 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1555 NOKPROBE_SYMBOL(is_debug_stack);
1557 DEFINE_PER_CPU(u32, debug_idt_ctr);
1559 void debug_stack_set_zero(void)
1561 this_cpu_inc(debug_idt_ctr);
1564 NOKPROBE_SYMBOL(debug_stack_set_zero);
1566 void debug_stack_reset(void)
1568 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1570 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1573 NOKPROBE_SYMBOL(debug_stack_reset);
1575 #else /* CONFIG_X86_64 */
1577 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1578 EXPORT_PER_CPU_SYMBOL(current_task);
1579 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1580 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1583 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1584 * the top of the kernel stack. Use an extra percpu variable to track the
1585 * top of the kernel stack directly.
1587 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1588 (unsigned long)&init_thread_union + THREAD_SIZE;
1589 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1591 #ifdef CONFIG_CC_STACKPROTECTOR
1592 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1595 #endif /* CONFIG_X86_64 */
1598 * Clear all 6 debug registers:
1600 static void clear_all_debug_regs(void)
1604 for (i = 0; i < 8; i++) {
1605 /* Ignore db4, db5 */
1606 if ((i == 4) || (i == 5))
1615 * Restore debug regs if using kgdbwait and you have a kernel debugger
1616 * connection established.
1618 static void dbg_restore_debug_regs(void)
1620 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1621 arch_kgdb_ops.correct_hw_break();
1623 #else /* ! CONFIG_KGDB */
1624 #define dbg_restore_debug_regs()
1625 #endif /* ! CONFIG_KGDB */
1627 static void wait_for_master_cpu(int cpu)
1631 * wait for ACK from master CPU before continuing
1632 * with AP initialization
1634 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1635 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1641 * cpu_init() initializes state that is per-CPU. Some data is already
1642 * initialized (naturally) in the bootstrap process, such as the GDT
1643 * and IDT. We reload them nevertheless, this function acts as a
1644 * 'CPU state barrier', nothing should get across.
1645 * A lot of state is already set up in PDA init for 64 bit
1647 #ifdef CONFIG_X86_64
1651 struct orig_ist *oist;
1652 struct task_struct *me;
1653 struct tss_struct *t;
1655 int cpu = stack_smp_processor_id();
1658 wait_for_master_cpu(cpu);
1661 * Initialize the CR4 shadow before doing anything that could
1665 if (!kaiser_enabled) {
1667 * secondary_startup_64() deferred setting PGE in cr4:
1668 * probe_page_size_mask() sets it on the boot cpu,
1669 * but it needs to be set on each secondary cpu.
1671 cr4_set_bits(X86_CR4_PGE);
1675 * Load microcode on this cpu if a valid microcode is available.
1676 * This is early microcode loading procedure.
1680 t = &per_cpu(cpu_tss, cpu);
1681 oist = &per_cpu(orig_ist, cpu);
1684 if (this_cpu_read(numa_node) == 0 &&
1685 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1686 set_numa_node(early_cpu_to_node(cpu));
1691 pr_debug("Initializing CPU#%d\n", cpu);
1693 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1696 * Initialize the per-CPU GDT with the boot GDT,
1697 * and set up the GDT descriptor:
1700 switch_to_new_gdt(cpu);
1705 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1708 wrmsrl(MSR_FS_BASE, 0);
1709 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1716 * set up and load the per-CPU TSS
1718 if (!oist->ist[0]) {
1719 char *estacks = per_cpu(exception_stacks, cpu);
1721 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1722 estacks += exception_stack_sizes[v];
1723 oist->ist[v] = t->x86_tss.ist[v] =
1724 (unsigned long)estacks;
1725 if (v == DEBUG_STACK-1)
1726 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1730 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1733 * <= is required because the CPU will access up to
1734 * 8 bits beyond the end of the IO permission bitmap.
1736 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1737 t->io_bitmap[i] = ~0UL;
1739 atomic_inc(&init_mm.mm_count);
1740 me->active_mm = &init_mm;
1742 enter_lazy_tlb(&init_mm, me);
1744 load_sp0(t, ¤t->thread);
1745 set_tss_desc(cpu, t);
1747 load_mm_ldt(&init_mm);
1749 clear_all_debug_regs();
1750 dbg_restore_debug_regs();
1762 int cpu = smp_processor_id();
1763 struct task_struct *curr = current;
1764 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1765 struct thread_struct *thread = &curr->thread;
1767 wait_for_master_cpu(cpu);
1770 * Initialize the CR4 shadow before doing anything that could
1775 show_ucode_info_early();
1777 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1779 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1781 boot_cpu_has(X86_FEATURE_DE))
1782 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1785 switch_to_new_gdt(cpu);
1788 * Set up and load the per-CPU TSS and LDT
1790 atomic_inc(&init_mm.mm_count);
1791 curr->active_mm = &init_mm;
1793 enter_lazy_tlb(&init_mm, curr);
1795 load_sp0(t, thread);
1796 set_tss_desc(cpu, t);
1798 load_mm_ldt(&init_mm);
1800 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1802 #ifdef CONFIG_DOUBLEFAULT
1803 /* Set up doublefault TSS pointer in the GDT */
1804 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1807 clear_all_debug_regs();
1808 dbg_restore_debug_regs();
1814 static void bsp_resume(void)
1816 if (this_cpu->c_bsp_resume)
1817 this_cpu->c_bsp_resume(&boot_cpu_data);
1820 static struct syscore_ops cpu_syscore_ops = {
1821 .resume = bsp_resume,
1824 static int __init init_cpu_syscore(void)
1826 register_syscore_ops(&cpu_syscore_ops);
1829 core_initcall(init_cpu_syscore);