1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/utsname.h>
29 #include <asm/alternative.h>
30 #include <asm/cmdline.h>
31 #include <asm/stackprotector.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
49 #include <asm/fpu/internal.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
59 #include <asm/memtype.h>
60 #include <asm/microcode.h>
61 #include <asm/microcode_intel.h>
62 #include <asm/intel-family.h>
63 #include <asm/cpu_device_id.h>
64 #include <asm/uv/uv.h>
65 #include <asm/set_memory.h>
69 u32 elf_hwcap2 __read_mostly;
71 /* all of these masks are initialized in setup_cpu_local_masks() */
72 cpumask_var_t cpu_initialized_mask;
73 cpumask_var_t cpu_callout_mask;
74 cpumask_var_t cpu_callin_mask;
76 /* representing cpus for which sibling maps can be computed */
77 cpumask_var_t cpu_sibling_setup_mask;
79 /* Number of siblings per CPU package */
80 int smp_num_siblings = 1;
81 EXPORT_SYMBOL(smp_num_siblings);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
86 u16 get_llc_id(unsigned int cpu)
88 return per_cpu(cpu_llc_id, cpu);
90 EXPORT_SYMBOL_GPL(get_llc_id);
92 /* correctly size the local cpu masks */
93 void __init setup_cpu_local_masks(void)
95 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
96 alloc_bootmem_cpumask_var(&cpu_callin_mask);
97 alloc_bootmem_cpumask_var(&cpu_callout_mask);
98 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
101 static void default_init(struct cpuinfo_x86 *c)
104 cpu_detect_cache_sizes(c);
106 /* Not much we can do here... */
107 /* Check if at least it has cpuid */
108 if (c->cpuid_level == -1) {
109 /* No cpuid. It must be an ancient CPU */
111 strcpy(c->x86_model_id, "486");
112 else if (c->x86 == 3)
113 strcpy(c->x86_model_id, "386");
118 static const struct cpu_dev default_cpu = {
119 .c_init = default_init,
120 .c_vendor = "Unknown",
121 .c_x86_vendor = X86_VENDOR_UNKNOWN,
124 static const struct cpu_dev *this_cpu = &default_cpu;
126 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
129 * We need valid kernel segments for data and code in long mode too
130 * IRET will check the segment types kkeil 2000/10/28
131 * Also sysret mandates a special GDT layout
133 * TLS descriptors are currently at a different place compared to i386.
134 * Hopefully nobody expects them at a fixed place (Wine?)
136 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
137 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
138 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
139 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
140 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
141 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
143 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
144 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
146 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
148 * Segments used for calling PnP BIOS have byte granularity.
149 * They code segments and data segments have fixed 64k limits,
150 * the transfer segment sizes are set at run time.
153 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
155 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
157 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
159 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
161 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
163 * The APM segments have byte granularity and their bases
164 * are set at run time. All have 64k limits.
167 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
169 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
171 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
173 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
174 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
177 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
180 static int __init x86_nopcid_setup(char *s)
182 /* nopcid doesn't accept parameters */
186 /* do not emit a message if the feature is not present */
187 if (!boot_cpu_has(X86_FEATURE_PCID))
190 setup_clear_cpu_cap(X86_FEATURE_PCID);
191 pr_info("nopcid: PCID feature disabled\n");
194 early_param("nopcid", x86_nopcid_setup);
197 static int __init x86_noinvpcid_setup(char *s)
199 /* noinvpcid doesn't accept parameters */
203 /* do not emit a message if the feature is not present */
204 if (!boot_cpu_has(X86_FEATURE_INVPCID))
207 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
208 pr_info("noinvpcid: INVPCID feature disabled\n");
211 early_param("noinvpcid", x86_noinvpcid_setup);
214 static int cachesize_override = -1;
215 static int disable_x86_serial_nr = 1;
217 static int __init cachesize_setup(char *str)
219 get_option(&str, &cachesize_override);
222 __setup("cachesize=", cachesize_setup);
224 static int __init x86_sep_setup(char *s)
226 setup_clear_cpu_cap(X86_FEATURE_SEP);
229 __setup("nosep", x86_sep_setup);
231 /* Standard macro to see if a specific flag is changeable */
232 static inline int flag_is_changeable_p(u32 flag)
237 * Cyrix and IDT cpus allow disabling of CPUID
238 * so the code below may return different results
239 * when it is executed before and after enabling
240 * the CPUID. Add "volatile" to not allow gcc to
241 * optimize the subsequent calls to this function.
243 asm volatile ("pushfl \n\t"
254 : "=&r" (f1), "=&r" (f2)
257 return ((f1^f2) & flag) != 0;
260 /* Probe for the CPUID instruction */
261 int have_cpuid_p(void)
263 return flag_is_changeable_p(X86_EFLAGS_ID);
266 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
268 unsigned long lo, hi;
270 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
273 /* Disable processor serial number: */
275 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
277 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
279 pr_notice("CPU serial number disabled.\n");
280 clear_cpu_cap(c, X86_FEATURE_PN);
282 /* Disabling the serial number may affect the cpuid level */
283 c->cpuid_level = cpuid_eax(0);
286 static int __init x86_serial_nr_setup(char *s)
288 disable_x86_serial_nr = 0;
291 __setup("serialnumber", x86_serial_nr_setup);
293 static inline int flag_is_changeable_p(u32 flag)
297 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
302 static __init int setup_disable_smep(char *arg)
304 setup_clear_cpu_cap(X86_FEATURE_SMEP);
307 __setup("nosmep", setup_disable_smep);
309 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
311 if (cpu_has(c, X86_FEATURE_SMEP))
312 cr4_set_bits(X86_CR4_SMEP);
315 static __init int setup_disable_smap(char *arg)
317 setup_clear_cpu_cap(X86_FEATURE_SMAP);
320 __setup("nosmap", setup_disable_smap);
322 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
324 unsigned long eflags = native_save_fl();
326 /* This should have been cleared long ago */
327 BUG_ON(eflags & X86_EFLAGS_AC);
329 if (cpu_has(c, X86_FEATURE_SMAP)) {
330 #ifdef CONFIG_X86_SMAP
331 cr4_set_bits(X86_CR4_SMAP);
333 clear_cpu_cap(c, X86_FEATURE_SMAP);
334 cr4_clear_bits(X86_CR4_SMAP);
339 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
341 /* Check the boot processor, plus build option for UMIP. */
342 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
345 /* Check the current processor's cpuid bits. */
346 if (!cpu_has(c, X86_FEATURE_UMIP))
349 cr4_set_bits(X86_CR4_UMIP);
351 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
357 * Make sure UMIP is disabled in case it was enabled in a
358 * previous boot (e.g., via kexec).
360 cr4_clear_bits(X86_CR4_UMIP);
363 /* These bits should not change their value after CPU init is finished. */
364 static const unsigned long cr4_pinned_mask =
365 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE;
366 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
367 static unsigned long cr4_pinned_bits __ro_after_init;
369 void native_write_cr0(unsigned long val)
371 unsigned long bits_missing = 0;
374 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
376 if (static_branch_likely(&cr_pinning)) {
377 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
378 bits_missing = X86_CR0_WP;
382 /* Warn after we've set the missing bits. */
383 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
386 EXPORT_SYMBOL(native_write_cr0);
388 void native_write_cr4(unsigned long val)
390 unsigned long bits_changed = 0;
393 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
395 if (static_branch_likely(&cr_pinning)) {
396 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
397 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
398 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
401 /* Warn after we've corrected the changed bits. */
402 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
406 #if IS_MODULE(CONFIG_LKDTM)
407 EXPORT_SYMBOL_GPL(native_write_cr4);
410 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
412 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
414 lockdep_assert_irqs_disabled();
416 newval = (cr4 & ~clear) | set;
418 this_cpu_write(cpu_tlbstate.cr4, newval);
422 EXPORT_SYMBOL(cr4_update_irqsoff);
424 /* Read the CR4 shadow. */
425 unsigned long cr4_read_shadow(void)
427 return this_cpu_read(cpu_tlbstate.cr4);
429 EXPORT_SYMBOL_GPL(cr4_read_shadow);
433 unsigned long cr4 = __read_cr4();
435 if (boot_cpu_has(X86_FEATURE_PCID))
436 cr4 |= X86_CR4_PCIDE;
437 if (static_branch_likely(&cr_pinning))
438 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
442 /* Initialize cr4 shadow for this CPU. */
443 this_cpu_write(cpu_tlbstate.cr4, cr4);
447 * Once CPU feature detection is finished (and boot params have been
448 * parsed), record any of the sensitive CR bits that are set, and
451 static void __init setup_cr_pinning(void)
453 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
454 static_key_enable(&cr_pinning.key);
457 static __init int x86_nofsgsbase_setup(char *arg)
459 /* Require an exact match without trailing characters. */
463 /* Do not emit a message if the feature is not present. */
464 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
467 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
468 pr_info("FSGSBASE disabled via kernel command line\n");
471 __setup("nofsgsbase", x86_nofsgsbase_setup);
474 * Protection Keys are not available in 32-bit mode.
476 static bool pku_disabled;
478 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
480 if (c == &boot_cpu_data) {
481 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
484 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
485 * bit to be set. Enforce it.
487 setup_force_cpu_cap(X86_FEATURE_OSPKE);
489 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
493 cr4_set_bits(X86_CR4_PKE);
494 /* Load the default PKRU value */
495 pkru_write_default();
498 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
499 static __init int setup_disable_pku(char *arg)
502 * Do not clear the X86_FEATURE_PKU bit. All of the
503 * runtime checks are against OSPKE so clearing the
506 * This way, we will see "pku" in cpuinfo, but not
507 * "ospke", which is exactly what we want. It shows
508 * that the CPU has PKU, but the OS has not enabled it.
509 * This happens to be exactly how a system would look
510 * if we disabled the config option.
512 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
516 __setup("nopku", setup_disable_pku);
517 #endif /* CONFIG_X86_64 */
520 * Some CPU features depend on higher CPUID levels, which may not always
521 * be available due to CPUID level capping or broken virtualization
522 * software. Add those features to this table to auto-disable them.
524 struct cpuid_dependent_feature {
529 static const struct cpuid_dependent_feature
530 cpuid_dependent_features[] = {
531 { X86_FEATURE_MWAIT, 0x00000005 },
532 { X86_FEATURE_DCA, 0x00000009 },
533 { X86_FEATURE_XSAVE, 0x0000000d },
537 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
539 const struct cpuid_dependent_feature *df;
541 for (df = cpuid_dependent_features; df->feature; df++) {
543 if (!cpu_has(c, df->feature))
546 * Note: cpuid_level is set to -1 if unavailable, but
547 * extended_extended_level is set to 0 if unavailable
548 * and the legitimate extended levels are all negative
549 * when signed; hence the weird messing around with
552 if (!((s32)df->level < 0 ?
553 (u32)df->level > (u32)c->extended_cpuid_level :
554 (s32)df->level > (s32)c->cpuid_level))
557 clear_cpu_cap(c, df->feature);
561 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
562 x86_cap_flag(df->feature), df->level);
567 * Naming convention should be: <Name> [(<Codename>)]
568 * This table only is used unless init_<vendor>() below doesn't set it;
569 * in particular, if CPUID levels 0x80000002..4 are supported, this
573 /* Look up CPU names by table lookup. */
574 static const char *table_lookup_model(struct cpuinfo_x86 *c)
577 const struct legacy_cpu_model_info *info;
579 if (c->x86_model >= 16)
580 return NULL; /* Range check */
585 info = this_cpu->legacy_models;
587 while (info->family) {
588 if (info->family == c->x86)
589 return info->model_names[c->x86_model];
593 return NULL; /* Not found */
596 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
597 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
598 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
600 void load_percpu_segment(int cpu)
603 loadsegment(fs, __KERNEL_PERCPU);
605 __loadsegment_simple(gs, 0);
606 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
611 /* The 32-bit entry code needs to find cpu_entry_area. */
612 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
615 /* Load the original GDT from the per-cpu structure */
616 void load_direct_gdt(int cpu)
618 struct desc_ptr gdt_descr;
620 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
621 gdt_descr.size = GDT_SIZE - 1;
622 load_gdt(&gdt_descr);
624 EXPORT_SYMBOL_GPL(load_direct_gdt);
626 /* Load a fixmap remapping of the per-cpu GDT */
627 void load_fixmap_gdt(int cpu)
629 struct desc_ptr gdt_descr;
631 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
632 gdt_descr.size = GDT_SIZE - 1;
633 load_gdt(&gdt_descr);
635 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
638 * Current gdt points %fs at the "master" per-cpu area: after this,
639 * it's on the real one.
641 void switch_to_new_gdt(int cpu)
643 /* Load the original GDT */
644 load_direct_gdt(cpu);
645 /* Reload the per-cpu base */
646 load_percpu_segment(cpu);
649 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
651 static void get_model_name(struct cpuinfo_x86 *c)
656 if (c->extended_cpuid_level < 0x80000004)
659 v = (unsigned int *)c->x86_model_id;
660 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
661 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
662 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
663 c->x86_model_id[48] = 0;
665 /* Trim whitespace */
666 p = q = s = &c->x86_model_id[0];
672 /* Note the last non-whitespace index */
682 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
684 unsigned int eax, ebx, ecx, edx;
686 c->x86_max_cores = 1;
687 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
690 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
692 c->x86_max_cores = (eax >> 26) + 1;
695 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
697 unsigned int n, dummy, ebx, ecx, edx, l2size;
699 n = c->extended_cpuid_level;
701 if (n >= 0x80000005) {
702 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
703 c->x86_cache_size = (ecx>>24) + (edx>>24);
705 /* On K8 L1 TLB is inclusive, so don't count it */
710 if (n < 0x80000006) /* Some chips just has a large L1. */
713 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
717 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
719 /* do processor-specific cache resizing */
720 if (this_cpu->legacy_cache_size)
721 l2size = this_cpu->legacy_cache_size(c, l2size);
723 /* Allow user to override all this if necessary. */
724 if (cachesize_override != -1)
725 l2size = cachesize_override;
728 return; /* Again, no L2 cache is possible */
731 c->x86_cache_size = l2size;
734 u16 __read_mostly tlb_lli_4k[NR_INFO];
735 u16 __read_mostly tlb_lli_2m[NR_INFO];
736 u16 __read_mostly tlb_lli_4m[NR_INFO];
737 u16 __read_mostly tlb_lld_4k[NR_INFO];
738 u16 __read_mostly tlb_lld_2m[NR_INFO];
739 u16 __read_mostly tlb_lld_4m[NR_INFO];
740 u16 __read_mostly tlb_lld_1g[NR_INFO];
742 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
744 if (this_cpu->c_detect_tlb)
745 this_cpu->c_detect_tlb(c);
747 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
748 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
749 tlb_lli_4m[ENTRIES]);
751 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
752 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
753 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
756 int detect_ht_early(struct cpuinfo_x86 *c)
759 u32 eax, ebx, ecx, edx;
761 if (!cpu_has(c, X86_FEATURE_HT))
764 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
767 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
770 cpuid(1, &eax, &ebx, &ecx, &edx);
772 smp_num_siblings = (ebx & 0xff0000) >> 16;
773 if (smp_num_siblings == 1)
774 pr_info_once("CPU0: Hyper-Threading is disabled\n");
779 void detect_ht(struct cpuinfo_x86 *c)
782 int index_msb, core_bits;
784 if (detect_ht_early(c) < 0)
787 index_msb = get_count_order(smp_num_siblings);
788 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
790 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
792 index_msb = get_count_order(smp_num_siblings);
794 core_bits = get_count_order(c->x86_max_cores);
796 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
797 ((1 << core_bits) - 1);
801 static void get_cpu_vendor(struct cpuinfo_x86 *c)
803 char *v = c->x86_vendor_id;
806 for (i = 0; i < X86_VENDOR_NUM; i++) {
810 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
811 (cpu_devs[i]->c_ident[1] &&
812 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
814 this_cpu = cpu_devs[i];
815 c->x86_vendor = this_cpu->c_x86_vendor;
820 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
821 "CPU: Your system may be unstable.\n", v);
823 c->x86_vendor = X86_VENDOR_UNKNOWN;
824 this_cpu = &default_cpu;
827 void cpu_detect(struct cpuinfo_x86 *c)
829 /* Get vendor name */
830 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
831 (unsigned int *)&c->x86_vendor_id[0],
832 (unsigned int *)&c->x86_vendor_id[8],
833 (unsigned int *)&c->x86_vendor_id[4]);
836 /* Intel-defined flags: level 0x00000001 */
837 if (c->cpuid_level >= 0x00000001) {
838 u32 junk, tfms, cap0, misc;
840 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
841 c->x86 = x86_family(tfms);
842 c->x86_model = x86_model(tfms);
843 c->x86_stepping = x86_stepping(tfms);
845 if (cap0 & (1<<19)) {
846 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
847 c->x86_cache_alignment = c->x86_clflush_size;
852 static void apply_forced_caps(struct cpuinfo_x86 *c)
856 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
857 c->x86_capability[i] &= ~cpu_caps_cleared[i];
858 c->x86_capability[i] |= cpu_caps_set[i];
862 static void init_speculation_control(struct cpuinfo_x86 *c)
865 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
866 * and they also have a different bit for STIBP support. Also,
867 * a hypervisor might have set the individual AMD bits even on
868 * Intel CPUs, for finer-grained selection of what's available.
870 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
871 set_cpu_cap(c, X86_FEATURE_IBRS);
872 set_cpu_cap(c, X86_FEATURE_IBPB);
873 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
876 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
877 set_cpu_cap(c, X86_FEATURE_STIBP);
879 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
880 cpu_has(c, X86_FEATURE_VIRT_SSBD))
881 set_cpu_cap(c, X86_FEATURE_SSBD);
883 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
884 set_cpu_cap(c, X86_FEATURE_IBRS);
885 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
888 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
889 set_cpu_cap(c, X86_FEATURE_IBPB);
891 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
892 set_cpu_cap(c, X86_FEATURE_STIBP);
893 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
896 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
897 set_cpu_cap(c, X86_FEATURE_SSBD);
898 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
899 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
903 void get_cpu_cap(struct cpuinfo_x86 *c)
905 u32 eax, ebx, ecx, edx;
907 /* Intel-defined flags: level 0x00000001 */
908 if (c->cpuid_level >= 0x00000001) {
909 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
911 c->x86_capability[CPUID_1_ECX] = ecx;
912 c->x86_capability[CPUID_1_EDX] = edx;
915 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
916 if (c->cpuid_level >= 0x00000006)
917 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
919 /* Additional Intel-defined flags: level 0x00000007 */
920 if (c->cpuid_level >= 0x00000007) {
921 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
922 c->x86_capability[CPUID_7_0_EBX] = ebx;
923 c->x86_capability[CPUID_7_ECX] = ecx;
924 c->x86_capability[CPUID_7_EDX] = edx;
926 /* Check valid sub-leaf index before accessing it */
928 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
929 c->x86_capability[CPUID_7_1_EAX] = eax;
933 /* Extended state features: level 0x0000000d */
934 if (c->cpuid_level >= 0x0000000d) {
935 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
937 c->x86_capability[CPUID_D_1_EAX] = eax;
940 /* AMD-defined flags: level 0x80000001 */
941 eax = cpuid_eax(0x80000000);
942 c->extended_cpuid_level = eax;
944 if ((eax & 0xffff0000) == 0x80000000) {
945 if (eax >= 0x80000001) {
946 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
948 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
949 c->x86_capability[CPUID_8000_0001_EDX] = edx;
953 if (c->extended_cpuid_level >= 0x80000007) {
954 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
956 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
960 if (c->extended_cpuid_level >= 0x80000008) {
961 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
962 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
965 if (c->extended_cpuid_level >= 0x8000000a)
966 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
968 if (c->extended_cpuid_level >= 0x8000001f)
969 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
971 if (c->extended_cpuid_level >= 0x80000021)
972 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
974 init_scattered_cpuid_features(c);
975 init_speculation_control(c);
978 * Clear/Set all flags overridden by options, after probe.
979 * This needs to happen each time we re-probe, which may happen
980 * several times during CPU initialization.
982 apply_forced_caps(c);
985 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
987 u32 eax, ebx, ecx, edx;
989 if (c->extended_cpuid_level >= 0x80000008) {
990 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
992 c->x86_virt_bits = (eax >> 8) & 0xff;
993 c->x86_phys_bits = eax & 0xff;
996 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
997 c->x86_phys_bits = 36;
999 c->x86_cache_bits = c->x86_phys_bits;
1002 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1004 #ifdef CONFIG_X86_32
1008 * First of all, decide if this is a 486 or higher
1009 * It's a 486 if we can modify the AC flag
1011 if (flag_is_changeable_p(X86_EFLAGS_AC))
1016 for (i = 0; i < X86_VENDOR_NUM; i++)
1017 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1018 c->x86_vendor_id[0] = 0;
1019 cpu_devs[i]->c_identify(c);
1020 if (c->x86_vendor_id[0]) {
1028 #define NO_SPECULATION BIT(0)
1029 #define NO_MELTDOWN BIT(1)
1030 #define NO_SSB BIT(2)
1031 #define NO_L1TF BIT(3)
1032 #define NO_MDS BIT(4)
1033 #define MSBDS_ONLY BIT(5)
1034 #define NO_SWAPGS BIT(6)
1035 #define NO_ITLB_MULTIHIT BIT(7)
1036 #define NO_SPECTRE_V2 BIT(8)
1037 #define NO_MMIO BIT(9)
1038 #define NO_EIBRS_PBRSB BIT(10)
1040 #define VULNWL(vendor, family, model, whitelist) \
1041 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1043 #define VULNWL_INTEL(model, whitelist) \
1044 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1046 #define VULNWL_AMD(family, whitelist) \
1047 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1049 #define VULNWL_HYGON(family, whitelist) \
1050 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1052 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1053 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1054 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1055 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1056 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1058 /* Intel Family 6 */
1059 VULNWL_INTEL(TIGERLAKE, NO_MMIO),
1060 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
1061 VULNWL_INTEL(ALDERLAKE, NO_MMIO),
1062 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
1064 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1065 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1066 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1067 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1068 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1070 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1071 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1072 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1073 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1074 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1075 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1077 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1079 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1080 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1083 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1084 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1087 * Technically, swapgs isn't serializing on AMD (despite it previously
1088 * being documented as such in the APM). But according to AMD, %gs is
1089 * updated non-speculatively, and the issuing of %gs-relative memory
1090 * operands will be blocked until the %gs update completes, which is
1091 * good enough for our purposes.
1094 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB),
1095 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1096 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1098 /* AMD Family 0xf - 0x12 */
1099 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1100 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1101 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1102 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1104 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1105 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1106 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1108 /* Zhaoxin Family 7 */
1109 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1110 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1114 #define VULNBL(vendor, family, model, blacklist) \
1115 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1117 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1118 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1119 INTEL_FAM6_##model, steppings, \
1120 X86_FEATURE_ANY, issues)
1122 #define VULNBL_AMD(family, blacklist) \
1123 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1125 #define VULNBL_HYGON(family, blacklist) \
1126 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1128 #define SRBDS BIT(0)
1129 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1131 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1132 #define MMIO_SBDS BIT(2)
1133 /* CPU is affected by RETbleed, speculating where you would not expect it */
1134 #define RETBLEED BIT(3)
1135 /* CPU is affected by SMT (cross-thread) return predictions */
1136 #define SMT_RSB BIT(4)
1137 /* CPU is affected by SRSO */
1139 /* CPU is affected by GDS */
1142 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1143 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1144 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1145 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1146 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1147 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1148 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1149 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1150 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1151 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1152 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1153 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1154 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1155 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1156 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1157 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1158 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1159 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1160 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1161 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1162 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1163 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1164 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1165 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS),
1166 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1167 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1168 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1169 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO),
1170 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1172 VULNBL_AMD(0x15, RETBLEED),
1173 VULNBL_AMD(0x16, RETBLEED),
1174 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1175 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
1176 VULNBL_AMD(0x19, SRSO),
1180 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1182 const struct x86_cpu_id *m = x86_match_cpu(table);
1184 return m && !!(m->driver_data & which);
1187 u64 x86_read_arch_cap_msr(void)
1191 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1192 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1197 static bool arch_cap_mmio_immune(u64 ia32_cap)
1199 return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1200 ia32_cap & ARCH_CAP_PSDP_NO &&
1201 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1204 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1206 u64 ia32_cap = x86_read_arch_cap_msr();
1208 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1209 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1210 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1211 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1213 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1216 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1218 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1219 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1221 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1222 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1223 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1224 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1226 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1227 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1229 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1230 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1231 setup_force_cpu_bug(X86_BUG_MDS);
1232 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1233 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1236 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1237 setup_force_cpu_bug(X86_BUG_SWAPGS);
1240 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1241 * - TSX is supported or
1242 * - TSX_CTRL is present
1244 * TSX_CTRL check is needed for cases when TSX could be disabled before
1245 * the kernel boot e.g. kexec.
1246 * TSX_CTRL check alone is not sufficient for cases when the microcode
1247 * update is not present or running as guest that don't get TSX_CTRL.
1249 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1250 (cpu_has(c, X86_FEATURE_RTM) ||
1251 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1252 setup_force_cpu_bug(X86_BUG_TAA);
1255 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1256 * in the vulnerability blacklist.
1258 * Some of the implications and mitigation of Shared Buffers Data
1259 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1262 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1263 cpu_has(c, X86_FEATURE_RDSEED)) &&
1264 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1265 setup_force_cpu_bug(X86_BUG_SRBDS);
1268 * Processor MMIO Stale Data bug enumeration
1270 * Affected CPU list is generally enough to enumerate the vulnerability,
1271 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1272 * not want the guest to enumerate the bug.
1274 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1275 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1277 if (!arch_cap_mmio_immune(ia32_cap)) {
1278 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1279 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1280 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1281 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1284 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1285 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))
1286 setup_force_cpu_bug(X86_BUG_RETBLEED);
1289 if (cpu_has(c, X86_FEATURE_IBRS_ENHANCED) &&
1290 !cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1291 !(ia32_cap & ARCH_CAP_PBRSB_NO))
1292 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1294 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1295 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1298 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1299 * an affected processor, the VMM may have disabled the use of GATHER by
1300 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1301 * which means that AVX will be disabled.
1303 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) &&
1304 boot_cpu_has(X86_FEATURE_AVX))
1305 setup_force_cpu_bug(X86_BUG_GDS);
1307 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1308 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1309 setup_force_cpu_bug(X86_BUG_SRSO);
1312 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1315 /* Rogue Data Cache Load? No! */
1316 if (ia32_cap & ARCH_CAP_RDCL_NO)
1319 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1321 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1324 setup_force_cpu_bug(X86_BUG_L1TF);
1328 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1329 * unfortunately, that's not true in practice because of early VIA
1330 * chips and (more importantly) broken virtualizers that are not easy
1331 * to detect. In the latter case it doesn't even *fail* reliably, so
1332 * probing for it doesn't even work. Disable it completely on 32-bit
1333 * unless we can find a reliable way to detect all the broken cases.
1334 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1336 static void detect_nopl(void)
1338 #ifdef CONFIG_X86_32
1339 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1341 setup_force_cpu_cap(X86_FEATURE_NOPL);
1346 * We parse cpu parameters early because fpu__init_system() is executed
1347 * before parse_early_param().
1349 static void __init cpu_parse_early_param(void)
1353 int arglen, res, bit;
1355 #ifdef CONFIG_X86_32
1356 if (cmdline_find_option_bool(boot_command_line, "no387"))
1357 #ifdef CONFIG_MATH_EMULATION
1358 setup_clear_cpu_cap(X86_FEATURE_FPU);
1360 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1363 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1364 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1367 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1368 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1370 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1371 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1373 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1374 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1376 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1380 pr_info("Clearing CPUID bits:");
1382 res = get_option(&argptr, &bit);
1383 if (res == 0 || res == 3)
1386 /* If the argument was too long, the last bit may be cut off */
1387 if (res == 1 && arglen >= sizeof(arg))
1390 if (bit >= 0 && bit < NCAPINTS * 32) {
1391 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1392 setup_clear_cpu_cap(bit);
1399 * Do minimum CPU detection early.
1400 * Fields really needed: vendor, cpuid_level, family, model, mask,
1402 * The others are not touched to avoid unwanted side effects.
1404 * WARNING: this function is only called on the boot CPU. Don't add code
1405 * here that is supposed to run on all CPUs.
1407 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1409 #ifdef CONFIG_X86_64
1410 c->x86_clflush_size = 64;
1411 c->x86_phys_bits = 36;
1412 c->x86_virt_bits = 48;
1414 c->x86_clflush_size = 32;
1415 c->x86_phys_bits = 32;
1416 c->x86_virt_bits = 32;
1418 c->x86_cache_alignment = c->x86_clflush_size;
1420 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1421 c->extended_cpuid_level = 0;
1423 if (!have_cpuid_p())
1424 identify_cpu_without_cpuid(c);
1426 /* cyrix could have cpuid enabled via c_identify()*/
1427 if (have_cpuid_p()) {
1431 get_cpu_address_sizes(c);
1432 setup_force_cpu_cap(X86_FEATURE_CPUID);
1433 cpu_parse_early_param();
1435 if (this_cpu->c_early_init)
1436 this_cpu->c_early_init(c);
1439 filter_cpuid_features(c, false);
1441 if (this_cpu->c_bsp_init)
1442 this_cpu->c_bsp_init(c);
1444 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1447 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1449 cpu_set_bug_bits(c);
1453 #ifdef CONFIG_X86_32
1455 * Regardless of whether PCID is enumerated, the SDM says
1456 * that it can't be enabled in 32-bit mode.
1458 setup_clear_cpu_cap(X86_FEATURE_PCID);
1462 * Later in the boot process pgtable_l5_enabled() relies on
1463 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1464 * enabled by this point we need to clear the feature bit to avoid
1465 * false-positives at the later stage.
1467 * pgtable_l5_enabled() can be false here for several reasons:
1468 * - 5-level paging is disabled compile-time;
1469 * - it's 32-bit kernel;
1470 * - machine doesn't support 5-level paging;
1471 * - user specified 'no5lvl' in kernel command line.
1473 if (!pgtable_l5_enabled())
1474 setup_clear_cpu_cap(X86_FEATURE_LA57);
1479 void __init early_cpu_init(void)
1481 const struct cpu_dev *const *cdev;
1484 #ifdef CONFIG_PROCESSOR_SELECT
1485 pr_info("KERNEL supported cpus:\n");
1488 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1489 const struct cpu_dev *cpudev = *cdev;
1491 if (count >= X86_VENDOR_NUM)
1493 cpu_devs[count] = cpudev;
1496 #ifdef CONFIG_PROCESSOR_SELECT
1500 for (j = 0; j < 2; j++) {
1501 if (!cpudev->c_ident[j])
1503 pr_info(" %s %s\n", cpudev->c_vendor,
1504 cpudev->c_ident[j]);
1509 early_identify_cpu(&boot_cpu_data);
1512 static bool detect_null_seg_behavior(void)
1515 * Empirically, writing zero to a segment selector on AMD does
1516 * not clear the base, whereas writing zero to a segment
1517 * selector on Intel does clear the base. Intel's behavior
1518 * allows slightly faster context switches in the common case
1519 * where GS is unused by the prev and next threads.
1521 * Since neither vendor documents this anywhere that I can see,
1522 * detect it directly instead of hard-coding the choice by
1525 * I've designated AMD's behavior as the "bug" because it's
1526 * counterintuitive and less friendly.
1529 unsigned long old_base, tmp;
1530 rdmsrl(MSR_FS_BASE, old_base);
1531 wrmsrl(MSR_FS_BASE, 1);
1533 rdmsrl(MSR_FS_BASE, tmp);
1534 wrmsrl(MSR_FS_BASE, old_base);
1538 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1540 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1541 if (!IS_ENABLED(CONFIG_X86_64))
1544 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */
1545 if (c->extended_cpuid_level >= 0x80000021 &&
1546 cpuid_eax(0x80000021) & BIT(6))
1550 * CPUID bit above wasn't set. If this kernel is still running
1551 * as a HV guest, then the HV has decided not to advertize
1552 * that CPUID bit for whatever reason. For example, one
1553 * member of the migration pool might be vulnerable. Which
1554 * means, the bug is present: set the BUG flag and return.
1556 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1557 set_cpu_bug(c, X86_BUG_NULL_SEG);
1562 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1563 * 0x18 is the respective family for Hygon.
1565 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1566 detect_null_seg_behavior())
1569 /* All the remaining ones are affected */
1570 set_cpu_bug(c, X86_BUG_NULL_SEG);
1573 static void generic_identify(struct cpuinfo_x86 *c)
1575 c->extended_cpuid_level = 0;
1577 if (!have_cpuid_p())
1578 identify_cpu_without_cpuid(c);
1580 /* cyrix could have cpuid enabled via c_identify()*/
1581 if (!have_cpuid_p())
1590 get_cpu_address_sizes(c);
1592 if (c->cpuid_level >= 0x00000001) {
1593 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1594 #ifdef CONFIG_X86_32
1596 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1598 c->apicid = c->initial_apicid;
1601 c->phys_proc_id = c->initial_apicid;
1604 get_model_name(c); /* Default name */
1607 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1608 * systems that run Linux at CPL > 0 may or may not have the
1609 * issue, but, even if they have the issue, there's absolutely
1610 * nothing we can do about it because we can't use the real IRET
1613 * NB: For the time being, only 32-bit kernels support
1614 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1615 * whether to apply espfix using paravirt hooks. If any
1616 * non-paravirt system ever shows up that does *not* have the
1617 * ESPFIX issue, we can change this.
1619 #ifdef CONFIG_X86_32
1620 set_cpu_bug(c, X86_BUG_ESPFIX);
1625 * Validate that ACPI/mptables have the same information about the
1626 * effective APIC id and update the package map.
1628 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1631 unsigned int apicid, cpu = smp_processor_id();
1633 apicid = apic->cpu_present_to_apicid(cpu);
1635 if (apicid != c->apicid) {
1636 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1637 cpu, apicid, c->initial_apicid);
1639 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1640 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1642 c->logical_proc_id = 0;
1647 * This does the hard work of actually picking apart the CPU stuff...
1649 static void identify_cpu(struct cpuinfo_x86 *c)
1653 c->loops_per_jiffy = loops_per_jiffy;
1654 c->x86_cache_size = 0;
1655 c->x86_vendor = X86_VENDOR_UNKNOWN;
1656 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1657 c->x86_vendor_id[0] = '\0'; /* Unset */
1658 c->x86_model_id[0] = '\0'; /* Unset */
1659 c->x86_max_cores = 1;
1660 c->x86_coreid_bits = 0;
1662 #ifdef CONFIG_X86_64
1663 c->x86_clflush_size = 64;
1664 c->x86_phys_bits = 36;
1665 c->x86_virt_bits = 48;
1667 c->cpuid_level = -1; /* CPUID not detected */
1668 c->x86_clflush_size = 32;
1669 c->x86_phys_bits = 32;
1670 c->x86_virt_bits = 32;
1672 c->x86_cache_alignment = c->x86_clflush_size;
1673 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1674 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1675 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1678 generic_identify(c);
1680 if (this_cpu->c_identify)
1681 this_cpu->c_identify(c);
1683 /* Clear/Set all flags overridden by options, after probe */
1684 apply_forced_caps(c);
1686 #ifdef CONFIG_X86_64
1687 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1691 * Vendor-specific initialization. In this section we
1692 * canonicalize the feature flags, meaning if there are
1693 * features a certain CPU supports which CPUID doesn't
1694 * tell us, CPUID claiming incorrect flags, or other bugs,
1695 * we handle them here.
1697 * At the end of this section, c->x86_capability better
1698 * indicate the features this CPU genuinely supports!
1700 if (this_cpu->c_init)
1701 this_cpu->c_init(c);
1703 /* Disable the PN if appropriate */
1704 squash_the_stupid_serial_number(c);
1706 /* Set up SMEP/SMAP/UMIP */
1711 /* Enable FSGSBASE instructions if available. */
1712 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1713 cr4_set_bits(X86_CR4_FSGSBASE);
1714 elf_hwcap2 |= HWCAP2_FSGSBASE;
1718 * The vendor-specific functions might have changed features.
1719 * Now we do "generic changes."
1722 /* Filter out anything that depends on CPUID levels we don't have */
1723 filter_cpuid_features(c, true);
1725 /* If the model name is still unset, do table lookup. */
1726 if (!c->x86_model_id[0]) {
1728 p = table_lookup_model(c);
1730 strcpy(c->x86_model_id, p);
1732 /* Last resort... */
1733 sprintf(c->x86_model_id, "%02x/%02x",
1734 c->x86, c->x86_model);
1737 #ifdef CONFIG_X86_64
1745 * Clear/Set all flags overridden by options, need do it
1746 * before following smp all cpus cap AND.
1748 apply_forced_caps(c);
1751 * On SMP, boot_cpu_data holds the common feature set between
1752 * all CPUs; so make sure that we indicate which features are
1753 * common between the CPUs. The first time this routine gets
1754 * executed, c == &boot_cpu_data.
1756 if (c != &boot_cpu_data) {
1757 /* AND the already accumulated flags with these */
1758 for (i = 0; i < NCAPINTS; i++)
1759 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1761 /* OR, i.e. replicate the bug flags */
1762 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1763 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1766 /* Init Machine Check Exception if available. */
1769 select_idle_routine(c);
1772 numa_add_cpu(smp_processor_id());
1777 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1778 * on 32-bit kernels:
1780 #ifdef CONFIG_X86_32
1781 void enable_sep_cpu(void)
1783 struct tss_struct *tss;
1786 if (!boot_cpu_has(X86_FEATURE_SEP))
1790 tss = &per_cpu(cpu_tss_rw, cpu);
1793 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1794 * see the big comment in struct x86_hw_tss's definition.
1797 tss->x86_tss.ss1 = __KERNEL_CS;
1798 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1799 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1800 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1806 void __init identify_boot_cpu(void)
1808 identify_cpu(&boot_cpu_data);
1809 #ifdef CONFIG_X86_32
1813 cpu_detect_tlb(&boot_cpu_data);
1819 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1821 BUG_ON(c == &boot_cpu_data);
1823 #ifdef CONFIG_X86_32
1827 validate_apic_and_package_id(c);
1828 x86_spec_ctrl_setup_ap();
1830 if (boot_cpu_has_bug(X86_BUG_GDS))
1836 static __init int setup_noclflush(char *arg)
1838 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1839 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1842 __setup("noclflush", setup_noclflush);
1844 void print_cpu_info(struct cpuinfo_x86 *c)
1846 const char *vendor = NULL;
1848 if (c->x86_vendor < X86_VENDOR_NUM) {
1849 vendor = this_cpu->c_vendor;
1851 if (c->cpuid_level >= 0)
1852 vendor = c->x86_vendor_id;
1855 if (vendor && !strstr(c->x86_model_id, vendor))
1856 pr_cont("%s ", vendor);
1858 if (c->x86_model_id[0])
1859 pr_cont("%s", c->x86_model_id);
1861 pr_cont("%d86", c->x86);
1863 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1865 if (c->x86_stepping || c->cpuid_level >= 0)
1866 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1872 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
1873 * function prevents it from becoming an environment variable for init.
1875 static __init int setup_clearcpuid(char *arg)
1879 __setup("clearcpuid=", setup_clearcpuid);
1881 #ifdef CONFIG_X86_64
1882 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1883 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1884 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1887 * The following percpu variables are hot. Align current_task to
1888 * cacheline size such that they fall in the same cacheline.
1890 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1892 EXPORT_PER_CPU_SYMBOL(current_task);
1894 DEFINE_PER_CPU(void *, hardirq_stack_ptr);
1895 DEFINE_PER_CPU(bool, hardirq_stack_inuse);
1897 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1898 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1900 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK;
1902 /* May not be marked __init: used by software suspend */
1903 void syscall_init(void)
1905 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1906 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1908 #ifdef CONFIG_IA32_EMULATION
1909 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1911 * This only works on Intel CPUs.
1912 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1913 * This does not cause SYSENTER to jump to the wrong location, because
1914 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1916 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1917 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1918 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1919 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1921 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1922 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1923 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1924 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1928 * Flags to clear on syscall; clear as much as possible
1929 * to minimize user space-kernel interference.
1931 wrmsrl(MSR_SYSCALL_MASK,
1932 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
1933 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
1934 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
1935 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
1936 X86_EFLAGS_AC|X86_EFLAGS_ID);
1939 #else /* CONFIG_X86_64 */
1941 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1942 EXPORT_PER_CPU_SYMBOL(current_task);
1943 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1944 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1947 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1948 * the top of the kernel stack. Use an extra percpu variable to track the
1949 * top of the kernel stack directly.
1951 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1952 (unsigned long)&init_thread_union + THREAD_SIZE;
1953 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1955 #ifdef CONFIG_STACKPROTECTOR
1956 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
1957 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
1960 #endif /* CONFIG_X86_64 */
1963 * Clear all 6 debug registers:
1965 static void clear_all_debug_regs(void)
1969 for (i = 0; i < 8; i++) {
1970 /* Ignore db4, db5 */
1971 if ((i == 4) || (i == 5))
1980 * Restore debug regs if using kgdbwait and you have a kernel debugger
1981 * connection established.
1983 static void dbg_restore_debug_regs(void)
1985 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1986 arch_kgdb_ops.correct_hw_break();
1988 #else /* ! CONFIG_KGDB */
1989 #define dbg_restore_debug_regs()
1990 #endif /* ! CONFIG_KGDB */
1992 static void wait_for_master_cpu(int cpu)
1996 * wait for ACK from master CPU before continuing
1997 * with AP initialization
1999 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
2000 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
2005 #ifdef CONFIG_X86_64
2006 static inline void setup_getcpu(int cpu)
2008 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2009 struct desc_struct d = { };
2011 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2012 wrmsr(MSR_TSC_AUX, cpudata, 0);
2014 /* Store CPU and node number in limit. */
2016 d.limit1 = cpudata >> 16;
2018 d.type = 5; /* RO data, expand down, accessed */
2019 d.dpl = 3; /* Visible to user code */
2020 d.s = 1; /* Not a system segment */
2021 d.p = 1; /* Present */
2022 d.d = 1; /* 32-bit */
2024 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2027 static inline void ucode_cpu_init(int cpu)
2033 static inline void tss_setup_ist(struct tss_struct *tss)
2035 /* Set up the per-CPU TSS IST stacks */
2036 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2037 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2038 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2039 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2040 /* Only mapped when SEV-ES is active */
2041 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2044 #else /* CONFIG_X86_64 */
2046 static inline void setup_getcpu(int cpu) { }
2048 static inline void ucode_cpu_init(int cpu)
2050 show_ucode_info_early();
2053 static inline void tss_setup_ist(struct tss_struct *tss) { }
2055 #endif /* !CONFIG_X86_64 */
2057 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2059 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2061 #ifdef CONFIG_X86_IOPL_IOPERM
2062 tss->io_bitmap.prev_max = 0;
2063 tss->io_bitmap.prev_sequence = 0;
2064 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2066 * Invalidate the extra array entry past the end of the all
2067 * permission bitmap as required by the hardware.
2069 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2074 * Setup everything needed to handle exceptions from the IDT, including the IST
2075 * exceptions which use paranoid_entry().
2077 void cpu_init_exception_handling(void)
2079 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2080 int cpu = raw_smp_processor_id();
2082 /* paranoid_entry() gets the CPU number from the GDT */
2085 /* IST vectors need TSS to be set up. */
2087 tss_setup_io_bitmap(tss);
2088 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2092 /* Finally load the IDT */
2097 * cpu_init() initializes state that is per-CPU. Some data is already
2098 * initialized (naturally) in the bootstrap process, such as the GDT. We
2099 * reload it nevertheless, this function acts as a 'CPU state barrier',
2100 * nothing should get across.
2104 struct task_struct *cur = current;
2105 int cpu = raw_smp_processor_id();
2107 wait_for_master_cpu(cpu);
2109 ucode_cpu_init(cpu);
2112 if (this_cpu_read(numa_node) == 0 &&
2113 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2114 set_numa_node(early_cpu_to_node(cpu));
2116 pr_debug("Initializing CPU#%d\n", cpu);
2118 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2119 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2120 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2123 * Initialize the per-CPU GDT with the boot GDT,
2124 * and set up the GDT descriptor:
2126 switch_to_new_gdt(cpu);
2128 if (IS_ENABLED(CONFIG_X86_64)) {
2130 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2133 wrmsrl(MSR_FS_BASE, 0);
2134 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2141 cur->active_mm = &init_mm;
2143 initialize_tlbstate_and_flush();
2144 enter_lazy_tlb(&init_mm, cur);
2147 * sp0 points to the entry trampoline stack regardless of what task
2150 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2152 load_mm_ldt(&init_mm);
2154 clear_all_debug_regs();
2155 dbg_restore_debug_regs();
2157 doublefault_init_cpu_tss();
2162 load_fixmap_gdt(cpu);
2166 void cpu_init_secondary(void)
2169 * Relies on the BP having set-up the IDT tables, which are loaded
2170 * on this CPU in cpu_init_exception_handling().
2172 cpu_init_exception_handling();
2178 #ifdef CONFIG_MICROCODE_LATE_LOADING
2180 * store_cpu_caps() - Store a snapshot of CPU capabilities
2181 * @curr_info: Pointer where to store it
2185 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2187 /* Reload CPUID max function as it might've changed. */
2188 curr_info->cpuid_level = cpuid_eax(0);
2190 /* Copy all capability leafs and pick up the synthetic ones. */
2191 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2192 sizeof(curr_info->x86_capability));
2194 /* Get the hardware CPUID leafs */
2195 get_cpu_cap(curr_info);
2199 * microcode_check() - Check if any CPU capabilities changed after an update.
2200 * @prev_info: CPU capabilities stored before an update.
2202 * The microcode loader calls this upon late microcode load to recheck features,
2203 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2208 void microcode_check(struct cpuinfo_x86 *prev_info)
2210 struct cpuinfo_x86 curr_info;
2212 perf_check_microcode();
2214 amd_check_microcode();
2216 store_cpu_caps(&curr_info);
2218 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2219 sizeof(prev_info->x86_capability)))
2222 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2223 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2228 * Invoked from core CPU hotplug code after hotplug operations
2230 void arch_smt_update(void)
2232 /* Handle the speculative execution misfeatures */
2233 cpu_bugs_smt_update();
2234 /* Check whether IPI broadcasting can be enabled */
2238 void __init arch_cpu_finalize_init(void)
2240 identify_boot_cpu();
2243 * identify_boot_cpu() initialized SMT support information, let the
2246 cpu_smt_check_topology();
2248 if (!IS_ENABLED(CONFIG_SMP)) {
2250 print_cpu_info(&boot_cpu_data);
2253 cpu_select_mitigations();
2257 if (IS_ENABLED(CONFIG_X86_32)) {
2259 * Check whether this is a real i386 which is not longer
2260 * supported and fixup the utsname.
2262 if (boot_cpu_data.x86 < 4)
2263 panic("Kernel requires i486+ for 'invlpg' and other features");
2265 init_utsname()->machine[1] =
2266 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2270 * Must be before alternatives because it might set or clear
2276 alternative_instructions();
2278 if (IS_ENABLED(CONFIG_X86_64)) {
2280 * Make sure the first 2MB area is not mapped by huge pages
2281 * There are typically fixed size MTRRs in there and overlapping
2282 * MTRRs into large pages causes slow downs.
2284 * Right now we don't do that with gbpages because there seems
2285 * very little benefit for that case.
2287 if (!direct_gbpages)
2288 set_memory_4k((unsigned long)__va(0), 1);
2290 fpu__init_check_bugs();
2294 * This needs to be called before any devices perform DMA
2295 * operations that might use the SWIOTLB bounce buffers. It will
2296 * mark the bounce buffers as decrypted so that their usage will
2297 * not cause "plain-text" data to be decrypted when accessed. It
2298 * must be called after late_time_init() so that Hyper-V x86/x64
2299 * hypercalls work when the SWIOTLB bounce buffers are decrypted.