1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
34 #include <linux/bpf.h>
38 static void __init spectre_v1_select_mitigation(void);
39 static void __init spectre_v2_select_mitigation(void);
40 static void __init ssb_select_mitigation(void);
41 static void __init l1tf_select_mitigation(void);
42 static void __init mds_select_mitigation(void);
43 static void __init mds_print_mitigation(void);
44 static void __init taa_select_mitigation(void);
45 static void __init srbds_select_mitigation(void);
47 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
48 u64 x86_spec_ctrl_base;
49 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
50 static DEFINE_MUTEX(spec_ctrl_mutex);
53 * The vendor and possibly platform specific bits which can be modified in
56 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
59 * AMD specific MSR info for Speculative Store Bypass control.
60 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
62 u64 __ro_after_init x86_amd_ls_cfg_base;
63 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
65 /* Control conditional STIBP in switch_to() */
66 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
67 /* Control conditional IBPB in switch_mm() */
68 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
69 /* Control unconditional IBPB in switch_mm() */
70 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
72 /* Control MDS CPU buffer clear before returning to user space */
73 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
74 EXPORT_SYMBOL_GPL(mds_user_clear);
75 /* Control MDS CPU buffer clear before idling (halt, mwait) */
76 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
77 EXPORT_SYMBOL_GPL(mds_idle_clear);
79 void __init check_bugs(void)
84 * identify_boot_cpu() initialized SMT support information, let the
87 cpu_smt_check_topology();
89 if (!IS_ENABLED(CONFIG_SMP)) {
91 print_cpu_info(&boot_cpu_data);
95 * Read the SPEC_CTRL MSR to account for reserved bits which may
96 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
97 * init code as it is not enumerated and depends on the family.
99 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
100 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
102 /* Allow STIBP in MSR_SPEC_CTRL if supported */
103 if (boot_cpu_has(X86_FEATURE_STIBP))
104 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
106 /* Select the proper CPU mitigations before patching alternatives: */
107 spectre_v1_select_mitigation();
108 spectre_v2_select_mitigation();
109 ssb_select_mitigation();
110 l1tf_select_mitigation();
111 mds_select_mitigation();
112 taa_select_mitigation();
113 srbds_select_mitigation();
116 * As MDS and TAA mitigations are inter-related, print MDS
117 * mitigation until after TAA mitigation selection is done.
119 mds_print_mitigation();
125 * Check whether we are able to run this kernel safely on SMP.
127 * - i386 is no longer supported.
128 * - In order to run on anything without a TSC, we need to be
129 * compiled for a i486.
131 if (boot_cpu_data.x86 < 4)
132 panic("Kernel requires i486+ for 'invlpg' and other features");
134 init_utsname()->machine[1] =
135 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
136 alternative_instructions();
138 fpu__init_check_bugs();
139 #else /* CONFIG_X86_64 */
140 alternative_instructions();
143 * Make sure the first 2MB area is not mapped by huge pages
144 * There are typically fixed size MTRRs in there and overlapping
145 * MTRRs into large pages causes slow downs.
147 * Right now we don't do that with gbpages because there seems
148 * very little benefit for that case.
151 set_memory_4k((unsigned long)__va(0), 1);
156 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
158 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
159 struct thread_info *ti = current_thread_info();
161 /* Is MSR_SPEC_CTRL implemented ? */
162 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
164 * Restrict guest_spec_ctrl to supported values. Clear the
165 * modifiable bits in the host base value and or the
166 * modifiable bits from the guest value.
168 guestval = hostval & ~x86_spec_ctrl_mask;
169 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
171 /* SSBD controlled in MSR_SPEC_CTRL */
172 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
173 static_cpu_has(X86_FEATURE_AMD_SSBD))
174 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
176 /* Conditional STIBP enabled? */
177 if (static_branch_unlikely(&switch_to_cond_stibp))
178 hostval |= stibp_tif_to_spec_ctrl(ti->flags);
180 if (hostval != guestval) {
181 msrval = setguest ? guestval : hostval;
182 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
187 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
188 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
190 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
191 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
195 * If the host has SSBD mitigation enabled, force it in the host's
196 * virtual MSR value. If its not permanently enabled, evaluate
197 * current's TIF_SSBD thread flag.
199 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
200 hostval = SPEC_CTRL_SSBD;
202 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
204 /* Sanitize the guest value */
205 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
207 if (hostval != guestval) {
210 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
211 ssbd_spec_ctrl_to_tif(hostval);
213 speculation_ctrl_update(tif);
216 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
218 static void x86_amd_ssb_disable(void)
220 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
222 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
223 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
224 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
225 wrmsrl(MSR_AMD64_LS_CFG, msrval);
229 #define pr_fmt(fmt) "MDS: " fmt
231 /* Default mitigation for MDS-affected CPUs */
232 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
233 static bool mds_nosmt __ro_after_init = false;
235 static const char * const mds_strings[] = {
236 [MDS_MITIGATION_OFF] = "Vulnerable",
237 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
238 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
241 static void __init mds_select_mitigation(void)
243 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
244 mds_mitigation = MDS_MITIGATION_OFF;
248 if (mds_mitigation == MDS_MITIGATION_FULL) {
249 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
250 mds_mitigation = MDS_MITIGATION_VMWERV;
252 static_branch_enable(&mds_user_clear);
254 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
255 (mds_nosmt || cpu_mitigations_auto_nosmt()))
256 cpu_smt_disable(false);
260 static void __init mds_print_mitigation(void)
262 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
265 pr_info("%s\n", mds_strings[mds_mitigation]);
268 static int __init mds_cmdline(char *str)
270 if (!boot_cpu_has_bug(X86_BUG_MDS))
276 if (!strcmp(str, "off"))
277 mds_mitigation = MDS_MITIGATION_OFF;
278 else if (!strcmp(str, "full"))
279 mds_mitigation = MDS_MITIGATION_FULL;
280 else if (!strcmp(str, "full,nosmt")) {
281 mds_mitigation = MDS_MITIGATION_FULL;
287 early_param("mds", mds_cmdline);
290 #define pr_fmt(fmt) "TAA: " fmt
292 /* Default mitigation for TAA-affected CPUs */
293 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
294 static bool taa_nosmt __ro_after_init;
296 static const char * const taa_strings[] = {
297 [TAA_MITIGATION_OFF] = "Vulnerable",
298 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
299 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
300 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
303 static void __init taa_select_mitigation(void)
307 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
308 taa_mitigation = TAA_MITIGATION_OFF;
312 /* TSX previously disabled by tsx=off */
313 if (!boot_cpu_has(X86_FEATURE_RTM)) {
314 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
318 if (cpu_mitigations_off()) {
319 taa_mitigation = TAA_MITIGATION_OFF;
324 * TAA mitigation via VERW is turned off if both
325 * tsx_async_abort=off and mds=off are specified.
327 if (taa_mitigation == TAA_MITIGATION_OFF &&
328 mds_mitigation == MDS_MITIGATION_OFF)
331 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
332 taa_mitigation = TAA_MITIGATION_VERW;
334 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
337 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
338 * A microcode update fixes this behavior to clear CPU buffers. It also
339 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
340 * ARCH_CAP_TSX_CTRL_MSR bit.
342 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
343 * update is required.
345 ia32_cap = x86_read_arch_cap_msr();
346 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
347 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
348 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
351 * TSX is enabled, select alternate mitigation for TAA which is
352 * the same as MDS. Enable MDS static branch to clear CPU buffers.
354 * For guests that can't determine whether the correct microcode is
355 * present on host, enable the mitigation for UCODE_NEEDED as well.
357 static_branch_enable(&mds_user_clear);
359 if (taa_nosmt || cpu_mitigations_auto_nosmt())
360 cpu_smt_disable(false);
363 * Update MDS mitigation, if necessary, as the mds_user_clear is
364 * now enabled for TAA mitigation.
366 if (mds_mitigation == MDS_MITIGATION_OFF &&
367 boot_cpu_has_bug(X86_BUG_MDS)) {
368 mds_mitigation = MDS_MITIGATION_FULL;
369 mds_select_mitigation();
372 pr_info("%s\n", taa_strings[taa_mitigation]);
375 static int __init tsx_async_abort_parse_cmdline(char *str)
377 if (!boot_cpu_has_bug(X86_BUG_TAA))
383 if (!strcmp(str, "off")) {
384 taa_mitigation = TAA_MITIGATION_OFF;
385 } else if (!strcmp(str, "full")) {
386 taa_mitigation = TAA_MITIGATION_VERW;
387 } else if (!strcmp(str, "full,nosmt")) {
388 taa_mitigation = TAA_MITIGATION_VERW;
394 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
397 #define pr_fmt(fmt) "SRBDS: " fmt
399 enum srbds_mitigations {
400 SRBDS_MITIGATION_OFF,
401 SRBDS_MITIGATION_UCODE_NEEDED,
402 SRBDS_MITIGATION_FULL,
403 SRBDS_MITIGATION_TSX_OFF,
404 SRBDS_MITIGATION_HYPERVISOR,
407 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
409 static const char * const srbds_strings[] = {
410 [SRBDS_MITIGATION_OFF] = "Vulnerable",
411 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
412 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
413 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
414 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
417 static bool srbds_off;
419 void update_srbds_msr(void)
423 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
426 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
429 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
432 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
434 switch (srbds_mitigation) {
435 case SRBDS_MITIGATION_OFF:
436 case SRBDS_MITIGATION_TSX_OFF:
437 mcu_ctrl |= RNGDS_MITG_DIS;
439 case SRBDS_MITIGATION_FULL:
440 mcu_ctrl &= ~RNGDS_MITG_DIS;
446 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
449 static void __init srbds_select_mitigation(void)
453 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
457 * Check to see if this is one of the MDS_NO systems supporting
458 * TSX that are only exposed to SRBDS when TSX is enabled.
460 ia32_cap = x86_read_arch_cap_msr();
461 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
462 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
463 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
464 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
465 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
466 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
467 else if (cpu_mitigations_off() || srbds_off)
468 srbds_mitigation = SRBDS_MITIGATION_OFF;
471 pr_info("%s\n", srbds_strings[srbds_mitigation]);
474 static int __init srbds_parse_cmdline(char *str)
479 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
482 srbds_off = !strcmp(str, "off");
485 early_param("srbds", srbds_parse_cmdline);
488 #define pr_fmt(fmt) "Spectre V1 : " fmt
490 enum spectre_v1_mitigation {
491 SPECTRE_V1_MITIGATION_NONE,
492 SPECTRE_V1_MITIGATION_AUTO,
495 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
496 SPECTRE_V1_MITIGATION_AUTO;
498 static const char * const spectre_v1_strings[] = {
499 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
500 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
504 * Does SMAP provide full mitigation against speculative kernel access to
507 static bool smap_works_speculatively(void)
509 if (!boot_cpu_has(X86_FEATURE_SMAP))
513 * On CPUs which are vulnerable to Meltdown, SMAP does not
514 * prevent speculative access to user data in the L1 cache.
515 * Consider SMAP to be non-functional as a mitigation on these
518 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
524 static void __init spectre_v1_select_mitigation(void)
526 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
527 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
531 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
533 * With Spectre v1, a user can speculatively control either
534 * path of a conditional swapgs with a user-controlled GS
535 * value. The mitigation is to add lfences to both code paths.
537 * If FSGSBASE is enabled, the user can put a kernel address in
538 * GS, in which case SMAP provides no protection.
540 * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
541 * FSGSBASE enablement patches have been merged. ]
543 * If FSGSBASE is disabled, the user can only put a user space
544 * address in GS. That makes an attack harder, but still
545 * possible if there's no SMAP protection.
547 if (!smap_works_speculatively()) {
549 * Mitigation can be provided from SWAPGS itself or
550 * PTI as the CR3 write in the Meltdown mitigation
553 * If neither is there, mitigate with an LFENCE to
554 * stop speculation through swapgs.
556 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
557 !boot_cpu_has(X86_FEATURE_PTI))
558 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
561 * Enable lfences in the kernel entry (non-swapgs)
562 * paths, to prevent user entry from speculatively
565 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
569 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
572 static int __init nospectre_v1_cmdline(char *str)
574 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
577 early_param("nospectre_v1", nospectre_v1_cmdline);
580 #define pr_fmt(fmt) "Spectre V2 : " fmt
582 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
585 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
586 SPECTRE_V2_USER_NONE;
587 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
588 SPECTRE_V2_USER_NONE;
590 #ifdef CONFIG_RETPOLINE
591 static bool spectre_v2_bad_module;
593 bool retpoline_module_ok(bool has_retpoline)
595 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
598 pr_err("System may be vulnerable to spectre v2\n");
599 spectre_v2_bad_module = true;
603 static inline const char *spectre_v2_module_string(void)
605 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
608 static inline const char *spectre_v2_module_string(void) { return ""; }
611 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
612 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
613 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
615 #ifdef CONFIG_BPF_SYSCALL
616 void unpriv_ebpf_notify(int new_state)
621 /* Unprivileged eBPF is enabled */
623 switch (spectre_v2_enabled) {
624 case SPECTRE_V2_EIBRS:
625 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
627 case SPECTRE_V2_EIBRS_LFENCE:
628 if (sched_smt_active())
629 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
637 static inline bool match_option(const char *arg, int arglen, const char *opt)
639 int len = strlen(opt);
641 return len == arglen && !strncmp(arg, opt, len);
644 /* The kernel command line selection for spectre v2 */
645 enum spectre_v2_mitigation_cmd {
648 SPECTRE_V2_CMD_FORCE,
649 SPECTRE_V2_CMD_RETPOLINE,
650 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
651 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
652 SPECTRE_V2_CMD_EIBRS,
653 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
654 SPECTRE_V2_CMD_EIBRS_LFENCE,
657 enum spectre_v2_user_cmd {
658 SPECTRE_V2_USER_CMD_NONE,
659 SPECTRE_V2_USER_CMD_AUTO,
660 SPECTRE_V2_USER_CMD_FORCE,
661 SPECTRE_V2_USER_CMD_PRCTL,
662 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
663 SPECTRE_V2_USER_CMD_SECCOMP,
664 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
667 static const char * const spectre_v2_user_strings[] = {
668 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
669 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
670 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
671 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
672 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
675 static const struct {
677 enum spectre_v2_user_cmd cmd;
679 } v2_user_options[] __initconst = {
680 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
681 { "off", SPECTRE_V2_USER_CMD_NONE, false },
682 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
683 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
684 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
685 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
686 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
689 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
691 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
692 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
695 static enum spectre_v2_user_cmd __init
696 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
702 case SPECTRE_V2_CMD_NONE:
703 return SPECTRE_V2_USER_CMD_NONE;
704 case SPECTRE_V2_CMD_FORCE:
705 return SPECTRE_V2_USER_CMD_FORCE;
710 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
713 return SPECTRE_V2_USER_CMD_AUTO;
715 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
716 if (match_option(arg, ret, v2_user_options[i].option)) {
717 spec_v2_user_print_cond(v2_user_options[i].option,
718 v2_user_options[i].secure);
719 return v2_user_options[i].cmd;
723 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
724 return SPECTRE_V2_USER_CMD_AUTO;
727 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
729 return (mode == SPECTRE_V2_EIBRS ||
730 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
731 mode == SPECTRE_V2_EIBRS_LFENCE);
735 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
737 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
738 bool smt_possible = IS_ENABLED(CONFIG_SMP);
739 enum spectre_v2_user_cmd cmd;
741 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
744 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
745 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
746 smt_possible = false;
748 cmd = spectre_v2_parse_user_cmdline(v2_cmd);
750 case SPECTRE_V2_USER_CMD_NONE:
752 case SPECTRE_V2_USER_CMD_FORCE:
753 mode = SPECTRE_V2_USER_STRICT;
755 case SPECTRE_V2_USER_CMD_PRCTL:
756 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
757 mode = SPECTRE_V2_USER_PRCTL;
759 case SPECTRE_V2_USER_CMD_AUTO:
760 case SPECTRE_V2_USER_CMD_SECCOMP:
761 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
762 if (IS_ENABLED(CONFIG_SECCOMP))
763 mode = SPECTRE_V2_USER_SECCOMP;
765 mode = SPECTRE_V2_USER_PRCTL;
769 /* Initialize Indirect Branch Prediction Barrier */
770 if (boot_cpu_has(X86_FEATURE_IBPB)) {
771 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
773 spectre_v2_user_ibpb = mode;
775 case SPECTRE_V2_USER_CMD_FORCE:
776 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
777 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
778 static_branch_enable(&switch_mm_always_ibpb);
779 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
781 case SPECTRE_V2_USER_CMD_PRCTL:
782 case SPECTRE_V2_USER_CMD_AUTO:
783 case SPECTRE_V2_USER_CMD_SECCOMP:
784 static_branch_enable(&switch_mm_cond_ibpb);
790 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
791 static_key_enabled(&switch_mm_always_ibpb) ?
792 "always-on" : "conditional");
796 * If no STIBP, enhanced IBRS is enabled or SMT impossible, STIBP is not
799 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
801 spectre_v2_in_eibrs_mode(spectre_v2_enabled))
805 * At this point, an STIBP mode other than "off" has been set.
806 * If STIBP support is not being forced, check if STIBP always-on
809 if (mode != SPECTRE_V2_USER_STRICT &&
810 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
811 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
813 spectre_v2_user_stibp = mode;
816 pr_info("%s\n", spectre_v2_user_strings[mode]);
819 static const char * const spectre_v2_strings[] = {
820 [SPECTRE_V2_NONE] = "Vulnerable",
821 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
822 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
823 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
824 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
825 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
828 static const struct {
830 enum spectre_v2_mitigation_cmd cmd;
832 } mitigation_options[] __initconst = {
833 { "off", SPECTRE_V2_CMD_NONE, false },
834 { "on", SPECTRE_V2_CMD_FORCE, true },
835 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
836 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
837 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
838 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
839 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
840 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
841 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
842 { "auto", SPECTRE_V2_CMD_AUTO, false },
845 static void __init spec_v2_print_cond(const char *reason, bool secure)
847 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
848 pr_info("%s selected on command line.\n", reason);
851 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
853 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
857 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
858 cpu_mitigations_off())
859 return SPECTRE_V2_CMD_NONE;
861 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
863 return SPECTRE_V2_CMD_AUTO;
865 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
866 if (!match_option(arg, ret, mitigation_options[i].option))
868 cmd = mitigation_options[i].cmd;
872 if (i >= ARRAY_SIZE(mitigation_options)) {
873 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
874 return SPECTRE_V2_CMD_AUTO;
877 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
878 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
879 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
880 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
881 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
882 !IS_ENABLED(CONFIG_RETPOLINE)) {
883 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
884 mitigation_options[i].option);
885 return SPECTRE_V2_CMD_AUTO;
888 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
889 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
890 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
891 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
892 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
893 mitigation_options[i].option);
894 return SPECTRE_V2_CMD_AUTO;
897 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
898 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
899 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
900 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
901 mitigation_options[i].option);
902 return SPECTRE_V2_CMD_AUTO;
905 spec_v2_print_cond(mitigation_options[i].option,
906 mitigation_options[i].secure);
910 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
912 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
913 pr_err("Kernel not compiled with retpoline; no mitigation available!");
914 return SPECTRE_V2_NONE;
917 return SPECTRE_V2_RETPOLINE;
920 static void __init spectre_v2_select_mitigation(void)
922 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
923 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
926 * If the CPU is not affected and the command line mode is NONE or AUTO
927 * then nothing to do.
929 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
930 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
934 case SPECTRE_V2_CMD_NONE:
937 case SPECTRE_V2_CMD_FORCE:
938 case SPECTRE_V2_CMD_AUTO:
939 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
940 mode = SPECTRE_V2_EIBRS;
944 mode = spectre_v2_select_retpoline();
947 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
948 pr_err(SPECTRE_V2_LFENCE_MSG);
949 mode = SPECTRE_V2_LFENCE;
952 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
953 mode = SPECTRE_V2_RETPOLINE;
956 case SPECTRE_V2_CMD_RETPOLINE:
957 mode = spectre_v2_select_retpoline();
960 case SPECTRE_V2_CMD_EIBRS:
961 mode = SPECTRE_V2_EIBRS;
964 case SPECTRE_V2_CMD_EIBRS_LFENCE:
965 mode = SPECTRE_V2_EIBRS_LFENCE;
968 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
969 mode = SPECTRE_V2_EIBRS_RETPOLINE;
973 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
974 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
976 if (spectre_v2_in_eibrs_mode(mode)) {
977 /* Force it so VMEXIT will restore correctly */
978 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
979 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
983 case SPECTRE_V2_NONE:
984 case SPECTRE_V2_EIBRS:
987 case SPECTRE_V2_LFENCE:
988 case SPECTRE_V2_EIBRS_LFENCE:
989 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
992 case SPECTRE_V2_RETPOLINE:
993 case SPECTRE_V2_EIBRS_RETPOLINE:
994 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
998 spectre_v2_enabled = mode;
999 pr_info("%s\n", spectre_v2_strings[mode]);
1002 * If spectre v2 protection has been enabled, unconditionally fill
1003 * RSB during a context switch; this protects against two independent
1006 * - RSB underflow (and switch to BTB) on Skylake+
1007 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
1009 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1010 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1013 * Retpoline means the kernel is safe because it has no indirect
1014 * branches. Enhanced IBRS protects firmware too, so, enable restricted
1015 * speculation around firmware calls only when Enhanced IBRS isn't
1018 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1019 * the user might select retpoline on the kernel command line and if
1020 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1021 * enable IBRS around firmware calls.
1023 if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_eibrs_mode(mode)) {
1024 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1025 pr_info("Enabling Restricted Speculation for firmware calls\n");
1028 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1029 spectre_v2_user_select_mitigation(cmd);
1032 static void update_stibp_msr(void * __unused)
1034 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1037 /* Update x86_spec_ctrl_base in case SMT state changed. */
1038 static void update_stibp_strict(void)
1040 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1042 if (sched_smt_active())
1043 mask |= SPEC_CTRL_STIBP;
1045 if (mask == x86_spec_ctrl_base)
1048 pr_info("Update user space SMT mitigation: STIBP %s\n",
1049 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1050 x86_spec_ctrl_base = mask;
1051 on_each_cpu(update_stibp_msr, NULL, 1);
1054 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1055 static void update_indir_branch_cond(void)
1057 if (sched_smt_active())
1058 static_branch_enable(&switch_to_cond_stibp);
1060 static_branch_disable(&switch_to_cond_stibp);
1064 #define pr_fmt(fmt) fmt
1066 /* Update the static key controlling the MDS CPU buffer clear in idle */
1067 static void update_mds_branch_idle(void)
1070 * Enable the idle clearing if SMT is active on CPUs which are
1071 * affected only by MSBDS and not any other MDS variant.
1073 * The other variants cannot be mitigated when SMT is enabled, so
1074 * clearing the buffers on idle just to prevent the Store Buffer
1075 * repartitioning leak would be a window dressing exercise.
1077 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1080 if (sched_smt_active())
1081 static_branch_enable(&mds_idle_clear);
1083 static_branch_disable(&mds_idle_clear);
1086 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1087 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1089 void arch_smt_update(void)
1091 mutex_lock(&spec_ctrl_mutex);
1093 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1094 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1095 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1097 switch (spectre_v2_user_stibp) {
1098 case SPECTRE_V2_USER_NONE:
1100 case SPECTRE_V2_USER_STRICT:
1101 case SPECTRE_V2_USER_STRICT_PREFERRED:
1102 update_stibp_strict();
1104 case SPECTRE_V2_USER_PRCTL:
1105 case SPECTRE_V2_USER_SECCOMP:
1106 update_indir_branch_cond();
1110 switch (mds_mitigation) {
1111 case MDS_MITIGATION_FULL:
1112 case MDS_MITIGATION_VMWERV:
1113 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1114 pr_warn_once(MDS_MSG_SMT);
1115 update_mds_branch_idle();
1117 case MDS_MITIGATION_OFF:
1121 switch (taa_mitigation) {
1122 case TAA_MITIGATION_VERW:
1123 case TAA_MITIGATION_UCODE_NEEDED:
1124 if (sched_smt_active())
1125 pr_warn_once(TAA_MSG_SMT);
1127 case TAA_MITIGATION_TSX_DISABLED:
1128 case TAA_MITIGATION_OFF:
1132 mutex_unlock(&spec_ctrl_mutex);
1136 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1138 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1140 /* The kernel command line selection */
1141 enum ssb_mitigation_cmd {
1142 SPEC_STORE_BYPASS_CMD_NONE,
1143 SPEC_STORE_BYPASS_CMD_AUTO,
1144 SPEC_STORE_BYPASS_CMD_ON,
1145 SPEC_STORE_BYPASS_CMD_PRCTL,
1146 SPEC_STORE_BYPASS_CMD_SECCOMP,
1149 static const char * const ssb_strings[] = {
1150 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1151 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1152 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1153 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1156 static const struct {
1158 enum ssb_mitigation_cmd cmd;
1159 } ssb_mitigation_options[] __initconst = {
1160 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1161 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1162 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1163 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1164 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1167 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1169 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1173 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1174 cpu_mitigations_off()) {
1175 return SPEC_STORE_BYPASS_CMD_NONE;
1177 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1180 return SPEC_STORE_BYPASS_CMD_AUTO;
1182 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1183 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1186 cmd = ssb_mitigation_options[i].cmd;
1190 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1191 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1192 return SPEC_STORE_BYPASS_CMD_AUTO;
1199 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1201 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1202 enum ssb_mitigation_cmd cmd;
1204 if (!boot_cpu_has(X86_FEATURE_SSBD))
1207 cmd = ssb_parse_cmdline();
1208 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1209 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1210 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1214 case SPEC_STORE_BYPASS_CMD_AUTO:
1215 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1217 * Choose prctl+seccomp as the default mode if seccomp is
1220 if (IS_ENABLED(CONFIG_SECCOMP))
1221 mode = SPEC_STORE_BYPASS_SECCOMP;
1223 mode = SPEC_STORE_BYPASS_PRCTL;
1225 case SPEC_STORE_BYPASS_CMD_ON:
1226 mode = SPEC_STORE_BYPASS_DISABLE;
1228 case SPEC_STORE_BYPASS_CMD_PRCTL:
1229 mode = SPEC_STORE_BYPASS_PRCTL;
1231 case SPEC_STORE_BYPASS_CMD_NONE:
1236 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1237 * bit in the mask to allow guests to use the mitigation even in the
1238 * case where the host does not enable it.
1240 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1241 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1242 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1246 * We have three CPU feature flags that are in play here:
1247 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1248 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1249 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1251 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1252 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1254 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1255 * use a completely different MSR and bit dependent on family.
1257 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1258 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1259 x86_amd_ssb_disable();
1261 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1262 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1269 static void ssb_select_mitigation(void)
1271 ssb_mode = __ssb_select_mitigation();
1273 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1274 pr_info("%s\n", ssb_strings[ssb_mode]);
1278 #define pr_fmt(fmt) "Speculation prctl: " fmt
1280 static void task_update_spec_tif(struct task_struct *tsk)
1282 /* Force the update of the real TIF bits */
1283 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1286 * Immediately update the speculation control MSRs for the current
1287 * task, but for a non-current task delay setting the CPU
1288 * mitigation until it is scheduled next.
1290 * This can only happen for SECCOMP mitigation. For PRCTL it's
1291 * always the current task.
1294 speculation_ctrl_update_current();
1297 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1299 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1300 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1304 case PR_SPEC_ENABLE:
1305 /* If speculation is force disabled, enable is not allowed */
1306 if (task_spec_ssb_force_disable(task))
1308 task_clear_spec_ssb_disable(task);
1309 task_update_spec_tif(task);
1311 case PR_SPEC_DISABLE:
1312 task_set_spec_ssb_disable(task);
1313 task_update_spec_tif(task);
1315 case PR_SPEC_FORCE_DISABLE:
1316 task_set_spec_ssb_disable(task);
1317 task_set_spec_ssb_force_disable(task);
1318 task_update_spec_tif(task);
1326 static bool is_spec_ib_user_controlled(void)
1328 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1329 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1330 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1331 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1334 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1337 case PR_SPEC_ENABLE:
1338 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1339 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1342 * With strict mode for both IBPB and STIBP, the instruction
1343 * code paths avoid checking this task flag and instead,
1344 * unconditionally run the instruction. However, STIBP and IBPB
1345 * are independent and either can be set to conditionally
1346 * enabled regardless of the mode of the other.
1348 * If either is set to conditional, allow the task flag to be
1349 * updated, unless it was force-disabled by a previous prctl
1350 * call. Currently, this is possible on an AMD CPU which has the
1351 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1352 * kernel is booted with 'spectre_v2_user=seccomp', then
1353 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1354 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1356 if (!is_spec_ib_user_controlled() ||
1357 task_spec_ib_force_disable(task))
1360 task_clear_spec_ib_disable(task);
1361 task_update_spec_tif(task);
1363 case PR_SPEC_DISABLE:
1364 case PR_SPEC_FORCE_DISABLE:
1366 * Indirect branch speculation is always allowed when
1367 * mitigation is force disabled.
1369 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1370 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1373 if (!is_spec_ib_user_controlled())
1376 task_set_spec_ib_disable(task);
1377 if (ctrl == PR_SPEC_FORCE_DISABLE)
1378 task_set_spec_ib_force_disable(task);
1379 task_update_spec_tif(task);
1387 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1391 case PR_SPEC_STORE_BYPASS:
1392 return ssb_prctl_set(task, ctrl);
1393 case PR_SPEC_INDIRECT_BRANCH:
1394 return ib_prctl_set(task, ctrl);
1400 #ifdef CONFIG_SECCOMP
1401 void arch_seccomp_spec_mitigate(struct task_struct *task)
1403 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1404 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1405 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1406 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1407 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1411 static int ssb_prctl_get(struct task_struct *task)
1414 case SPEC_STORE_BYPASS_DISABLE:
1415 return PR_SPEC_DISABLE;
1416 case SPEC_STORE_BYPASS_SECCOMP:
1417 case SPEC_STORE_BYPASS_PRCTL:
1418 if (task_spec_ssb_force_disable(task))
1419 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1420 if (task_spec_ssb_disable(task))
1421 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1422 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1424 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1425 return PR_SPEC_ENABLE;
1426 return PR_SPEC_NOT_AFFECTED;
1430 static int ib_prctl_get(struct task_struct *task)
1432 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1433 return PR_SPEC_NOT_AFFECTED;
1435 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1436 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1437 return PR_SPEC_ENABLE;
1438 else if (is_spec_ib_user_controlled()) {
1439 if (task_spec_ib_force_disable(task))
1440 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1441 if (task_spec_ib_disable(task))
1442 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1443 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1444 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1445 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1446 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1447 return PR_SPEC_DISABLE;
1449 return PR_SPEC_NOT_AFFECTED;
1452 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1455 case PR_SPEC_STORE_BYPASS:
1456 return ssb_prctl_get(task);
1457 case PR_SPEC_INDIRECT_BRANCH:
1458 return ib_prctl_get(task);
1464 void x86_spec_ctrl_setup_ap(void)
1466 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1467 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1469 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1470 x86_amd_ssb_disable();
1473 bool itlb_multihit_kvm_mitigation;
1474 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1477 #define pr_fmt(fmt) "L1TF: " fmt
1479 /* Default mitigation for L1TF-affected CPUs */
1480 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1481 #if IS_ENABLED(CONFIG_KVM_INTEL)
1482 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1484 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1485 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1488 * These CPUs all support 44bits physical address space internally in the
1489 * cache but CPUID can report a smaller number of physical address bits.
1491 * The L1TF mitigation uses the top most address bit for the inversion of
1492 * non present PTEs. When the installed memory reaches into the top most
1493 * address bit due to memory holes, which has been observed on machines
1494 * which report 36bits physical address bits and have 32G RAM installed,
1495 * then the mitigation range check in l1tf_select_mitigation() triggers.
1496 * This is a false positive because the mitigation is still possible due to
1497 * the fact that the cache uses 44bit internally. Use the cache bits
1498 * instead of the reported physical bits and adjust them on the affected
1499 * machines to 44bit if the reported bits are less than 44.
1501 static void override_cache_bits(struct cpuinfo_x86 *c)
1506 switch (c->x86_model) {
1507 case INTEL_FAM6_NEHALEM:
1508 case INTEL_FAM6_WESTMERE:
1509 case INTEL_FAM6_SANDYBRIDGE:
1510 case INTEL_FAM6_IVYBRIDGE:
1511 case INTEL_FAM6_HASWELL_CORE:
1512 case INTEL_FAM6_HASWELL_ULT:
1513 case INTEL_FAM6_HASWELL_GT3E:
1514 case INTEL_FAM6_BROADWELL_CORE:
1515 case INTEL_FAM6_BROADWELL_GT3E:
1516 case INTEL_FAM6_SKYLAKE_MOBILE:
1517 case INTEL_FAM6_SKYLAKE_DESKTOP:
1518 case INTEL_FAM6_KABYLAKE_MOBILE:
1519 case INTEL_FAM6_KABYLAKE_DESKTOP:
1520 if (c->x86_cache_bits < 44)
1521 c->x86_cache_bits = 44;
1526 static void __init l1tf_select_mitigation(void)
1530 if (!boot_cpu_has_bug(X86_BUG_L1TF))
1533 if (cpu_mitigations_off())
1534 l1tf_mitigation = L1TF_MITIGATION_OFF;
1535 else if (cpu_mitigations_auto_nosmt())
1536 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1538 override_cache_bits(&boot_cpu_data);
1540 switch (l1tf_mitigation) {
1541 case L1TF_MITIGATION_OFF:
1542 case L1TF_MITIGATION_FLUSH_NOWARN:
1543 case L1TF_MITIGATION_FLUSH:
1545 case L1TF_MITIGATION_FLUSH_NOSMT:
1546 case L1TF_MITIGATION_FULL:
1547 cpu_smt_disable(false);
1549 case L1TF_MITIGATION_FULL_FORCE:
1550 cpu_smt_disable(true);
1554 #if CONFIG_PGTABLE_LEVELS == 2
1555 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1559 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1560 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1561 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1562 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1563 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1565 pr_info("However, doing so will make a part of your RAM unusable.\n");
1566 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1570 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1573 static int __init l1tf_cmdline(char *str)
1575 if (!boot_cpu_has_bug(X86_BUG_L1TF))
1581 if (!strcmp(str, "off"))
1582 l1tf_mitigation = L1TF_MITIGATION_OFF;
1583 else if (!strcmp(str, "flush,nowarn"))
1584 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1585 else if (!strcmp(str, "flush"))
1586 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1587 else if (!strcmp(str, "flush,nosmt"))
1588 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1589 else if (!strcmp(str, "full"))
1590 l1tf_mitigation = L1TF_MITIGATION_FULL;
1591 else if (!strcmp(str, "full,force"))
1592 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1596 early_param("l1tf", l1tf_cmdline);
1599 #define pr_fmt(fmt) fmt
1603 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1605 #if IS_ENABLED(CONFIG_KVM_INTEL)
1606 static const char * const l1tf_vmx_states[] = {
1607 [VMENTER_L1D_FLUSH_AUTO] = "auto",
1608 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
1609 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
1610 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
1611 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
1612 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
1615 static ssize_t l1tf_show_state(char *buf)
1617 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1618 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1620 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1621 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1622 sched_smt_active())) {
1623 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1624 l1tf_vmx_states[l1tf_vmx_mitigation]);
1627 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1628 l1tf_vmx_states[l1tf_vmx_mitigation],
1629 sched_smt_active() ? "vulnerable" : "disabled");
1632 static ssize_t itlb_multihit_show_state(char *buf)
1634 if (itlb_multihit_kvm_mitigation)
1635 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
1637 return sprintf(buf, "KVM: Vulnerable\n");
1640 static ssize_t l1tf_show_state(char *buf)
1642 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1645 static ssize_t itlb_multihit_show_state(char *buf)
1647 return sprintf(buf, "Processor vulnerable\n");
1651 static ssize_t mds_show_state(char *buf)
1653 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1654 return sprintf(buf, "%s; SMT Host state unknown\n",
1655 mds_strings[mds_mitigation]);
1658 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1659 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1660 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1661 sched_smt_active() ? "mitigated" : "disabled"));
1664 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1665 sched_smt_active() ? "vulnerable" : "disabled");
1668 static ssize_t tsx_async_abort_show_state(char *buf)
1670 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1671 (taa_mitigation == TAA_MITIGATION_OFF))
1672 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1674 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1675 return sprintf(buf, "%s; SMT Host state unknown\n",
1676 taa_strings[taa_mitigation]);
1679 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1680 sched_smt_active() ? "vulnerable" : "disabled");
1683 static char *stibp_state(void)
1685 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1688 switch (spectre_v2_user_stibp) {
1689 case SPECTRE_V2_USER_NONE:
1690 return ", STIBP: disabled";
1691 case SPECTRE_V2_USER_STRICT:
1692 return ", STIBP: forced";
1693 case SPECTRE_V2_USER_STRICT_PREFERRED:
1694 return ", STIBP: always-on";
1695 case SPECTRE_V2_USER_PRCTL:
1696 case SPECTRE_V2_USER_SECCOMP:
1697 if (static_key_enabled(&switch_to_cond_stibp))
1698 return ", STIBP: conditional";
1703 static char *ibpb_state(void)
1705 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1706 if (static_key_enabled(&switch_mm_always_ibpb))
1707 return ", IBPB: always-on";
1708 if (static_key_enabled(&switch_mm_cond_ibpb))
1709 return ", IBPB: conditional";
1710 return ", IBPB: disabled";
1715 static ssize_t spectre_v2_show_state(char *buf)
1717 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
1718 return sprintf(buf, "Vulnerable: LFENCE\n");
1720 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1721 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
1723 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1724 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1725 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
1727 return sprintf(buf, "%s%s%s%s%s%s\n",
1728 spectre_v2_strings[spectre_v2_enabled],
1730 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1732 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1733 spectre_v2_module_string());
1736 static ssize_t srbds_show_state(char *buf)
1738 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1741 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1742 char *buf, unsigned int bug)
1744 if (!boot_cpu_has_bug(bug))
1745 return sprintf(buf, "Not affected\n");
1748 case X86_BUG_CPU_MELTDOWN:
1749 if (boot_cpu_has(X86_FEATURE_PTI))
1750 return sprintf(buf, "Mitigation: PTI\n");
1752 if (hypervisor_is_type(X86_HYPER_XEN_PV))
1753 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
1757 case X86_BUG_SPECTRE_V1:
1758 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1760 case X86_BUG_SPECTRE_V2:
1761 return spectre_v2_show_state(buf);
1763 case X86_BUG_SPEC_STORE_BYPASS:
1764 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1767 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1768 return l1tf_show_state(buf);
1772 return mds_show_state(buf);
1775 return tsx_async_abort_show_state(buf);
1777 case X86_BUG_ITLB_MULTIHIT:
1778 return itlb_multihit_show_state(buf);
1781 return srbds_show_state(buf);
1787 return sprintf(buf, "Vulnerable\n");
1790 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1792 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1795 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1797 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1800 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1802 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1805 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1807 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1810 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1812 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1815 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1817 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1820 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1822 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1825 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1827 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1830 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1832 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);