arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/module.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16 #include <linux/sched/smt.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/vmx.h>
  26 #include <asm/paravirt.h>
  27 #include <asm/alternative.h>
  28 #include <asm/hypervisor.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/cacheflush.h>
  31 #include <asm/intel-family.h>
  32 #include <asm/e820.h>
  33 #include <linux/bpf.h>
  34
  35 #include "cpu.h"
  36
  37 static void __init spectre_v1_select_mitigation(void);
  38 static void __init spectre_v2_select_mitigation(void);
  39 static void __init ssb_select_mitigation(void);
  40 static void __init l1tf_select_mitigation(void);
  41 static void __init mds_select_mitigation(void);
  42 static void __init md_clear_update_mitigation(void);
  43 static void __init md_clear_select_mitigation(void);
  44 static void __init taa_select_mitigation(void);
  45 static void __init mmio_select_mitigation(void);
  46 static void __init srbds_select_mitigation(void);
  47
  48 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
  49 u64 x86_spec_ctrl_base;
  50 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  51 static DEFINE_MUTEX(spec_ctrl_mutex);
  52
  53 /*
  54  * The vendor and possibly platform specific bits which can be modified in
  55  * x86_spec_ctrl_base.
  56  */
  57 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  58
  59 /*
  60  * AMD specific MSR info for Speculative Store Bypass control.
  61  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  62  */
  63 u64 __ro_after_init x86_amd_ls_cfg_base;
  64 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  65
  66 /* Control conditional STIBP in switch_to() */
  67 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
  68 /* Control conditional IBPB in switch_mm() */
  69 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
  70 /* Control unconditional IBPB in switch_mm() */
  71 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
  72
  73 /* Control MDS CPU buffer clear before returning to user space */
  74 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
  75 EXPORT_SYMBOL_GPL(mds_user_clear);
  76 /* Control MDS CPU buffer clear before idling (halt, mwait) */
  77 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
  78 EXPORT_SYMBOL_GPL(mds_idle_clear);
  79
  80 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
  81 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
  82 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
  83
  84 void __init check_bugs(void)
  85 {
  86         identify_boot_cpu();
  87
  88         /*
  89          * identify_boot_cpu() initialized SMT support information, let the
  90          * core code know.
  91          */
  92         cpu_smt_check_topology_early();
  93
  94         if (!IS_ENABLED(CONFIG_SMP)) {
  95                 pr_info("CPU: ");
  96                 print_cpu_info(&boot_cpu_data);
  97         }
  98
  99         /*
 100          * Read the SPEC_CTRL MSR to account for reserved bits which may
 101          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
 102          * init code as it is not enumerated and depends on the family.
 103          */
 104         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 105                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 106
 107         /* Allow STIBP in MSR_SPEC_CTRL if supported */
 108         if (boot_cpu_has(X86_FEATURE_STIBP))
 109                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
 110
 111         /* Select the proper CPU mitigations before patching alternatives: */
 112         spectre_v1_select_mitigation();
 113         spectre_v2_select_mitigation();
 114         ssb_select_mitigation();
 115         l1tf_select_mitigation();
 116         md_clear_select_mitigation();
 117         srbds_select_mitigation();
 118
 119         arch_smt_update();
 120
 121 #ifdef CONFIG_X86_32
 122         /*
 123          * Check whether we are able to run this kernel safely on SMP.
 124          *
 125          * - i386 is no longer supported.
 126          * - In order to run on anything without a TSC, we need to be
 127          *   compiled for a i486.
 128          */
 129         if (boot_cpu_data.x86 < 4)
 130                 panic("Kernel requires i486+ for 'invlpg' and other features");
 131
 132         init_utsname()->machine[1] =
 133                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 134         alternative_instructions();
 135
 136         fpu__init_check_bugs();
 137 #else /* CONFIG_X86_64 */
 138         alternative_instructions();
 139
 140         /*
 141          * Make sure the first 2MB area is not mapped by huge pages
 142          * There are typically fixed size MTRRs in there and overlapping
 143          * MTRRs into large pages causes slow downs.
 144          *
 145          * Right now we don't do that with gbpages because there seems
 146          * very little benefit for that case.
 147          */
 148         if (!direct_gbpages)
 149                 set_memory_4k((unsigned long)__va(0), 1);
 150 #endif
 151 }
 152
 153 void
 154 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 155 {
 156         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 157         struct thread_info *ti = current_thread_info();
 158
 159         /* Is MSR_SPEC_CTRL implemented ? */
 160         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 161                 /*
 162                  * Restrict guest_spec_ctrl to supported values. Clear the
 163                  * modifiable bits in the host base value and or the
 164                  * modifiable bits from the guest value.
 165                  */
 166                 guestval = hostval & ~x86_spec_ctrl_mask;
 167                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 168
 169                 /* SSBD controlled in MSR_SPEC_CTRL */
 170                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 171                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 172                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 173
 174                 /* Conditional STIBP enabled? */
 175                 if (static_branch_unlikely(&switch_to_cond_stibp))
 176                         hostval |= stibp_tif_to_spec_ctrl(ti->flags);
 177
 178                 if (hostval != guestval) {
 179                         msrval = setguest ? guestval : hostval;
 180                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 181                 }
 182         }
 183
 184         /*
 185          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 186          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 187          */
 188         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 189             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 190                 return;
 191
 192         /*
 193          * If the host has SSBD mitigation enabled, force it in the host's
 194          * virtual MSR value. If its not permanently enabled, evaluate
 195          * current's TIF_SSBD thread flag.
 196          */
 197         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 198                 hostval = SPEC_CTRL_SSBD;
 199         else
 200                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 201
 202         /* Sanitize the guest value */
 203         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 204
 205         if (hostval != guestval) {
 206                 unsigned long tif;
 207
 208                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 209                                  ssbd_spec_ctrl_to_tif(hostval);
 210
 211                 speculation_ctrl_update(tif);
 212         }
 213 }
 214 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 215
 216 static void x86_amd_ssb_disable(void)
 217 {
 218         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 219
 220         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 221                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 222         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 223                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 224 }
 225
 226 #undef pr_fmt
 227 #define pr_fmt(fmt)     "MDS: " fmt
 228
 229 /* Default mitigation for MDS-affected CPUs */
 230 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 231 static bool mds_nosmt __ro_after_init = false;
 232
 233 static const char * const mds_strings[] = {
 234         [MDS_MITIGATION_OFF]    = "Vulnerable",
 235         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 236         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 237 };
 238
 239 static void __init mds_select_mitigation(void)
 240 {
 241         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 242                 mds_mitigation = MDS_MITIGATION_OFF;
 243                 return;
 244         }
 245
 246         if (mds_mitigation == MDS_MITIGATION_FULL) {
 247                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 248                         mds_mitigation = MDS_MITIGATION_VMWERV;
 249
 250                 static_branch_enable(&mds_user_clear);
 251
 252                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 253                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 254                         cpu_smt_disable(false);
 255         }
 256 }
 257
 258 static int __init mds_cmdline(char *str)
 259 {
 260         if (!boot_cpu_has_bug(X86_BUG_MDS))
 261                 return 0;
 262
 263         if (!str)
 264                 return -EINVAL;
 265
 266         if (!strcmp(str, "off"))
 267                 mds_mitigation = MDS_MITIGATION_OFF;
 268         else if (!strcmp(str, "full"))
 269                 mds_mitigation = MDS_MITIGATION_FULL;
 270         else if (!strcmp(str, "full,nosmt")) {
 271                 mds_mitigation = MDS_MITIGATION_FULL;
 272                 mds_nosmt = true;
 273         }
 274
 275         return 0;
 276 }
 277 early_param("mds", mds_cmdline);
 278
 279 #undef pr_fmt
 280 #define pr_fmt(fmt)     "TAA: " fmt
 281
 282 /* Default mitigation for TAA-affected CPUs */
 283 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 284 static bool taa_nosmt __ro_after_init;
 285
 286 static const char * const taa_strings[] = {
 287         [TAA_MITIGATION_OFF]            = "Vulnerable",
 288         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 289         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 290         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 291 };
 292
 293 static void __init taa_select_mitigation(void)
 294 {
 295         u64 ia32_cap;
 296
 297         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 298                 taa_mitigation = TAA_MITIGATION_OFF;
 299                 return;
 300         }
 301
 302         /* TSX previously disabled by tsx=off */
 303         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 304                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 305                 return;
 306         }
 307
 308         if (cpu_mitigations_off()) {
 309                 taa_mitigation = TAA_MITIGATION_OFF;
 310                 return;
 311         }
 312
 313         /*
 314          * TAA mitigation via VERW is turned off if both
 315          * tsx_async_abort=off and mds=off are specified.
 316          */
 317         if (taa_mitigation == TAA_MITIGATION_OFF &&
 318             mds_mitigation == MDS_MITIGATION_OFF)
 319                 return;
 320
 321         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 322                 taa_mitigation = TAA_MITIGATION_VERW;
 323         else
 324                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 325
 326         /*
 327          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 328          * A microcode update fixes this behavior to clear CPU buffers. It also
 329          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 330          * ARCH_CAP_TSX_CTRL_MSR bit.
 331          *
 332          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 333          * update is required.
 334          */
 335         ia32_cap = x86_read_arch_cap_msr();
 336         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 337             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 338                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 339
 340         /*
 341          * TSX is enabled, select alternate mitigation for TAA which is
 342          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 343          *
 344          * For guests that can't determine whether the correct microcode is
 345          * present on host, enable the mitigation for UCODE_NEEDED as well.
 346          */
 347         static_branch_enable(&mds_user_clear);
 348
 349         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 350                 cpu_smt_disable(false);
 351 }
 352
 353 static int __init tsx_async_abort_parse_cmdline(char *str)
 354 {
 355         if (!boot_cpu_has_bug(X86_BUG_TAA))
 356                 return 0;
 357
 358         if (!str)
 359                 return -EINVAL;
 360
 361         if (!strcmp(str, "off")) {
 362                 taa_mitigation = TAA_MITIGATION_OFF;
 363         } else if (!strcmp(str, "full")) {
 364                 taa_mitigation = TAA_MITIGATION_VERW;
 365         } else if (!strcmp(str, "full,nosmt")) {
 366                 taa_mitigation = TAA_MITIGATION_VERW;
 367                 taa_nosmt = true;
 368         }
 369
 370         return 0;
 371 }
 372 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 373
 374 #undef pr_fmt
 375 #define pr_fmt(fmt)     "MMIO Stale Data: " fmt
 376
 377 enum mmio_mitigations {
 378         MMIO_MITIGATION_OFF,
 379         MMIO_MITIGATION_UCODE_NEEDED,
 380         MMIO_MITIGATION_VERW,
 381 };
 382
 383 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
 384 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
 385 static bool mmio_nosmt __ro_after_init = false;
 386
 387 static const char * const mmio_strings[] = {
 388         [MMIO_MITIGATION_OFF]           = "Vulnerable",
 389         [MMIO_MITIGATION_UCODE_NEEDED]  = "Vulnerable: Clear CPU buffers attempted, no microcode",
 390         [MMIO_MITIGATION_VERW]          = "Mitigation: Clear CPU buffers",
 391 };
 392
 393 static void __init mmio_select_mitigation(void)
 394 {
 395         u64 ia32_cap;
 396
 397         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
 398              boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
 399              cpu_mitigations_off()) {
 400                 mmio_mitigation = MMIO_MITIGATION_OFF;
 401                 return;
 402         }
 403
 404         if (mmio_mitigation == MMIO_MITIGATION_OFF)
 405                 return;
 406
 407         ia32_cap = x86_read_arch_cap_msr();
 408
 409         /*
 410          * Enable CPU buffer clear mitigation for host and VMM, if also affected
 411          * by MDS or TAA. Otherwise, enable mitigation for VMM only.
 412          */
 413         if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
 414                                               boot_cpu_has(X86_FEATURE_RTM)))
 415                 static_branch_enable(&mds_user_clear);
 416         else
 417                 static_branch_enable(&mmio_stale_data_clear);
 418
 419         /*
 420          * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
 421          * be propagated to uncore buffers, clearing the Fill buffers on idle
 422          * is required irrespective of SMT state.
 423          */
 424         if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
 425                 static_branch_enable(&mds_idle_clear);
 426
 427         /*
 428          * Check if the system has the right microcode.
 429          *
 430          * CPU Fill buffer clear mitigation is enumerated by either an explicit
 431          * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
 432          * affected systems.
 433          */
 434         if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
 435             (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
 436              boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
 437              !(ia32_cap & ARCH_CAP_MDS_NO)))
 438                 mmio_mitigation = MMIO_MITIGATION_VERW;
 439         else
 440                 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
 441
 442         if (mmio_nosmt || cpu_mitigations_auto_nosmt())
 443                 cpu_smt_disable(false);
 444 }
 445
 446 static int __init mmio_stale_data_parse_cmdline(char *str)
 447 {
 448         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 449                 return 0;
 450
 451         if (!str)
 452                 return -EINVAL;
 453
 454         if (!strcmp(str, "off")) {
 455                 mmio_mitigation = MMIO_MITIGATION_OFF;
 456         } else if (!strcmp(str, "full")) {
 457                 mmio_mitigation = MMIO_MITIGATION_VERW;
 458         } else if (!strcmp(str, "full,nosmt")) {
 459                 mmio_mitigation = MMIO_MITIGATION_VERW;
 460                 mmio_nosmt = true;
 461         }
 462
 463         return 0;
 464 }
 465 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
 466
 467 #undef pr_fmt
 468 #define pr_fmt(fmt)     "" fmt
 469
 470 static void __init md_clear_update_mitigation(void)
 471 {
 472         if (cpu_mitigations_off())
 473                 return;
 474
 475         if (!static_key_enabled(&mds_user_clear))
 476                 goto out;
 477
 478         /*
 479          * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
 480          * mitigation, if necessary.
 481          */
 482         if (mds_mitigation == MDS_MITIGATION_OFF &&
 483             boot_cpu_has_bug(X86_BUG_MDS)) {
 484                 mds_mitigation = MDS_MITIGATION_FULL;
 485                 mds_select_mitigation();
 486         }
 487         if (taa_mitigation == TAA_MITIGATION_OFF &&
 488             boot_cpu_has_bug(X86_BUG_TAA)) {
 489                 taa_mitigation = TAA_MITIGATION_VERW;
 490                 taa_select_mitigation();
 491         }
 492         if (mmio_mitigation == MMIO_MITIGATION_OFF &&
 493             boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
 494                 mmio_mitigation = MMIO_MITIGATION_VERW;
 495                 mmio_select_mitigation();
 496         }
 497 out:
 498         if (boot_cpu_has_bug(X86_BUG_MDS))
 499                 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
 500         if (boot_cpu_has_bug(X86_BUG_TAA))
 501                 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
 502         if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 503                 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
 504         else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
 505                 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
 506 }
 507
 508 static void __init md_clear_select_mitigation(void)
 509 {
 510         mds_select_mitigation();
 511         taa_select_mitigation();
 512         mmio_select_mitigation();
 513
 514         /*
 515          * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
 516          * and print their mitigation after MDS, TAA and MMIO Stale Data
 517          * mitigation selection is done.
 518          */
 519         md_clear_update_mitigation();
 520 }
 521
 522 #undef pr_fmt
 523 #define pr_fmt(fmt)     "SRBDS: " fmt
 524
 525 enum srbds_mitigations {
 526         SRBDS_MITIGATION_OFF,
 527         SRBDS_MITIGATION_UCODE_NEEDED,
 528         SRBDS_MITIGATION_FULL,
 529         SRBDS_MITIGATION_TSX_OFF,
 530         SRBDS_MITIGATION_HYPERVISOR,
 531 };
 532
 533 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 534
 535 static const char * const srbds_strings[] = {
 536         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 537         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 538         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 539         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 540         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 541 };
 542
 543 static bool srbds_off;
 544
 545 void update_srbds_msr(void)
 546 {
 547         u64 mcu_ctrl;
 548
 549         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 550                 return;
 551
 552         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 553                 return;
 554
 555         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 556                 return;
 557
 558         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 559
 560         switch (srbds_mitigation) {
 561         case SRBDS_MITIGATION_OFF:
 562         case SRBDS_MITIGATION_TSX_OFF:
 563                 mcu_ctrl |= RNGDS_MITG_DIS;
 564                 break;
 565         case SRBDS_MITIGATION_FULL:
 566                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 567                 break;
 568         default:
 569                 break;
 570         }
 571
 572         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 573 }
 574
 575 static void __init srbds_select_mitigation(void)
 576 {
 577         u64 ia32_cap;
 578
 579         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 580                 return;
 581
 582         /*
 583          * Check to see if this is one of the MDS_NO systems supporting TSX that
 584          * are only exposed to SRBDS when TSX is enabled or when CPU is affected
 585          * by Processor MMIO Stale Data vulnerability.
 586          */
 587         ia32_cap = x86_read_arch_cap_msr();
 588         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
 589             !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 590                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 591         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 592                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 593         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 594                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 595         else if (cpu_mitigations_off() || srbds_off)
 596                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 597
 598         update_srbds_msr();
 599         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 600 }
 601
 602 static int __init srbds_parse_cmdline(char *str)
 603 {
 604         if (!str)
 605                 return -EINVAL;
 606
 607         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 608                 return 0;
 609
 610         srbds_off = !strcmp(str, "off");
 611         return 0;
 612 }
 613 early_param("srbds", srbds_parse_cmdline);
 614
 615 #undef pr_fmt
 616 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 617
 618 enum spectre_v1_mitigation {
 619         SPECTRE_V1_MITIGATION_NONE,
 620         SPECTRE_V1_MITIGATION_AUTO,
 621 };
 622
 623 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 624         SPECTRE_V1_MITIGATION_AUTO;
 625
 626 static const char * const spectre_v1_strings[] = {
 627         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 628         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 629 };
 630
 631 /*
 632  * Does SMAP provide full mitigation against speculative kernel access to
 633  * userspace?
 634  */
 635 static bool smap_works_speculatively(void)
 636 {
 637         if (!boot_cpu_has(X86_FEATURE_SMAP))
 638                 return false;
 639
 640         /*
 641          * On CPUs which are vulnerable to Meltdown, SMAP does not
 642          * prevent speculative access to user data in the L1 cache.
 643          * Consider SMAP to be non-functional as a mitigation on these
 644          * CPUs.
 645          */
 646         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 647                 return false;
 648
 649         return true;
 650 }
 651
 652 static void __init spectre_v1_select_mitigation(void)
 653 {
 654         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 655                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 656                 return;
 657         }
 658
 659         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 660                 /*
 661                  * With Spectre v1, a user can speculatively control either
 662                  * path of a conditional swapgs with a user-controlled GS
 663                  * value.  The mitigation is to add lfences to both code paths.
 664                  *
 665                  * If FSGSBASE is enabled, the user can put a kernel address in
 666                  * GS, in which case SMAP provides no protection.
 667                  *
 668                  * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
 669                  *         FSGSBASE enablement patches have been merged. ]
 670                  *
 671                  * If FSGSBASE is disabled, the user can only put a user space
 672                  * address in GS.  That makes an attack harder, but still
 673                  * possible if there's no SMAP protection.
 674                  */
 675                 if (!smap_works_speculatively()) {
 676                         /*
 677                          * Mitigation can be provided from SWAPGS itself or
 678                          * PTI as the CR3 write in the Meltdown mitigation
 679                          * is serializing.
 680                          *
 681                          * If neither is there, mitigate with an LFENCE to
 682                          * stop speculation through swapgs.
 683                          */
 684                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 685                             !boot_cpu_has(X86_FEATURE_KAISER))
 686                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 687
 688                         /*
 689                          * Enable lfences in the kernel entry (non-swapgs)
 690                          * paths, to prevent user entry from speculatively
 691                          * skipping swapgs.
 692                          */
 693                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 694                 }
 695         }
 696
 697         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 698 }
 699
 700 static int __init nospectre_v1_cmdline(char *str)
 701 {
 702         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 703         return 0;
 704 }
 705 early_param("nospectre_v1", nospectre_v1_cmdline);
 706
 707 #undef pr_fmt
 708 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 709
 710 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 711         SPECTRE_V2_NONE;
 712
 713 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
 714         SPECTRE_V2_USER_NONE;
 715 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
 716         SPECTRE_V2_USER_NONE;
 717
 718 #ifdef CONFIG_RETPOLINE
 719 static bool spectre_v2_bad_module;
 720
 721 bool retpoline_module_ok(bool has_retpoline)
 722 {
 723         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 724                 return true;
 725
 726         pr_err("System may be vulnerable to spectre v2\n");
 727         spectre_v2_bad_module = true;
 728         return false;
 729 }
 730
 731 static inline const char *spectre_v2_module_string(void)
 732 {
 733         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 734 }
 735 #else
 736 static inline const char *spectre_v2_module_string(void) { return ""; }
 737 #endif
 738
 739 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
 740 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
 741 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
 742
 743 #ifdef CONFIG_BPF_SYSCALL
 744 void unpriv_ebpf_notify(int new_state)
 745 {
 746         if (new_state)
 747                 return;
 748
 749         /* Unprivileged eBPF is enabled */
 750
 751         switch (spectre_v2_enabled) {
 752         case SPECTRE_V2_EIBRS:
 753                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
 754                 break;
 755         case SPECTRE_V2_EIBRS_LFENCE:
 756                 if (sched_smt_active())
 757                         pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
 758                 break;
 759         default:
 760                 break;
 761         }
 762 }
 763 #endif
 764
 765 static inline bool match_option(const char *arg, int arglen, const char *opt)
 766 {
 767         int len = strlen(opt);
 768
 769         return len == arglen && !strncmp(arg, opt, len);
 770 }
 771
 772 /* The kernel command line selection for spectre v2 */
 773 enum spectre_v2_mitigation_cmd {
 774         SPECTRE_V2_CMD_NONE,
 775         SPECTRE_V2_CMD_AUTO,
 776         SPECTRE_V2_CMD_FORCE,
 777         SPECTRE_V2_CMD_RETPOLINE,
 778         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 779         SPECTRE_V2_CMD_RETPOLINE_LFENCE,
 780         SPECTRE_V2_CMD_EIBRS,
 781         SPECTRE_V2_CMD_EIBRS_RETPOLINE,
 782         SPECTRE_V2_CMD_EIBRS_LFENCE,
 783 };
 784
 785 enum spectre_v2_user_cmd {
 786         SPECTRE_V2_USER_CMD_NONE,
 787         SPECTRE_V2_USER_CMD_AUTO,
 788         SPECTRE_V2_USER_CMD_FORCE,
 789         SPECTRE_V2_USER_CMD_PRCTL,
 790         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 791         SPECTRE_V2_USER_CMD_SECCOMP,
 792         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 793 };
 794
 795 static const char * const spectre_v2_user_strings[] = {
 796         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
 797         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
 798         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
 799         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
 800         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
 801 };
 802
 803 static const struct {
 804         const char                      *option;
 805         enum spectre_v2_user_cmd        cmd;
 806         bool                            secure;
 807 } v2_user_options[] __initconst = {
 808         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 809         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 810         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 811         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 812         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 813         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 814         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 815 };
 816
 817 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 818 {
 819         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 820                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 821 }
 822
 823 static enum spectre_v2_user_cmd __init
 824 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
 825 {
 826         char arg[20];
 827         int ret, i;
 828
 829         switch (v2_cmd) {
 830         case SPECTRE_V2_CMD_NONE:
 831                 return SPECTRE_V2_USER_CMD_NONE;
 832         case SPECTRE_V2_CMD_FORCE:
 833                 return SPECTRE_V2_USER_CMD_FORCE;
 834         default:
 835                 break;
 836         }
 837
 838         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 839                                   arg, sizeof(arg));
 840         if (ret < 0)
 841                 return SPECTRE_V2_USER_CMD_AUTO;
 842
 843         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 844                 if (match_option(arg, ret, v2_user_options[i].option)) {
 845                         spec_v2_user_print_cond(v2_user_options[i].option,
 846                                                 v2_user_options[i].secure);
 847                         return v2_user_options[i].cmd;
 848                 }
 849         }
 850
 851         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 852         return SPECTRE_V2_USER_CMD_AUTO;
 853 }
 854
 855 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
 856 {
 857         return (mode == SPECTRE_V2_EIBRS ||
 858                 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
 859                 mode == SPECTRE_V2_EIBRS_LFENCE);
 860 }
 861
 862 static void __init
 863 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
 864 {
 865         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
 866         bool smt_possible = IS_ENABLED(CONFIG_SMP);
 867         enum spectre_v2_user_cmd cmd;
 868
 869         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
 870                 return;
 871
 872         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
 873             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
 874                 smt_possible = false;
 875
 876         cmd = spectre_v2_parse_user_cmdline(v2_cmd);
 877         switch (cmd) {
 878         case SPECTRE_V2_USER_CMD_NONE:
 879                 goto set_mode;
 880         case SPECTRE_V2_USER_CMD_FORCE:
 881                 mode = SPECTRE_V2_USER_STRICT;
 882                 break;
 883         case SPECTRE_V2_USER_CMD_PRCTL:
 884         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 885                 mode = SPECTRE_V2_USER_PRCTL;
 886                 break;
 887         case SPECTRE_V2_USER_CMD_AUTO:
 888         case SPECTRE_V2_USER_CMD_SECCOMP:
 889         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 890                 if (IS_ENABLED(CONFIG_SECCOMP))
 891                         mode = SPECTRE_V2_USER_SECCOMP;
 892                 else
 893                         mode = SPECTRE_V2_USER_PRCTL;
 894                 break;
 895         }
 896
 897         /* Initialize Indirect Branch Prediction Barrier */
 898         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 899                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 900
 901                 spectre_v2_user_ibpb = mode;
 902                 switch (cmd) {
 903                 case SPECTRE_V2_USER_CMD_FORCE:
 904                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 905                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 906                         static_branch_enable(&switch_mm_always_ibpb);
 907                         spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
 908                         break;
 909                 case SPECTRE_V2_USER_CMD_PRCTL:
 910                 case SPECTRE_V2_USER_CMD_AUTO:
 911                 case SPECTRE_V2_USER_CMD_SECCOMP:
 912                         static_branch_enable(&switch_mm_cond_ibpb);
 913                         break;
 914                 default:
 915                         break;
 916                 }
 917
 918                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
 919                         static_key_enabled(&switch_mm_always_ibpb) ?
 920                         "always-on" : "conditional");
 921         }
 922
 923         /*
 924          * If no STIBP, enhanced IBRS is enabled or SMT impossible, STIBP is not
 925          * required.
 926          */
 927         if (!boot_cpu_has(X86_FEATURE_STIBP) ||
 928             !smt_possible ||
 929             spectre_v2_in_eibrs_mode(spectre_v2_enabled))
 930                 return;
 931
 932         /*
 933          * At this point, an STIBP mode other than "off" has been set.
 934          * If STIBP support is not being forced, check if STIBP always-on
 935          * is preferred.
 936          */
 937         if (mode != SPECTRE_V2_USER_STRICT &&
 938             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
 939                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
 940
 941         spectre_v2_user_stibp = mode;
 942
 943 set_mode:
 944         pr_info("%s\n", spectre_v2_user_strings[mode]);
 945 }
 946
 947 static const char * const spectre_v2_strings[] = {
 948         [SPECTRE_V2_NONE]                       = "Vulnerable",
 949         [SPECTRE_V2_RETPOLINE]                  = "Mitigation: Retpolines",
 950         [SPECTRE_V2_LFENCE]                     = "Mitigation: LFENCE",
 951         [SPECTRE_V2_EIBRS]                      = "Mitigation: Enhanced IBRS",
 952         [SPECTRE_V2_EIBRS_LFENCE]               = "Mitigation: Enhanced IBRS + LFENCE",
 953         [SPECTRE_V2_EIBRS_RETPOLINE]            = "Mitigation: Enhanced IBRS + Retpolines",
 954 };
 955
 956 static const struct {
 957         const char *option;
 958         enum spectre_v2_mitigation_cmd cmd;
 959         bool secure;
 960 } mitigation_options[] __initconst = {
 961         { "off",                SPECTRE_V2_CMD_NONE,              false },
 962         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
 963         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
 964         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
 965         { "retpoline,lfence",   SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
 966         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 967         { "eibrs",              SPECTRE_V2_CMD_EIBRS,             false },
 968         { "eibrs,lfence",       SPECTRE_V2_CMD_EIBRS_LFENCE,      false },
 969         { "eibrs,retpoline",    SPECTRE_V2_CMD_EIBRS_RETPOLINE,   false },
 970         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
 971 };
 972
 973 static void __init spec_v2_print_cond(const char *reason, bool secure)
 974 {
 975         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 976                 pr_info("%s selected on command line.\n", reason);
 977 }
 978
 979 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 980 {
 981         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 982         char arg[20];
 983         int ret, i;
 984
 985         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
 986             cpu_mitigations_off())
 987                 return SPECTRE_V2_CMD_NONE;
 988
 989         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 990         if (ret < 0)
 991                 return SPECTRE_V2_CMD_AUTO;
 992
 993         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 994                 if (!match_option(arg, ret, mitigation_options[i].option))
 995                         continue;
 996                 cmd = mitigation_options[i].cmd;
 997                 break;
 998         }
 999
1000         if (i >= ARRAY_SIZE(mitigation_options)) {
1001                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1002                 return SPECTRE_V2_CMD_AUTO;
1003         }
1004
1005         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1006              cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1007              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1008              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1009              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1010             !IS_ENABLED(CONFIG_RETPOLINE)) {
1011                 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1012                        mitigation_options[i].option);
1013                 return SPECTRE_V2_CMD_AUTO;
1014         }
1015
1016         if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1017              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1018              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1019             !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1020                 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1021                        mitigation_options[i].option);
1022                 return SPECTRE_V2_CMD_AUTO;
1023         }
1024
1025         if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1026              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1027             !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1028                 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1029                        mitigation_options[i].option);
1030                 return SPECTRE_V2_CMD_AUTO;
1031         }
1032
1033         spec_v2_print_cond(mitigation_options[i].option,
1034                            mitigation_options[i].secure);
1035         return cmd;
1036 }
1037
1038 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1039 {
1040         if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1041                 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1042                 return SPECTRE_V2_NONE;
1043         }
1044
1045         return SPECTRE_V2_RETPOLINE;
1046 }
1047
1048 static void __init spectre_v2_select_mitigation(void)
1049 {
1050         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1051         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1052
1053         /*
1054          * If the CPU is not affected and the command line mode is NONE or AUTO
1055          * then nothing to do.
1056          */
1057         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1058             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1059                 return;
1060
1061         switch (cmd) {
1062         case SPECTRE_V2_CMD_NONE:
1063                 return;
1064
1065         case SPECTRE_V2_CMD_FORCE:
1066         case SPECTRE_V2_CMD_AUTO:
1067                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1068                         mode = SPECTRE_V2_EIBRS;
1069                         break;
1070                 }
1071
1072                 mode = spectre_v2_select_retpoline();
1073                 break;
1074
1075         case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1076                 pr_err(SPECTRE_V2_LFENCE_MSG);
1077                 mode = SPECTRE_V2_LFENCE;
1078                 break;
1079
1080         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1081                 mode = SPECTRE_V2_RETPOLINE;
1082                 break;
1083
1084         case SPECTRE_V2_CMD_RETPOLINE:
1085                 mode = spectre_v2_select_retpoline();
1086                 break;
1087
1088         case SPECTRE_V2_CMD_EIBRS:
1089                 mode = SPECTRE_V2_EIBRS;
1090                 break;
1091
1092         case SPECTRE_V2_CMD_EIBRS_LFENCE:
1093                 mode = SPECTRE_V2_EIBRS_LFENCE;
1094                 break;
1095
1096         case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1097                 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1098                 break;
1099         }
1100
1101         if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1102                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1103
1104         if (spectre_v2_in_eibrs_mode(mode)) {
1105                 /* Force it so VMEXIT will restore correctly */
1106                 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1107                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1108         }
1109
1110         switch (mode) {
1111         case SPECTRE_V2_NONE:
1112         case SPECTRE_V2_EIBRS:
1113                 break;
1114
1115         case SPECTRE_V2_LFENCE:
1116         case SPECTRE_V2_EIBRS_LFENCE:
1117                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1118                 /* fallthrough */
1119
1120         case SPECTRE_V2_RETPOLINE:
1121         case SPECTRE_V2_EIBRS_RETPOLINE:
1122                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1123                 break;
1124         }
1125
1126         spectre_v2_enabled = mode;
1127         pr_info("%s\n", spectre_v2_strings[mode]);
1128
1129         /*
1130          * If spectre v2 protection has been enabled, unconditionally fill
1131          * RSB during a context switch; this protects against two independent
1132          * issues:
1133          *
1134          *      - RSB underflow (and switch to BTB) on Skylake+
1135          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
1136          */
1137         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1138         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1139
1140         /*
1141          * Retpoline means the kernel is safe because it has no indirect
1142          * branches. Enhanced IBRS protects firmware too, so, enable restricted
1143          * speculation around firmware calls only when Enhanced IBRS isn't
1144          * supported.
1145          *
1146          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1147          * the user might select retpoline on the kernel command line and if
1148          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1149          * enable IBRS around firmware calls.
1150          */
1151         if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_eibrs_mode(mode)) {
1152                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1153                 pr_info("Enabling Restricted Speculation for firmware calls\n");
1154         }
1155
1156         /* Set up IBPB and STIBP depending on the general spectre V2 command */
1157         spectre_v2_user_select_mitigation(cmd);
1158 }
1159
1160 static void update_stibp_msr(void * __unused)
1161 {
1162         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1163 }
1164
1165 /* Update x86_spec_ctrl_base in case SMT state changed. */
1166 static void update_stibp_strict(void)
1167 {
1168         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1169
1170         if (sched_smt_active())
1171                 mask |= SPEC_CTRL_STIBP;
1172
1173         if (mask == x86_spec_ctrl_base)
1174                 return;
1175
1176         pr_info("Update user space SMT mitigation: STIBP %s\n",
1177                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1178         x86_spec_ctrl_base = mask;
1179         on_each_cpu(update_stibp_msr, NULL, 1);
1180 }
1181
1182 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1183 static void update_indir_branch_cond(void)
1184 {
1185         if (sched_smt_active())
1186                 static_branch_enable(&switch_to_cond_stibp);
1187         else
1188                 static_branch_disable(&switch_to_cond_stibp);
1189 }
1190
1191 #undef pr_fmt
1192 #define pr_fmt(fmt) fmt
1193
1194 /* Update the static key controlling the MDS CPU buffer clear in idle */
1195 static void update_mds_branch_idle(void)
1196 {
1197         u64 ia32_cap = x86_read_arch_cap_msr();
1198
1199         /*
1200          * Enable the idle clearing if SMT is active on CPUs which are
1201          * affected only by MSBDS and not any other MDS variant.
1202          *
1203          * The other variants cannot be mitigated when SMT is enabled, so
1204          * clearing the buffers on idle just to prevent the Store Buffer
1205          * repartitioning leak would be a window dressing exercise.
1206          */
1207         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1208                 return;
1209
1210         if (sched_smt_active()) {
1211                 static_branch_enable(&mds_idle_clear);
1212         } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1213                    (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1214                 static_branch_disable(&mds_idle_clear);
1215         }
1216 }
1217
1218 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1219 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1220 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1221
1222 void arch_smt_update(void)
1223 {
1224         mutex_lock(&spec_ctrl_mutex);
1225
1226         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1227             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1228                 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1229
1230         switch (spectre_v2_user_stibp) {
1231         case SPECTRE_V2_USER_NONE:
1232                 break;
1233         case SPECTRE_V2_USER_STRICT:
1234         case SPECTRE_V2_USER_STRICT_PREFERRED:
1235                 update_stibp_strict();
1236                 break;
1237         case SPECTRE_V2_USER_PRCTL:
1238         case SPECTRE_V2_USER_SECCOMP:
1239                 update_indir_branch_cond();
1240                 break;
1241         }
1242
1243         switch (mds_mitigation) {
1244         case MDS_MITIGATION_FULL:
1245         case MDS_MITIGATION_VMWERV:
1246                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1247                         pr_warn_once(MDS_MSG_SMT);
1248                 update_mds_branch_idle();
1249                 break;
1250         case MDS_MITIGATION_OFF:
1251                 break;
1252         }
1253
1254         switch (taa_mitigation) {
1255         case TAA_MITIGATION_VERW:
1256         case TAA_MITIGATION_UCODE_NEEDED:
1257                 if (sched_smt_active())
1258                         pr_warn_once(TAA_MSG_SMT);
1259                 break;
1260         case TAA_MITIGATION_TSX_DISABLED:
1261         case TAA_MITIGATION_OFF:
1262                 break;
1263         }
1264
1265         switch (mmio_mitigation) {
1266         case MMIO_MITIGATION_VERW:
1267         case MMIO_MITIGATION_UCODE_NEEDED:
1268                 if (sched_smt_active())
1269                         pr_warn_once(MMIO_MSG_SMT);
1270                 break;
1271         case MMIO_MITIGATION_OFF:
1272                 break;
1273         }
1274
1275         mutex_unlock(&spec_ctrl_mutex);
1276 }
1277
1278 #undef pr_fmt
1279 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1280
1281 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1282
1283 /* The kernel command line selection */
1284 enum ssb_mitigation_cmd {
1285         SPEC_STORE_BYPASS_CMD_NONE,
1286         SPEC_STORE_BYPASS_CMD_AUTO,
1287         SPEC_STORE_BYPASS_CMD_ON,
1288         SPEC_STORE_BYPASS_CMD_PRCTL,
1289         SPEC_STORE_BYPASS_CMD_SECCOMP,
1290 };
1291
1292 static const char * const ssb_strings[] = {
1293         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1294         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1295         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1296         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1297 };
1298
1299 static const struct {
1300         const char *option;
1301         enum ssb_mitigation_cmd cmd;
1302 } ssb_mitigation_options[]  __initconst = {
1303         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1304         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1305         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1306         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1307         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1308 };
1309
1310 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1311 {
1312         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1313         char arg[20];
1314         int ret, i;
1315
1316         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1317             cpu_mitigations_off()) {
1318                 return SPEC_STORE_BYPASS_CMD_NONE;
1319         } else {
1320                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1321                                           arg, sizeof(arg));
1322                 if (ret < 0)
1323                         return SPEC_STORE_BYPASS_CMD_AUTO;
1324
1325                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1326                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1327                                 continue;
1328
1329                         cmd = ssb_mitigation_options[i].cmd;
1330                         break;
1331                 }
1332
1333                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1334                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1335                         return SPEC_STORE_BYPASS_CMD_AUTO;
1336                 }
1337         }
1338
1339         return cmd;
1340 }
1341
1342 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1343 {
1344         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1345         enum ssb_mitigation_cmd cmd;
1346
1347         if (!boot_cpu_has(X86_FEATURE_SSBD))
1348                 return mode;
1349
1350         cmd = ssb_parse_cmdline();
1351         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1352             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1353              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1354                 return mode;
1355
1356         switch (cmd) {
1357         case SPEC_STORE_BYPASS_CMD_AUTO:
1358         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1359                 /*
1360                  * Choose prctl+seccomp as the default mode if seccomp is
1361                  * enabled.
1362                  */
1363                 if (IS_ENABLED(CONFIG_SECCOMP))
1364                         mode = SPEC_STORE_BYPASS_SECCOMP;
1365                 else
1366                         mode = SPEC_STORE_BYPASS_PRCTL;
1367                 break;
1368         case SPEC_STORE_BYPASS_CMD_ON:
1369                 mode = SPEC_STORE_BYPASS_DISABLE;
1370                 break;
1371         case SPEC_STORE_BYPASS_CMD_PRCTL:
1372                 mode = SPEC_STORE_BYPASS_PRCTL;
1373                 break;
1374         case SPEC_STORE_BYPASS_CMD_NONE:
1375                 break;
1376         }
1377
1378         /*
1379          * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1380          * bit in the mask to allow guests to use the mitigation even in the
1381          * case where the host does not enable it.
1382          */
1383         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1384             static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1385                 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1386         }
1387
1388         /*
1389          * We have three CPU feature flags that are in play here:
1390          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1391          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1392          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1393          */
1394         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1395                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1396                 /*
1397                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1398                  * use a completely different MSR and bit dependent on family.
1399                  */
1400                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1401                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1402                         x86_amd_ssb_disable();
1403                 } else {
1404                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1405                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1406                 }
1407         }
1408
1409         return mode;
1410 }
1411
1412 static void ssb_select_mitigation(void)
1413 {
1414         ssb_mode = __ssb_select_mitigation();
1415
1416         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1417                 pr_info("%s\n", ssb_strings[ssb_mode]);
1418 }
1419
1420 #undef pr_fmt
1421 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1422
1423 static void task_update_spec_tif(struct task_struct *tsk)
1424 {
1425         /* Force the update of the real TIF bits */
1426         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1427
1428         /*
1429          * Immediately update the speculation control MSRs for the current
1430          * task, but for a non-current task delay setting the CPU
1431          * mitigation until it is scheduled next.
1432          *
1433          * This can only happen for SECCOMP mitigation. For PRCTL it's
1434          * always the current task.
1435          */
1436         if (tsk == current)
1437                 speculation_ctrl_update_current();
1438 }
1439
1440 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1441 {
1442         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1443             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1444                 return -ENXIO;
1445
1446         switch (ctrl) {
1447         case PR_SPEC_ENABLE:
1448                 /* If speculation is force disabled, enable is not allowed */
1449                 if (task_spec_ssb_force_disable(task))
1450                         return -EPERM;
1451                 task_clear_spec_ssb_disable(task);
1452                 task_update_spec_tif(task);
1453                 break;
1454         case PR_SPEC_DISABLE:
1455                 task_set_spec_ssb_disable(task);
1456                 task_update_spec_tif(task);
1457                 break;
1458         case PR_SPEC_FORCE_DISABLE:
1459                 task_set_spec_ssb_disable(task);
1460                 task_set_spec_ssb_force_disable(task);
1461                 task_update_spec_tif(task);
1462                 break;
1463         default:
1464                 return -ERANGE;
1465         }
1466         return 0;
1467 }
1468
1469 static bool is_spec_ib_user_controlled(void)
1470 {
1471         return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1472                 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1473                 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1474                 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1475 }
1476
1477 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1478 {
1479         switch (ctrl) {
1480         case PR_SPEC_ENABLE:
1481                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1482                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1483                         return 0;
1484                 /*
1485                  * With strict mode for both IBPB and STIBP, the instruction
1486                  * code paths avoid checking this task flag and instead,
1487                  * unconditionally run the instruction. However, STIBP and IBPB
1488                  * are independent and either can be set to conditionally
1489                  * enabled regardless of the mode of the other.
1490                  *
1491                  * If either is set to conditional, allow the task flag to be
1492                  * updated, unless it was force-disabled by a previous prctl
1493                  * call. Currently, this is possible on an AMD CPU which has the
1494                  * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1495                  * kernel is booted with 'spectre_v2_user=seccomp', then
1496                  * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1497                  * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1498                  */
1499                 if (!is_spec_ib_user_controlled() ||
1500                     task_spec_ib_force_disable(task))
1501                         return -EPERM;
1502
1503                 task_clear_spec_ib_disable(task);
1504                 task_update_spec_tif(task);
1505                 break;
1506         case PR_SPEC_DISABLE:
1507         case PR_SPEC_FORCE_DISABLE:
1508                 /*
1509                  * Indirect branch speculation is always allowed when
1510                  * mitigation is force disabled.
1511                  */
1512                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1513                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1514                         return -EPERM;
1515
1516                 if (!is_spec_ib_user_controlled())
1517                         return 0;
1518
1519                 task_set_spec_ib_disable(task);
1520                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1521                         task_set_spec_ib_force_disable(task);
1522                 task_update_spec_tif(task);
1523                 break;
1524         default:
1525                 return -ERANGE;
1526         }
1527         return 0;
1528 }
1529
1530 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1531                              unsigned long ctrl)
1532 {
1533         switch (which) {
1534         case PR_SPEC_STORE_BYPASS:
1535                 return ssb_prctl_set(task, ctrl);
1536         case PR_SPEC_INDIRECT_BRANCH:
1537                 return ib_prctl_set(task, ctrl);
1538         default:
1539                 return -ENODEV;
1540         }
1541 }
1542
1543 #ifdef CONFIG_SECCOMP
1544 void arch_seccomp_spec_mitigate(struct task_struct *task)
1545 {
1546         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1547                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1548         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1549             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1550                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1551 }
1552 #endif
1553
1554 static int ssb_prctl_get(struct task_struct *task)
1555 {
1556         switch (ssb_mode) {
1557         case SPEC_STORE_BYPASS_DISABLE:
1558                 return PR_SPEC_DISABLE;
1559         case SPEC_STORE_BYPASS_SECCOMP:
1560         case SPEC_STORE_BYPASS_PRCTL:
1561                 if (task_spec_ssb_force_disable(task))
1562                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1563                 if (task_spec_ssb_disable(task))
1564                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1565                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1566         default:
1567                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1568                         return PR_SPEC_ENABLE;
1569                 return PR_SPEC_NOT_AFFECTED;
1570         }
1571 }
1572
1573 static int ib_prctl_get(struct task_struct *task)
1574 {
1575         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1576                 return PR_SPEC_NOT_AFFECTED;
1577
1578         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1579             spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1580                 return PR_SPEC_ENABLE;
1581         else if (is_spec_ib_user_controlled()) {
1582                 if (task_spec_ib_force_disable(task))
1583                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1584                 if (task_spec_ib_disable(task))
1585                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1586                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1587         } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1588             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1589             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1590                 return PR_SPEC_DISABLE;
1591         else
1592                 return PR_SPEC_NOT_AFFECTED;
1593 }
1594
1595 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1596 {
1597         switch (which) {
1598         case PR_SPEC_STORE_BYPASS:
1599                 return ssb_prctl_get(task);
1600         case PR_SPEC_INDIRECT_BRANCH:
1601                 return ib_prctl_get(task);
1602         default:
1603                 return -ENODEV;
1604         }
1605 }
1606
1607 void x86_spec_ctrl_setup_ap(void)
1608 {
1609         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1610                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1611
1612         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1613                 x86_amd_ssb_disable();
1614 }
1615
1616 bool itlb_multihit_kvm_mitigation;
1617 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1618
1619 #undef pr_fmt
1620 #define pr_fmt(fmt)     "L1TF: " fmt
1621
1622 /* Default mitigation for L1TF-affected CPUs */
1623 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1624 #if IS_ENABLED(CONFIG_KVM_INTEL)
1625 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1626 #endif
1627 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1628 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1629
1630 /*
1631  * These CPUs all support 44bits physical address space internally in the
1632  * cache but CPUID can report a smaller number of physical address bits.
1633  *
1634  * The L1TF mitigation uses the top most address bit for the inversion of
1635  * non present PTEs. When the installed memory reaches into the top most
1636  * address bit due to memory holes, which has been observed on machines
1637  * which report 36bits physical address bits and have 32G RAM installed,
1638  * then the mitigation range check in l1tf_select_mitigation() triggers.
1639  * This is a false positive because the mitigation is still possible due to
1640  * the fact that the cache uses 44bit internally. Use the cache bits
1641  * instead of the reported physical bits and adjust them on the affected
1642  * machines to 44bit if the reported bits are less than 44.
1643  */
1644 static void override_cache_bits(struct cpuinfo_x86 *c)
1645 {
1646         if (c->x86 != 6)
1647                 return;
1648
1649         switch (c->x86_model) {
1650         case INTEL_FAM6_NEHALEM:
1651         case INTEL_FAM6_WESTMERE:
1652         case INTEL_FAM6_SANDYBRIDGE:
1653         case INTEL_FAM6_IVYBRIDGE:
1654         case INTEL_FAM6_HASWELL_CORE:
1655         case INTEL_FAM6_HASWELL_ULT:
1656         case INTEL_FAM6_HASWELL_GT3E:
1657         case INTEL_FAM6_BROADWELL_CORE:
1658         case INTEL_FAM6_BROADWELL_GT3E:
1659         case INTEL_FAM6_SKYLAKE_MOBILE:
1660         case INTEL_FAM6_SKYLAKE_DESKTOP:
1661         case INTEL_FAM6_KABYLAKE_MOBILE:
1662         case INTEL_FAM6_KABYLAKE_DESKTOP:
1663                 if (c->x86_cache_bits < 44)
1664                         c->x86_cache_bits = 44;
1665                 break;
1666         }
1667 }
1668
1669 static void __init l1tf_select_mitigation(void)
1670 {
1671         u64 half_pa;
1672
1673         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1674                 return;
1675
1676         if (cpu_mitigations_off())
1677                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1678         else if (cpu_mitigations_auto_nosmt())
1679                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1680
1681         override_cache_bits(&boot_cpu_data);
1682
1683         switch (l1tf_mitigation) {
1684         case L1TF_MITIGATION_OFF:
1685         case L1TF_MITIGATION_FLUSH_NOWARN:
1686         case L1TF_MITIGATION_FLUSH:
1687                 break;
1688         case L1TF_MITIGATION_FLUSH_NOSMT:
1689         case L1TF_MITIGATION_FULL:
1690                 cpu_smt_disable(false);
1691                 break;
1692         case L1TF_MITIGATION_FULL_FORCE:
1693                 cpu_smt_disable(true);
1694                 break;
1695         }
1696
1697 #if CONFIG_PGTABLE_LEVELS == 2
1698         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1699         return;
1700 #endif
1701
1702         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1703         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1704                         e820_any_mapped(half_pa, ULLONG_MAX - half_pa, E820_RAM)) {
1705                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1706                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1707                                 half_pa);
1708                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1709                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1710                 return;
1711         }
1712
1713         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1714 }
1715
1716 static int __init l1tf_cmdline(char *str)
1717 {
1718         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1719                 return 0;
1720
1721         if (!str)
1722                 return -EINVAL;
1723
1724         if (!strcmp(str, "off"))
1725                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1726         else if (!strcmp(str, "flush,nowarn"))
1727                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1728         else if (!strcmp(str, "flush"))
1729                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1730         else if (!strcmp(str, "flush,nosmt"))
1731                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1732         else if (!strcmp(str, "full"))
1733                 l1tf_mitigation = L1TF_MITIGATION_FULL;
1734         else if (!strcmp(str, "full,force"))
1735                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1736
1737         return 0;
1738 }
1739 early_param("l1tf", l1tf_cmdline);
1740
1741 #undef pr_fmt
1742 #define pr_fmt(fmt) fmt
1743
1744 #ifdef CONFIG_SYSFS
1745
1746 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1747
1748 #if IS_ENABLED(CONFIG_KVM_INTEL)
1749 static const char * const l1tf_vmx_states[] = {
1750         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
1751         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
1752         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
1753         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
1754         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
1755         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
1756 };
1757
1758 static ssize_t l1tf_show_state(char *buf)
1759 {
1760         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1761                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1762
1763         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1764             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1765              sched_smt_active())) {
1766                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1767                                l1tf_vmx_states[l1tf_vmx_mitigation]);
1768         }
1769
1770         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1771                        l1tf_vmx_states[l1tf_vmx_mitigation],
1772                        sched_smt_active() ? "vulnerable" : "disabled");
1773 }
1774
1775 static ssize_t itlb_multihit_show_state(char *buf)
1776 {
1777         if (itlb_multihit_kvm_mitigation)
1778                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
1779         else
1780                 return sprintf(buf, "KVM: Vulnerable\n");
1781 }
1782 #else
1783 static ssize_t l1tf_show_state(char *buf)
1784 {
1785         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1786 }
1787
1788 static ssize_t itlb_multihit_show_state(char *buf)
1789 {
1790         return sprintf(buf, "Processor vulnerable\n");
1791 }
1792 #endif
1793
1794 static ssize_t mds_show_state(char *buf)
1795 {
1796 #ifdef CONFIG_HYPERVISOR_GUEST
1797         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1798                 return sprintf(buf, "%s; SMT Host state unknown\n",
1799                                mds_strings[mds_mitigation]);
1800         }
1801 #endif
1802
1803         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1804                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1805                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1806                                 sched_smt_active() ? "mitigated" : "disabled"));
1807         }
1808
1809         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1810                        sched_smt_active() ? "vulnerable" : "disabled");
1811 }
1812
1813 static ssize_t tsx_async_abort_show_state(char *buf)
1814 {
1815         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1816             (taa_mitigation == TAA_MITIGATION_OFF))
1817                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1818
1819         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1820                 return sprintf(buf, "%s; SMT Host state unknown\n",
1821                                taa_strings[taa_mitigation]);
1822         }
1823
1824         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1825                        sched_smt_active() ? "vulnerable" : "disabled");
1826 }
1827
1828 static ssize_t mmio_stale_data_show_state(char *buf)
1829 {
1830         if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
1831                 return sysfs_emit(buf, "Unknown: No mitigations\n");
1832
1833         if (mmio_mitigation == MMIO_MITIGATION_OFF)
1834                 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
1835
1836         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1837                 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
1838                                   mmio_strings[mmio_mitigation]);
1839         }
1840
1841         return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
1842                           sched_smt_active() ? "vulnerable" : "disabled");
1843 }
1844
1845 static char *stibp_state(void)
1846 {
1847         if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1848                 return "";
1849
1850         switch (spectre_v2_user_stibp) {
1851         case SPECTRE_V2_USER_NONE:
1852                 return ", STIBP: disabled";
1853         case SPECTRE_V2_USER_STRICT:
1854                 return ", STIBP: forced";
1855         case SPECTRE_V2_USER_STRICT_PREFERRED:
1856                 return ", STIBP: always-on";
1857         case SPECTRE_V2_USER_PRCTL:
1858         case SPECTRE_V2_USER_SECCOMP:
1859                 if (static_key_enabled(&switch_to_cond_stibp))
1860                         return ", STIBP: conditional";
1861         }
1862         return "";
1863 }
1864
1865 static char *ibpb_state(void)
1866 {
1867         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1868                 if (static_key_enabled(&switch_mm_always_ibpb))
1869                         return ", IBPB: always-on";
1870                 if (static_key_enabled(&switch_mm_cond_ibpb))
1871                         return ", IBPB: conditional";
1872                 return ", IBPB: disabled";
1873         }
1874         return "";
1875 }
1876
1877 static ssize_t spectre_v2_show_state(char *buf)
1878 {
1879         if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
1880                 return sprintf(buf, "Vulnerable: LFENCE\n");
1881
1882         if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1883                 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
1884
1885         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1886             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1887                 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
1888
1889         return sprintf(buf, "%s%s%s%s%s%s\n",
1890                        spectre_v2_strings[spectre_v2_enabled],
1891                        ibpb_state(),
1892                        boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1893                        stibp_state(),
1894                        boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1895                        spectre_v2_module_string());
1896 }
1897
1898 static ssize_t srbds_show_state(char *buf)
1899 {
1900         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1901 }
1902
1903 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1904                                char *buf, unsigned int bug)
1905 {
1906         if (!boot_cpu_has_bug(bug))
1907                 return sprintf(buf, "Not affected\n");
1908
1909         switch (bug) {
1910         case X86_BUG_CPU_MELTDOWN:
1911                 if (boot_cpu_has(X86_FEATURE_KAISER))
1912                         return sprintf(buf, "Mitigation: PTI\n");
1913
1914                 break;
1915
1916         case X86_BUG_SPECTRE_V1:
1917                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1918
1919         case X86_BUG_SPECTRE_V2:
1920                 return spectre_v2_show_state(buf);
1921
1922         case X86_BUG_SPEC_STORE_BYPASS:
1923                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1924
1925         case X86_BUG_L1TF:
1926                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1927                         return l1tf_show_state(buf);
1928                 break;
1929
1930         case X86_BUG_MDS:
1931                 return mds_show_state(buf);
1932
1933         case X86_BUG_TAA:
1934                 return tsx_async_abort_show_state(buf);
1935
1936         case X86_BUG_ITLB_MULTIHIT:
1937                 return itlb_multihit_show_state(buf);
1938
1939         case X86_BUG_SRBDS:
1940                 return srbds_show_state(buf);
1941
1942         case X86_BUG_MMIO_STALE_DATA:
1943         case X86_BUG_MMIO_UNKNOWN:
1944                 return mmio_stale_data_show_state(buf);
1945
1946         default:
1947                 break;
1948         }
1949
1950         return sprintf(buf, "Vulnerable\n");
1951 }
1952
1953 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1954 {
1955         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1956 }
1957
1958 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1959 {
1960         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1961 }
1962
1963 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1964 {
1965         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1966 }
1967
1968 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1969 {
1970         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1971 }
1972
1973 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1974 {
1975         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1976 }
1977
1978 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1979 {
1980         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1981 }
1982
1983 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1984 {
1985         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1986 }
1987
1988 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1989 {
1990         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1991 }
1992
1993 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1994 {
1995         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
1996 }
1997
1998 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
1999 {
2000         if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2001                 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2002         else
2003                 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2004 }
2005 #endif