arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/module.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16 #include <linux/sched/smt.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/vmx.h>
  26 #include <asm/paravirt.h>
  27 #include <asm/alternative.h>
  28 #include <asm/hypervisor.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/cacheflush.h>
  31 #include <asm/intel-family.h>
  32 #include <asm/e820.h>
  33
  34 #include "cpu.h"
  35
  36 static void __init spectre_v1_select_mitigation(void);
  37 static void __init spectre_v2_select_mitigation(void);
  38 static void __init ssb_select_mitigation(void);
  39 static void __init l1tf_select_mitigation(void);
  40 static void __init mds_select_mitigation(void);
  41 static void __init mds_print_mitigation(void);
  42 static void __init taa_select_mitigation(void);
  43 static void __init srbds_select_mitigation(void);
  44
  45 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
  46 u64 x86_spec_ctrl_base;
  47 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  48 static DEFINE_MUTEX(spec_ctrl_mutex);
  49
  50 /*
  51  * The vendor and possibly platform specific bits which can be modified in
  52  * x86_spec_ctrl_base.
  53  */
  54 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  55
  56 /*
  57  * AMD specific MSR info for Speculative Store Bypass control.
  58  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  59  */
  60 u64 __ro_after_init x86_amd_ls_cfg_base;
  61 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  62
  63 /* Control conditional STIBP in switch_to() */
  64 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
  65 /* Control conditional IBPB in switch_mm() */
  66 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
  67 /* Control unconditional IBPB in switch_mm() */
  68 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
  69
  70 /* Control MDS CPU buffer clear before returning to user space */
  71 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
  72 EXPORT_SYMBOL_GPL(mds_user_clear);
  73 /* Control MDS CPU buffer clear before idling (halt, mwait) */
  74 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
  75 EXPORT_SYMBOL_GPL(mds_idle_clear);
  76
  77 void __init check_bugs(void)
  78 {
  79         identify_boot_cpu();
  80
  81         /*
  82          * identify_boot_cpu() initialized SMT support information, let the
  83          * core code know.
  84          */
  85         cpu_smt_check_topology_early();
  86
  87         if (!IS_ENABLED(CONFIG_SMP)) {
  88                 pr_info("CPU: ");
  89                 print_cpu_info(&boot_cpu_data);
  90         }
  91
  92         /*
  93          * Read the SPEC_CTRL MSR to account for reserved bits which may
  94          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  95          * init code as it is not enumerated and depends on the family.
  96          */
  97         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  98                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  99
 100         /* Allow STIBP in MSR_SPEC_CTRL if supported */
 101         if (boot_cpu_has(X86_FEATURE_STIBP))
 102                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
 103
 104         /* Select the proper CPU mitigations before patching alternatives: */
 105         spectre_v1_select_mitigation();
 106         spectre_v2_select_mitigation();
 107         ssb_select_mitigation();
 108         l1tf_select_mitigation();
 109         mds_select_mitigation();
 110         taa_select_mitigation();
 111         srbds_select_mitigation();
 112
 113         /*
 114          * As MDS and TAA mitigations are inter-related, print MDS
 115          * mitigation until after TAA mitigation selection is done.
 116          */
 117         mds_print_mitigation();
 118
 119         arch_smt_update();
 120
 121 #ifdef CONFIG_X86_32
 122         /*
 123          * Check whether we are able to run this kernel safely on SMP.
 124          *
 125          * - i386 is no longer supported.
 126          * - In order to run on anything without a TSC, we need to be
 127          *   compiled for a i486.
 128          */
 129         if (boot_cpu_data.x86 < 4)
 130                 panic("Kernel requires i486+ for 'invlpg' and other features");
 131
 132         init_utsname()->machine[1] =
 133                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 134         alternative_instructions();
 135
 136         fpu__init_check_bugs();
 137 #else /* CONFIG_X86_64 */
 138         alternative_instructions();
 139
 140         /*
 141          * Make sure the first 2MB area is not mapped by huge pages
 142          * There are typically fixed size MTRRs in there and overlapping
 143          * MTRRs into large pages causes slow downs.
 144          *
 145          * Right now we don't do that with gbpages because there seems
 146          * very little benefit for that case.
 147          */
 148         if (!direct_gbpages)
 149                 set_memory_4k((unsigned long)__va(0), 1);
 150 #endif
 151 }
 152
 153 void
 154 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 155 {
 156         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 157         struct thread_info *ti = current_thread_info();
 158
 159         /* Is MSR_SPEC_CTRL implemented ? */
 160         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 161                 /*
 162                  * Restrict guest_spec_ctrl to supported values. Clear the
 163                  * modifiable bits in the host base value and or the
 164                  * modifiable bits from the guest value.
 165                  */
 166                 guestval = hostval & ~x86_spec_ctrl_mask;
 167                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 168
 169                 /* SSBD controlled in MSR_SPEC_CTRL */
 170                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 171                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 172                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 173
 174                 /* Conditional STIBP enabled? */
 175                 if (static_branch_unlikely(&switch_to_cond_stibp))
 176                         hostval |= stibp_tif_to_spec_ctrl(ti->flags);
 177
 178                 if (hostval != guestval) {
 179                         msrval = setguest ? guestval : hostval;
 180                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 181                 }
 182         }
 183
 184         /*
 185          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 186          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 187          */
 188         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 189             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 190                 return;
 191
 192         /*
 193          * If the host has SSBD mitigation enabled, force it in the host's
 194          * virtual MSR value. If its not permanently enabled, evaluate
 195          * current's TIF_SSBD thread flag.
 196          */
 197         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 198                 hostval = SPEC_CTRL_SSBD;
 199         else
 200                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 201
 202         /* Sanitize the guest value */
 203         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 204
 205         if (hostval != guestval) {
 206                 unsigned long tif;
 207
 208                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 209                                  ssbd_spec_ctrl_to_tif(hostval);
 210
 211                 speculation_ctrl_update(tif);
 212         }
 213 }
 214 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 215
 216 static void x86_amd_ssb_disable(void)
 217 {
 218         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 219
 220         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 221                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 222         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 223                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 224 }
 225
 226 #undef pr_fmt
 227 #define pr_fmt(fmt)     "MDS: " fmt
 228
 229 /* Default mitigation for MDS-affected CPUs */
 230 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 231 static bool mds_nosmt __ro_after_init = false;
 232
 233 static const char * const mds_strings[] = {
 234         [MDS_MITIGATION_OFF]    = "Vulnerable",
 235         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 236         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 237 };
 238
 239 static void __init mds_select_mitigation(void)
 240 {
 241         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 242                 mds_mitigation = MDS_MITIGATION_OFF;
 243                 return;
 244         }
 245
 246         if (mds_mitigation == MDS_MITIGATION_FULL) {
 247                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 248                         mds_mitigation = MDS_MITIGATION_VMWERV;
 249
 250                 static_branch_enable(&mds_user_clear);
 251
 252                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 253                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 254                         cpu_smt_disable(false);
 255         }
 256 }
 257
 258 static void __init mds_print_mitigation(void)
 259 {
 260         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
 261                 return;
 262
 263         pr_info("%s\n", mds_strings[mds_mitigation]);
 264 }
 265
 266 static int __init mds_cmdline(char *str)
 267 {
 268         if (!boot_cpu_has_bug(X86_BUG_MDS))
 269                 return 0;
 270
 271         if (!str)
 272                 return -EINVAL;
 273
 274         if (!strcmp(str, "off"))
 275                 mds_mitigation = MDS_MITIGATION_OFF;
 276         else if (!strcmp(str, "full"))
 277                 mds_mitigation = MDS_MITIGATION_FULL;
 278         else if (!strcmp(str, "full,nosmt")) {
 279                 mds_mitigation = MDS_MITIGATION_FULL;
 280                 mds_nosmt = true;
 281         }
 282
 283         return 0;
 284 }
 285 early_param("mds", mds_cmdline);
 286
 287 #undef pr_fmt
 288 #define pr_fmt(fmt)     "TAA: " fmt
 289
 290 /* Default mitigation for TAA-affected CPUs */
 291 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 292 static bool taa_nosmt __ro_after_init;
 293
 294 static const char * const taa_strings[] = {
 295         [TAA_MITIGATION_OFF]            = "Vulnerable",
 296         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 297         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 298         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 299 };
 300
 301 static void __init taa_select_mitigation(void)
 302 {
 303         u64 ia32_cap;
 304
 305         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 306                 taa_mitigation = TAA_MITIGATION_OFF;
 307                 return;
 308         }
 309
 310         /* TSX previously disabled by tsx=off */
 311         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 312                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 313                 goto out;
 314         }
 315
 316         if (cpu_mitigations_off()) {
 317                 taa_mitigation = TAA_MITIGATION_OFF;
 318                 return;
 319         }
 320
 321         /*
 322          * TAA mitigation via VERW is turned off if both
 323          * tsx_async_abort=off and mds=off are specified.
 324          */
 325         if (taa_mitigation == TAA_MITIGATION_OFF &&
 326             mds_mitigation == MDS_MITIGATION_OFF)
 327                 goto out;
 328
 329         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 330                 taa_mitigation = TAA_MITIGATION_VERW;
 331         else
 332                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 333
 334         /*
 335          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 336          * A microcode update fixes this behavior to clear CPU buffers. It also
 337          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 338          * ARCH_CAP_TSX_CTRL_MSR bit.
 339          *
 340          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 341          * update is required.
 342          */
 343         ia32_cap = x86_read_arch_cap_msr();
 344         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 345             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 346                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 347
 348         /*
 349          * TSX is enabled, select alternate mitigation for TAA which is
 350          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 351          *
 352          * For guests that can't determine whether the correct microcode is
 353          * present on host, enable the mitigation for UCODE_NEEDED as well.
 354          */
 355         static_branch_enable(&mds_user_clear);
 356
 357         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 358                 cpu_smt_disable(false);
 359
 360         /*
 361          * Update MDS mitigation, if necessary, as the mds_user_clear is
 362          * now enabled for TAA mitigation.
 363          */
 364         if (mds_mitigation == MDS_MITIGATION_OFF &&
 365             boot_cpu_has_bug(X86_BUG_MDS)) {
 366                 mds_mitigation = MDS_MITIGATION_FULL;
 367                 mds_select_mitigation();
 368         }
 369 out:
 370         pr_info("%s\n", taa_strings[taa_mitigation]);
 371 }
 372
 373 static int __init tsx_async_abort_parse_cmdline(char *str)
 374 {
 375         if (!boot_cpu_has_bug(X86_BUG_TAA))
 376                 return 0;
 377
 378         if (!str)
 379                 return -EINVAL;
 380
 381         if (!strcmp(str, "off")) {
 382                 taa_mitigation = TAA_MITIGATION_OFF;
 383         } else if (!strcmp(str, "full")) {
 384                 taa_mitigation = TAA_MITIGATION_VERW;
 385         } else if (!strcmp(str, "full,nosmt")) {
 386                 taa_mitigation = TAA_MITIGATION_VERW;
 387                 taa_nosmt = true;
 388         }
 389
 390         return 0;
 391 }
 392 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 393
 394 #undef pr_fmt
 395 #define pr_fmt(fmt)     "SRBDS: " fmt
 396
 397 enum srbds_mitigations {
 398         SRBDS_MITIGATION_OFF,
 399         SRBDS_MITIGATION_UCODE_NEEDED,
 400         SRBDS_MITIGATION_FULL,
 401         SRBDS_MITIGATION_TSX_OFF,
 402         SRBDS_MITIGATION_HYPERVISOR,
 403 };
 404
 405 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 406
 407 static const char * const srbds_strings[] = {
 408         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 409         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 410         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 411         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 412         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 413 };
 414
 415 static bool srbds_off;
 416
 417 void update_srbds_msr(void)
 418 {
 419         u64 mcu_ctrl;
 420
 421         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 422                 return;
 423
 424         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 425                 return;
 426
 427         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 428                 return;
 429
 430         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 431
 432         switch (srbds_mitigation) {
 433         case SRBDS_MITIGATION_OFF:
 434         case SRBDS_MITIGATION_TSX_OFF:
 435                 mcu_ctrl |= RNGDS_MITG_DIS;
 436                 break;
 437         case SRBDS_MITIGATION_FULL:
 438                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 439                 break;
 440         default:
 441                 break;
 442         }
 443
 444         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 445 }
 446
 447 static void __init srbds_select_mitigation(void)
 448 {
 449         u64 ia32_cap;
 450
 451         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 452                 return;
 453
 454         /*
 455          * Check to see if this is one of the MDS_NO systems supporting
 456          * TSX that are only exposed to SRBDS when TSX is enabled.
 457          */
 458         ia32_cap = x86_read_arch_cap_msr();
 459         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
 460                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 461         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 462                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 463         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 464                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 465         else if (cpu_mitigations_off() || srbds_off)
 466                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 467
 468         update_srbds_msr();
 469         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 470 }
 471
 472 static int __init srbds_parse_cmdline(char *str)
 473 {
 474         if (!str)
 475                 return -EINVAL;
 476
 477         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 478                 return 0;
 479
 480         srbds_off = !strcmp(str, "off");
 481         return 0;
 482 }
 483 early_param("srbds", srbds_parse_cmdline);
 484
 485 #undef pr_fmt
 486 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 487
 488 enum spectre_v1_mitigation {
 489         SPECTRE_V1_MITIGATION_NONE,
 490         SPECTRE_V1_MITIGATION_AUTO,
 491 };
 492
 493 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 494         SPECTRE_V1_MITIGATION_AUTO;
 495
 496 static const char * const spectre_v1_strings[] = {
 497         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 498         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 499 };
 500
 501 /*
 502  * Does SMAP provide full mitigation against speculative kernel access to
 503  * userspace?
 504  */
 505 static bool smap_works_speculatively(void)
 506 {
 507         if (!boot_cpu_has(X86_FEATURE_SMAP))
 508                 return false;
 509
 510         /*
 511          * On CPUs which are vulnerable to Meltdown, SMAP does not
 512          * prevent speculative access to user data in the L1 cache.
 513          * Consider SMAP to be non-functional as a mitigation on these
 514          * CPUs.
 515          */
 516         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 517                 return false;
 518
 519         return true;
 520 }
 521
 522 static void __init spectre_v1_select_mitigation(void)
 523 {
 524         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 525                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 526                 return;
 527         }
 528
 529         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 530                 /*
 531                  * With Spectre v1, a user can speculatively control either
 532                  * path of a conditional swapgs with a user-controlled GS
 533                  * value.  The mitigation is to add lfences to both code paths.
 534                  *
 535                  * If FSGSBASE is enabled, the user can put a kernel address in
 536                  * GS, in which case SMAP provides no protection.
 537                  *
 538                  * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
 539                  *         FSGSBASE enablement patches have been merged. ]
 540                  *
 541                  * If FSGSBASE is disabled, the user can only put a user space
 542                  * address in GS.  That makes an attack harder, but still
 543                  * possible if there's no SMAP protection.
 544                  */
 545                 if (!smap_works_speculatively()) {
 546                         /*
 547                          * Mitigation can be provided from SWAPGS itself or
 548                          * PTI as the CR3 write in the Meltdown mitigation
 549                          * is serializing.
 550                          *
 551                          * If neither is there, mitigate with an LFENCE to
 552                          * stop speculation through swapgs.
 553                          */
 554                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 555                             !boot_cpu_has(X86_FEATURE_KAISER))
 556                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 557
 558                         /*
 559                          * Enable lfences in the kernel entry (non-swapgs)
 560                          * paths, to prevent user entry from speculatively
 561                          * skipping swapgs.
 562                          */
 563                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 564                 }
 565         }
 566
 567         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 568 }
 569
 570 static int __init nospectre_v1_cmdline(char *str)
 571 {
 572         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 573         return 0;
 574 }
 575 early_param("nospectre_v1", nospectre_v1_cmdline);
 576
 577 #undef pr_fmt
 578 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 579
 580 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 581         SPECTRE_V2_NONE;
 582
 583 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
 584         SPECTRE_V2_USER_NONE;
 585 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
 586         SPECTRE_V2_USER_NONE;
 587
 588 #ifdef RETPOLINE
 589 static bool spectre_v2_bad_module;
 590
 591 bool retpoline_module_ok(bool has_retpoline)
 592 {
 593         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 594                 return true;
 595
 596         pr_err("System may be vulnerable to spectre v2\n");
 597         spectre_v2_bad_module = true;
 598         return false;
 599 }
 600
 601 static inline const char *spectre_v2_module_string(void)
 602 {
 603         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 604 }
 605 #else
 606 static inline const char *spectre_v2_module_string(void) { return ""; }
 607 #endif
 608
 609 static inline bool match_option(const char *arg, int arglen, const char *opt)
 610 {
 611         int len = strlen(opt);
 612
 613         return len == arglen && !strncmp(arg, opt, len);
 614 }
 615
 616 /* The kernel command line selection for spectre v2 */
 617 enum spectre_v2_mitigation_cmd {
 618         SPECTRE_V2_CMD_NONE,
 619         SPECTRE_V2_CMD_AUTO,
 620         SPECTRE_V2_CMD_FORCE,
 621         SPECTRE_V2_CMD_RETPOLINE,
 622         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 623         SPECTRE_V2_CMD_RETPOLINE_AMD,
 624 };
 625
 626 enum spectre_v2_user_cmd {
 627         SPECTRE_V2_USER_CMD_NONE,
 628         SPECTRE_V2_USER_CMD_AUTO,
 629         SPECTRE_V2_USER_CMD_FORCE,
 630         SPECTRE_V2_USER_CMD_PRCTL,
 631         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 632         SPECTRE_V2_USER_CMD_SECCOMP,
 633         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 634 };
 635
 636 static const char * const spectre_v2_user_strings[] = {
 637         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
 638         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
 639         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
 640         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
 641         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
 642 };
 643
 644 static const struct {
 645         const char                      *option;
 646         enum spectre_v2_user_cmd        cmd;
 647         bool                            secure;
 648 } v2_user_options[] __initconst = {
 649         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 650         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 651         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 652         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 653         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 654         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 655         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 656 };
 657
 658 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 659 {
 660         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 661                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 662 }
 663
 664 static enum spectre_v2_user_cmd __init
 665 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
 666 {
 667         char arg[20];
 668         int ret, i;
 669
 670         switch (v2_cmd) {
 671         case SPECTRE_V2_CMD_NONE:
 672                 return SPECTRE_V2_USER_CMD_NONE;
 673         case SPECTRE_V2_CMD_FORCE:
 674                 return SPECTRE_V2_USER_CMD_FORCE;
 675         default:
 676                 break;
 677         }
 678
 679         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 680                                   arg, sizeof(arg));
 681         if (ret < 0)
 682                 return SPECTRE_V2_USER_CMD_AUTO;
 683
 684         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 685                 if (match_option(arg, ret, v2_user_options[i].option)) {
 686                         spec_v2_user_print_cond(v2_user_options[i].option,
 687                                                 v2_user_options[i].secure);
 688                         return v2_user_options[i].cmd;
 689                 }
 690         }
 691
 692         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 693         return SPECTRE_V2_USER_CMD_AUTO;
 694 }
 695
 696 static void __init
 697 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
 698 {
 699         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
 700         bool smt_possible = IS_ENABLED(CONFIG_SMP);
 701         enum spectre_v2_user_cmd cmd;
 702
 703         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
 704                 return;
 705
 706         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
 707             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
 708                 smt_possible = false;
 709
 710         cmd = spectre_v2_parse_user_cmdline(v2_cmd);
 711         switch (cmd) {
 712         case SPECTRE_V2_USER_CMD_NONE:
 713                 goto set_mode;
 714         case SPECTRE_V2_USER_CMD_FORCE:
 715                 mode = SPECTRE_V2_USER_STRICT;
 716                 break;
 717         case SPECTRE_V2_USER_CMD_PRCTL:
 718         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 719                 mode = SPECTRE_V2_USER_PRCTL;
 720                 break;
 721         case SPECTRE_V2_USER_CMD_AUTO:
 722         case SPECTRE_V2_USER_CMD_SECCOMP:
 723         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 724                 if (IS_ENABLED(CONFIG_SECCOMP))
 725                         mode = SPECTRE_V2_USER_SECCOMP;
 726                 else
 727                         mode = SPECTRE_V2_USER_PRCTL;
 728                 break;
 729         }
 730
 731         /* Initialize Indirect Branch Prediction Barrier */
 732         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 733                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 734
 735                 spectre_v2_user_ibpb = mode;
 736                 switch (cmd) {
 737                 case SPECTRE_V2_USER_CMD_FORCE:
 738                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 739                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 740                         static_branch_enable(&switch_mm_always_ibpb);
 741                         spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
 742                         break;
 743                 case SPECTRE_V2_USER_CMD_PRCTL:
 744                 case SPECTRE_V2_USER_CMD_AUTO:
 745                 case SPECTRE_V2_USER_CMD_SECCOMP:
 746                         static_branch_enable(&switch_mm_cond_ibpb);
 747                         break;
 748                 default:
 749                         break;
 750                 }
 751
 752                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
 753                         static_key_enabled(&switch_mm_always_ibpb) ?
 754                         "always-on" : "conditional");
 755         }
 756
 757         /*
 758          * If enhanced IBRS is enabled or SMT impossible, STIBP is not
 759          * required.
 760          */
 761         if (!smt_possible || spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
 762                 return;
 763
 764         /*
 765          * At this point, an STIBP mode other than "off" has been set.
 766          * If STIBP support is not being forced, check if STIBP always-on
 767          * is preferred.
 768          */
 769         if (mode != SPECTRE_V2_USER_STRICT &&
 770             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
 771                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
 772
 773         /*
 774          * If STIBP is not available, clear the STIBP mode.
 775          */
 776         if (!boot_cpu_has(X86_FEATURE_STIBP))
 777                 mode = SPECTRE_V2_USER_NONE;
 778
 779         spectre_v2_user_stibp = mode;
 780
 781 set_mode:
 782         pr_info("%s\n", spectre_v2_user_strings[mode]);
 783 }
 784
 785 static const char * const spectre_v2_strings[] = {
 786         [SPECTRE_V2_NONE]                       = "Vulnerable",
 787         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 788         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 789         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 790         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 791         [SPECTRE_V2_IBRS_ENHANCED]              = "Mitigation: Enhanced IBRS",
 792 };
 793
 794 static const struct {
 795         const char *option;
 796         enum spectre_v2_mitigation_cmd cmd;
 797         bool secure;
 798 } mitigation_options[] __initconst = {
 799         { "off",                SPECTRE_V2_CMD_NONE,              false },
 800         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
 801         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
 802         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 803         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 804         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
 805 };
 806
 807 static void __init spec_v2_print_cond(const char *reason, bool secure)
 808 {
 809         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 810                 pr_info("%s selected on command line.\n", reason);
 811 }
 812
 813 static inline bool retp_compiler(void)
 814 {
 815         return __is_defined(RETPOLINE);
 816 }
 817
 818 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 819 {
 820         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 821         char arg[20];
 822         int ret, i;
 823
 824         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
 825             cpu_mitigations_off())
 826                 return SPECTRE_V2_CMD_NONE;
 827
 828         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 829         if (ret < 0)
 830                 return SPECTRE_V2_CMD_AUTO;
 831
 832         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 833                 if (!match_option(arg, ret, mitigation_options[i].option))
 834                         continue;
 835                 cmd = mitigation_options[i].cmd;
 836                 break;
 837         }
 838
 839         if (i >= ARRAY_SIZE(mitigation_options)) {
 840                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 841                 return SPECTRE_V2_CMD_AUTO;
 842         }
 843
 844         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 845              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 846              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 847             !IS_ENABLED(CONFIG_RETPOLINE)) {
 848                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 849                 return SPECTRE_V2_CMD_AUTO;
 850         }
 851
 852         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 853             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 854                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 855                 return SPECTRE_V2_CMD_AUTO;
 856         }
 857
 858         spec_v2_print_cond(mitigation_options[i].option,
 859                            mitigation_options[i].secure);
 860         return cmd;
 861 }
 862
 863 static void __init spectre_v2_select_mitigation(void)
 864 {
 865         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 866         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 867
 868         /*
 869          * If the CPU is not affected and the command line mode is NONE or AUTO
 870          * then nothing to do.
 871          */
 872         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 873             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 874                 return;
 875
 876         switch (cmd) {
 877         case SPECTRE_V2_CMD_NONE:
 878                 return;
 879
 880         case SPECTRE_V2_CMD_FORCE:
 881         case SPECTRE_V2_CMD_AUTO:
 882                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
 883                         mode = SPECTRE_V2_IBRS_ENHANCED;
 884                         /* Force it so VMEXIT will restore correctly */
 885                         x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
 886                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 887                         goto specv2_set_mode;
 888                 }
 889                 if (IS_ENABLED(CONFIG_RETPOLINE))
 890                         goto retpoline_auto;
 891                 break;
 892         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 893                 if (IS_ENABLED(CONFIG_RETPOLINE))
 894                         goto retpoline_amd;
 895                 break;
 896         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 897                 if (IS_ENABLED(CONFIG_RETPOLINE))
 898                         goto retpoline_generic;
 899                 break;
 900         case SPECTRE_V2_CMD_RETPOLINE:
 901                 if (IS_ENABLED(CONFIG_RETPOLINE))
 902                         goto retpoline_auto;
 903                 break;
 904         }
 905         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 906         return;
 907
 908 retpoline_auto:
 909         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 910         retpoline_amd:
 911                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 912                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 913                         goto retpoline_generic;
 914                 }
 915                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 916                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 917                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 918                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 919         } else {
 920         retpoline_generic:
 921                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 922                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 923                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 924         }
 925
 926 specv2_set_mode:
 927         spectre_v2_enabled = mode;
 928         pr_info("%s\n", spectre_v2_strings[mode]);
 929
 930         /*
 931          * If spectre v2 protection has been enabled, unconditionally fill
 932          * RSB during a context switch; this protects against two independent
 933          * issues:
 934          *
 935          *      - RSB underflow (and switch to BTB) on Skylake+
 936          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
 937          */
 938         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 939         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 940
 941         /*
 942          * Retpoline means the kernel is safe because it has no indirect
 943          * branches. Enhanced IBRS protects firmware too, so, enable restricted
 944          * speculation around firmware calls only when Enhanced IBRS isn't
 945          * supported.
 946          *
 947          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
 948          * the user might select retpoline on the kernel command line and if
 949          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
 950          * enable IBRS around firmware calls.
 951          */
 952         if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
 953                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 954                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 955         }
 956
 957         /* Set up IBPB and STIBP depending on the general spectre V2 command */
 958         spectre_v2_user_select_mitigation(cmd);
 959 }
 960
 961 static void update_stibp_msr(void * __unused)
 962 {
 963         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 964 }
 965
 966 /* Update x86_spec_ctrl_base in case SMT state changed. */
 967 static void update_stibp_strict(void)
 968 {
 969         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
 970
 971         if (sched_smt_active())
 972                 mask |= SPEC_CTRL_STIBP;
 973
 974         if (mask == x86_spec_ctrl_base)
 975                 return;
 976
 977         pr_info("Update user space SMT mitigation: STIBP %s\n",
 978                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
 979         x86_spec_ctrl_base = mask;
 980         on_each_cpu(update_stibp_msr, NULL, 1);
 981 }
 982
 983 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
 984 static void update_indir_branch_cond(void)
 985 {
 986         if (sched_smt_active())
 987                 static_branch_enable(&switch_to_cond_stibp);
 988         else
 989                 static_branch_disable(&switch_to_cond_stibp);
 990 }
 991
 992 #undef pr_fmt
 993 #define pr_fmt(fmt) fmt
 994
 995 /* Update the static key controlling the MDS CPU buffer clear in idle */
 996 static void update_mds_branch_idle(void)
 997 {
 998         /*
 999          * Enable the idle clearing if SMT is active on CPUs which are
1000          * affected only by MSBDS and not any other MDS variant.
1001          *
1002          * The other variants cannot be mitigated when SMT is enabled, so
1003          * clearing the buffers on idle just to prevent the Store Buffer
1004          * repartitioning leak would be a window dressing exercise.
1005          */
1006         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1007                 return;
1008
1009         if (sched_smt_active())
1010                 static_branch_enable(&mds_idle_clear);
1011         else
1012                 static_branch_disable(&mds_idle_clear);
1013 }
1014
1015 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1016 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1017
1018 void arch_smt_update(void)
1019 {
1020         mutex_lock(&spec_ctrl_mutex);
1021
1022         switch (spectre_v2_user_stibp) {
1023         case SPECTRE_V2_USER_NONE:
1024                 break;
1025         case SPECTRE_V2_USER_STRICT:
1026         case SPECTRE_V2_USER_STRICT_PREFERRED:
1027                 update_stibp_strict();
1028                 break;
1029         case SPECTRE_V2_USER_PRCTL:
1030         case SPECTRE_V2_USER_SECCOMP:
1031                 update_indir_branch_cond();
1032                 break;
1033         }
1034
1035         switch (mds_mitigation) {
1036         case MDS_MITIGATION_FULL:
1037         case MDS_MITIGATION_VMWERV:
1038                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1039                         pr_warn_once(MDS_MSG_SMT);
1040                 update_mds_branch_idle();
1041                 break;
1042         case MDS_MITIGATION_OFF:
1043                 break;
1044         }
1045
1046         switch (taa_mitigation) {
1047         case TAA_MITIGATION_VERW:
1048         case TAA_MITIGATION_UCODE_NEEDED:
1049                 if (sched_smt_active())
1050                         pr_warn_once(TAA_MSG_SMT);
1051                 break;
1052         case TAA_MITIGATION_TSX_DISABLED:
1053         case TAA_MITIGATION_OFF:
1054                 break;
1055         }
1056
1057         mutex_unlock(&spec_ctrl_mutex);
1058 }
1059
1060 #undef pr_fmt
1061 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1062
1063 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1064
1065 /* The kernel command line selection */
1066 enum ssb_mitigation_cmd {
1067         SPEC_STORE_BYPASS_CMD_NONE,
1068         SPEC_STORE_BYPASS_CMD_AUTO,
1069         SPEC_STORE_BYPASS_CMD_ON,
1070         SPEC_STORE_BYPASS_CMD_PRCTL,
1071         SPEC_STORE_BYPASS_CMD_SECCOMP,
1072 };
1073
1074 static const char * const ssb_strings[] = {
1075         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1076         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1077         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1078         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1079 };
1080
1081 static const struct {
1082         const char *option;
1083         enum ssb_mitigation_cmd cmd;
1084 } ssb_mitigation_options[]  __initconst = {
1085         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1086         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1087         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1088         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1089         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1090 };
1091
1092 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1093 {
1094         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1095         char arg[20];
1096         int ret, i;
1097
1098         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1099             cpu_mitigations_off()) {
1100                 return SPEC_STORE_BYPASS_CMD_NONE;
1101         } else {
1102                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1103                                           arg, sizeof(arg));
1104                 if (ret < 0)
1105                         return SPEC_STORE_BYPASS_CMD_AUTO;
1106
1107                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1108                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1109                                 continue;
1110
1111                         cmd = ssb_mitigation_options[i].cmd;
1112                         break;
1113                 }
1114
1115                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1116                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1117                         return SPEC_STORE_BYPASS_CMD_AUTO;
1118                 }
1119         }
1120
1121         return cmd;
1122 }
1123
1124 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1125 {
1126         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1127         enum ssb_mitigation_cmd cmd;
1128
1129         if (!boot_cpu_has(X86_FEATURE_SSBD))
1130                 return mode;
1131
1132         cmd = ssb_parse_cmdline();
1133         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1134             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1135              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1136                 return mode;
1137
1138         switch (cmd) {
1139         case SPEC_STORE_BYPASS_CMD_AUTO:
1140         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1141                 /*
1142                  * Choose prctl+seccomp as the default mode if seccomp is
1143                  * enabled.
1144                  */
1145                 if (IS_ENABLED(CONFIG_SECCOMP))
1146                         mode = SPEC_STORE_BYPASS_SECCOMP;
1147                 else
1148                         mode = SPEC_STORE_BYPASS_PRCTL;
1149                 break;
1150         case SPEC_STORE_BYPASS_CMD_ON:
1151                 mode = SPEC_STORE_BYPASS_DISABLE;
1152                 break;
1153         case SPEC_STORE_BYPASS_CMD_PRCTL:
1154                 mode = SPEC_STORE_BYPASS_PRCTL;
1155                 break;
1156         case SPEC_STORE_BYPASS_CMD_NONE:
1157                 break;
1158         }
1159
1160         /*
1161          * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1162          * bit in the mask to allow guests to use the mitigation even in the
1163          * case where the host does not enable it.
1164          */
1165         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1166             static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1167                 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1168         }
1169
1170         /*
1171          * We have three CPU feature flags that are in play here:
1172          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1173          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1174          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1175          */
1176         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1177                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1178                 /*
1179                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1180                  * use a completely different MSR and bit dependent on family.
1181                  */
1182                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1183                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1184                         x86_amd_ssb_disable();
1185                 } else {
1186                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1187                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1188                 }
1189         }
1190
1191         return mode;
1192 }
1193
1194 static void ssb_select_mitigation(void)
1195 {
1196         ssb_mode = __ssb_select_mitigation();
1197
1198         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1199                 pr_info("%s\n", ssb_strings[ssb_mode]);
1200 }
1201
1202 #undef pr_fmt
1203 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1204
1205 static void task_update_spec_tif(struct task_struct *tsk)
1206 {
1207         /* Force the update of the real TIF bits */
1208         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1209
1210         /*
1211          * Immediately update the speculation control MSRs for the current
1212          * task, but for a non-current task delay setting the CPU
1213          * mitigation until it is scheduled next.
1214          *
1215          * This can only happen for SECCOMP mitigation. For PRCTL it's
1216          * always the current task.
1217          */
1218         if (tsk == current)
1219                 speculation_ctrl_update_current();
1220 }
1221
1222 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1223 {
1224         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1225             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1226                 return -ENXIO;
1227
1228         switch (ctrl) {
1229         case PR_SPEC_ENABLE:
1230                 /* If speculation is force disabled, enable is not allowed */
1231                 if (task_spec_ssb_force_disable(task))
1232                         return -EPERM;
1233                 task_clear_spec_ssb_disable(task);
1234                 task_update_spec_tif(task);
1235                 break;
1236         case PR_SPEC_DISABLE:
1237                 task_set_spec_ssb_disable(task);
1238                 task_update_spec_tif(task);
1239                 break;
1240         case PR_SPEC_FORCE_DISABLE:
1241                 task_set_spec_ssb_disable(task);
1242                 task_set_spec_ssb_force_disable(task);
1243                 task_update_spec_tif(task);
1244                 break;
1245         default:
1246                 return -ERANGE;
1247         }
1248         return 0;
1249 }
1250
1251 static bool is_spec_ib_user_controlled(void)
1252 {
1253         return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1254                 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1255                 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1256                 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1257 }
1258
1259 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1260 {
1261         switch (ctrl) {
1262         case PR_SPEC_ENABLE:
1263                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1264                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1265                         return 0;
1266
1267                 /*
1268                  * With strict mode for both IBPB and STIBP, the instruction
1269                  * code paths avoid checking this task flag and instead,
1270                  * unconditionally run the instruction. However, STIBP and IBPB
1271                  * are independent and either can be set to conditionally
1272                  * enabled regardless of the mode of the other.
1273                  *
1274                  * If either is set to conditional, allow the task flag to be
1275                  * updated, unless it was force-disabled by a previous prctl
1276                  * call. Currently, this is possible on an AMD CPU which has the
1277                  * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1278                  * kernel is booted with 'spectre_v2_user=seccomp', then
1279                  * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1280                  * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1281                  */
1282                 if (!is_spec_ib_user_controlled() ||
1283                     task_spec_ib_force_disable(task))
1284                         return -EPERM;
1285
1286                 task_clear_spec_ib_disable(task);
1287                 task_update_spec_tif(task);
1288                 break;
1289         case PR_SPEC_DISABLE:
1290         case PR_SPEC_FORCE_DISABLE:
1291                 /*
1292                  * Indirect branch speculation is always allowed when
1293                  * mitigation is force disabled.
1294                  */
1295                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1296                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1297                         return -EPERM;
1298
1299                 if (!is_spec_ib_user_controlled())
1300                         return 0;
1301
1302                 task_set_spec_ib_disable(task);
1303                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1304                         task_set_spec_ib_force_disable(task);
1305                 task_update_spec_tif(task);
1306                 break;
1307         default:
1308                 return -ERANGE;
1309         }
1310         return 0;
1311 }
1312
1313 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1314                              unsigned long ctrl)
1315 {
1316         switch (which) {
1317         case PR_SPEC_STORE_BYPASS:
1318                 return ssb_prctl_set(task, ctrl);
1319         case PR_SPEC_INDIRECT_BRANCH:
1320                 return ib_prctl_set(task, ctrl);
1321         default:
1322                 return -ENODEV;
1323         }
1324 }
1325
1326 #ifdef CONFIG_SECCOMP
1327 void arch_seccomp_spec_mitigate(struct task_struct *task)
1328 {
1329         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1330                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1331         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1332             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1333                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1334 }
1335 #endif
1336
1337 static int ssb_prctl_get(struct task_struct *task)
1338 {
1339         switch (ssb_mode) {
1340         case SPEC_STORE_BYPASS_DISABLE:
1341                 return PR_SPEC_DISABLE;
1342         case SPEC_STORE_BYPASS_SECCOMP:
1343         case SPEC_STORE_BYPASS_PRCTL:
1344                 if (task_spec_ssb_force_disable(task))
1345                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1346                 if (task_spec_ssb_disable(task))
1347                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1348                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1349         default:
1350                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1351                         return PR_SPEC_ENABLE;
1352                 return PR_SPEC_NOT_AFFECTED;
1353         }
1354 }
1355
1356 static int ib_prctl_get(struct task_struct *task)
1357 {
1358         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1359                 return PR_SPEC_NOT_AFFECTED;
1360
1361         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1362             spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1363                 return PR_SPEC_ENABLE;
1364         else if (is_spec_ib_user_controlled()) {
1365                 if (task_spec_ib_force_disable(task))
1366                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1367                 if (task_spec_ib_disable(task))
1368                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1369                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1370         } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1371             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1372             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1373                 return PR_SPEC_DISABLE;
1374         else
1375                 return PR_SPEC_NOT_AFFECTED;
1376 }
1377
1378 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1379 {
1380         switch (which) {
1381         case PR_SPEC_STORE_BYPASS:
1382                 return ssb_prctl_get(task);
1383         case PR_SPEC_INDIRECT_BRANCH:
1384                 return ib_prctl_get(task);
1385         default:
1386                 return -ENODEV;
1387         }
1388 }
1389
1390 void x86_spec_ctrl_setup_ap(void)
1391 {
1392         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1393                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1394
1395         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1396                 x86_amd_ssb_disable();
1397 }
1398
1399 bool itlb_multihit_kvm_mitigation;
1400 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1401
1402 #undef pr_fmt
1403 #define pr_fmt(fmt)     "L1TF: " fmt
1404
1405 /* Default mitigation for L1TF-affected CPUs */
1406 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1407 #if IS_ENABLED(CONFIG_KVM_INTEL)
1408 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1409 #endif
1410 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1411 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1412
1413 /*
1414  * These CPUs all support 44bits physical address space internally in the
1415  * cache but CPUID can report a smaller number of physical address bits.
1416  *
1417  * The L1TF mitigation uses the top most address bit for the inversion of
1418  * non present PTEs. When the installed memory reaches into the top most
1419  * address bit due to memory holes, which has been observed on machines
1420  * which report 36bits physical address bits and have 32G RAM installed,
1421  * then the mitigation range check in l1tf_select_mitigation() triggers.
1422  * This is a false positive because the mitigation is still possible due to
1423  * the fact that the cache uses 44bit internally. Use the cache bits
1424  * instead of the reported physical bits and adjust them on the affected
1425  * machines to 44bit if the reported bits are less than 44.
1426  */
1427 static void override_cache_bits(struct cpuinfo_x86 *c)
1428 {
1429         if (c->x86 != 6)
1430                 return;
1431
1432         switch (c->x86_model) {
1433         case INTEL_FAM6_NEHALEM:
1434         case INTEL_FAM6_WESTMERE:
1435         case INTEL_FAM6_SANDYBRIDGE:
1436         case INTEL_FAM6_IVYBRIDGE:
1437         case INTEL_FAM6_HASWELL_CORE:
1438         case INTEL_FAM6_HASWELL_ULT:
1439         case INTEL_FAM6_HASWELL_GT3E:
1440         case INTEL_FAM6_BROADWELL_CORE:
1441         case INTEL_FAM6_BROADWELL_GT3E:
1442         case INTEL_FAM6_SKYLAKE_MOBILE:
1443         case INTEL_FAM6_SKYLAKE_DESKTOP:
1444         case INTEL_FAM6_KABYLAKE_MOBILE:
1445         case INTEL_FAM6_KABYLAKE_DESKTOP:
1446                 if (c->x86_cache_bits < 44)
1447                         c->x86_cache_bits = 44;
1448                 break;
1449         }
1450 }
1451
1452 static void __init l1tf_select_mitigation(void)
1453 {
1454         u64 half_pa;
1455
1456         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1457                 return;
1458
1459         if (cpu_mitigations_off())
1460                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1461         else if (cpu_mitigations_auto_nosmt())
1462                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1463
1464         override_cache_bits(&boot_cpu_data);
1465
1466         switch (l1tf_mitigation) {
1467         case L1TF_MITIGATION_OFF:
1468         case L1TF_MITIGATION_FLUSH_NOWARN:
1469         case L1TF_MITIGATION_FLUSH:
1470                 break;
1471         case L1TF_MITIGATION_FLUSH_NOSMT:
1472         case L1TF_MITIGATION_FULL:
1473                 cpu_smt_disable(false);
1474                 break;
1475         case L1TF_MITIGATION_FULL_FORCE:
1476                 cpu_smt_disable(true);
1477                 break;
1478         }
1479
1480 #if CONFIG_PGTABLE_LEVELS == 2
1481         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1482         return;
1483 #endif
1484
1485         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1486         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1487                         e820_any_mapped(half_pa, ULLONG_MAX - half_pa, E820_RAM)) {
1488                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1489                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1490                                 half_pa);
1491                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1492                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1493                 return;
1494         }
1495
1496         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1497 }
1498
1499 static int __init l1tf_cmdline(char *str)
1500 {
1501         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1502                 return 0;
1503
1504         if (!str)
1505                 return -EINVAL;
1506
1507         if (!strcmp(str, "off"))
1508                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1509         else if (!strcmp(str, "flush,nowarn"))
1510                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1511         else if (!strcmp(str, "flush"))
1512                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1513         else if (!strcmp(str, "flush,nosmt"))
1514                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1515         else if (!strcmp(str, "full"))
1516                 l1tf_mitigation = L1TF_MITIGATION_FULL;
1517         else if (!strcmp(str, "full,force"))
1518                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1519
1520         return 0;
1521 }
1522 early_param("l1tf", l1tf_cmdline);
1523
1524 #undef pr_fmt
1525 #define pr_fmt(fmt) fmt
1526
1527 #ifdef CONFIG_SYSFS
1528
1529 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1530
1531 #if IS_ENABLED(CONFIG_KVM_INTEL)
1532 static const char * const l1tf_vmx_states[] = {
1533         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
1534         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
1535         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
1536         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
1537         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
1538         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
1539 };
1540
1541 static ssize_t l1tf_show_state(char *buf)
1542 {
1543         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1544                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1545
1546         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1547             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1548              sched_smt_active())) {
1549                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1550                                l1tf_vmx_states[l1tf_vmx_mitigation]);
1551         }
1552
1553         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1554                        l1tf_vmx_states[l1tf_vmx_mitigation],
1555                        sched_smt_active() ? "vulnerable" : "disabled");
1556 }
1557
1558 static ssize_t itlb_multihit_show_state(char *buf)
1559 {
1560         if (itlb_multihit_kvm_mitigation)
1561                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
1562         else
1563                 return sprintf(buf, "KVM: Vulnerable\n");
1564 }
1565 #else
1566 static ssize_t l1tf_show_state(char *buf)
1567 {
1568         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1569 }
1570
1571 static ssize_t itlb_multihit_show_state(char *buf)
1572 {
1573         return sprintf(buf, "Processor vulnerable\n");
1574 }
1575 #endif
1576
1577 static ssize_t mds_show_state(char *buf)
1578 {
1579 #ifdef CONFIG_HYPERVISOR_GUEST
1580         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1581                 return sprintf(buf, "%s; SMT Host state unknown\n",
1582                                mds_strings[mds_mitigation]);
1583         }
1584 #endif
1585
1586         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1587                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1588                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1589                                 sched_smt_active() ? "mitigated" : "disabled"));
1590         }
1591
1592         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1593                        sched_smt_active() ? "vulnerable" : "disabled");
1594 }
1595
1596 static ssize_t tsx_async_abort_show_state(char *buf)
1597 {
1598         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1599             (taa_mitigation == TAA_MITIGATION_OFF))
1600                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1601
1602         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1603                 return sprintf(buf, "%s; SMT Host state unknown\n",
1604                                taa_strings[taa_mitigation]);
1605         }
1606
1607         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1608                        sched_smt_active() ? "vulnerable" : "disabled");
1609 }
1610
1611 static char *stibp_state(void)
1612 {
1613         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
1614                 return "";
1615
1616         switch (spectre_v2_user_stibp) {
1617         case SPECTRE_V2_USER_NONE:
1618                 return ", STIBP: disabled";
1619         case SPECTRE_V2_USER_STRICT:
1620                 return ", STIBP: forced";
1621         case SPECTRE_V2_USER_STRICT_PREFERRED:
1622                 return ", STIBP: always-on";
1623         case SPECTRE_V2_USER_PRCTL:
1624         case SPECTRE_V2_USER_SECCOMP:
1625                 if (static_key_enabled(&switch_to_cond_stibp))
1626                         return ", STIBP: conditional";
1627         }
1628         return "";
1629 }
1630
1631 static char *ibpb_state(void)
1632 {
1633         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1634                 if (static_key_enabled(&switch_mm_always_ibpb))
1635                         return ", IBPB: always-on";
1636                 if (static_key_enabled(&switch_mm_cond_ibpb))
1637                         return ", IBPB: conditional";
1638                 return ", IBPB: disabled";
1639         }
1640         return "";
1641 }
1642
1643 static ssize_t srbds_show_state(char *buf)
1644 {
1645         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1646 }
1647
1648 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1649                                char *buf, unsigned int bug)
1650 {
1651         if (!boot_cpu_has_bug(bug))
1652                 return sprintf(buf, "Not affected\n");
1653
1654         switch (bug) {
1655         case X86_BUG_CPU_MELTDOWN:
1656                 if (boot_cpu_has(X86_FEATURE_KAISER))
1657                         return sprintf(buf, "Mitigation: PTI\n");
1658
1659                 break;
1660
1661         case X86_BUG_SPECTRE_V1:
1662                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1663
1664         case X86_BUG_SPECTRE_V2:
1665                 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1666                                ibpb_state(),
1667                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1668                                stibp_state(),
1669                                boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1670                                spectre_v2_module_string());
1671
1672         case X86_BUG_SPEC_STORE_BYPASS:
1673                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1674
1675         case X86_BUG_L1TF:
1676                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1677                         return l1tf_show_state(buf);
1678                 break;
1679
1680         case X86_BUG_MDS:
1681                 return mds_show_state(buf);
1682
1683         case X86_BUG_TAA:
1684                 return tsx_async_abort_show_state(buf);
1685
1686         case X86_BUG_ITLB_MULTIHIT:
1687                 return itlb_multihit_show_state(buf);
1688
1689         case X86_BUG_SRBDS:
1690                 return srbds_show_state(buf);
1691
1692         default:
1693                 break;
1694         }
1695
1696         return sprintf(buf, "Vulnerable\n");
1697 }
1698
1699 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1700 {
1701         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1702 }
1703
1704 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1705 {
1706         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1707 }
1708
1709 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1710 {
1711         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1712 }
1713
1714 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1715 {
1716         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1717 }
1718
1719 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1720 {
1721         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1722 }
1723
1724 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1725 {
1726         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1727 }
1728
1729 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1730 {
1731         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1732 }
1733
1734 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1735 {
1736         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1737 }
1738
1739 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1740 {
1741         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
1742 }
1743 #endif