arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17 #include <linux/sched/smt.h>
  18
  19 #include <asm/spec-ctrl.h>
  20 #include <asm/cmdline.h>
  21 #include <asm/bugs.h>
  22 #include <asm/processor.h>
  23 #include <asm/processor-flags.h>
  24 #include <asm/fpu/internal.h>
  25 #include <asm/msr.h>
  26 #include <asm/vmx.h>
  27 #include <asm/paravirt.h>
  28 #include <asm/alternative.h>
  29 #include <asm/hypervisor.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/set_memory.h>
  32 #include <asm/intel-family.h>
  33 #include <asm/e820/api.h>
  34 #include <linux/bpf.h>
  35
  36 #include "cpu.h"
  37
  38 static void __init spectre_v1_select_mitigation(void);
  39 static void __init spectre_v2_select_mitigation(void);
  40 static void __init retbleed_select_mitigation(void);
  41 static void __init spectre_v2_user_select_mitigation(void);
  42 static void __init ssb_select_mitigation(void);
  43 static void __init l1tf_select_mitigation(void);
  44 static void __init mds_select_mitigation(void);
  45 static void __init md_clear_update_mitigation(void);
  46 static void __init md_clear_select_mitigation(void);
  47 static void __init taa_select_mitigation(void);
  48 static void __init mmio_select_mitigation(void);
  49 static void __init srbds_select_mitigation(void);
  50
  51 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
  52 u64 x86_spec_ctrl_base;
  53 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  54
  55 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
  56 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
  57 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
  58
  59 static DEFINE_MUTEX(spec_ctrl_mutex);
  60
  61 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
  62 static void update_spec_ctrl(u64 val)
  63 {
  64         this_cpu_write(x86_spec_ctrl_current, val);
  65         wrmsrl(MSR_IA32_SPEC_CTRL, val);
  66 }
  67
  68 /*
  69  * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
  70  * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
  71  */
  72 void update_spec_ctrl_cond(u64 val)
  73 {
  74         if (this_cpu_read(x86_spec_ctrl_current) == val)
  75                 return;
  76
  77         this_cpu_write(x86_spec_ctrl_current, val);
  78
  79         /*
  80          * When KERNEL_IBRS this MSR is written on return-to-user, unless
  81          * forced the update can be delayed until that time.
  82          */
  83         if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
  84                 wrmsrl(MSR_IA32_SPEC_CTRL, val);
  85 }
  86
  87 u64 spec_ctrl_current(void)
  88 {
  89         return this_cpu_read(x86_spec_ctrl_current);
  90 }
  91 EXPORT_SYMBOL_GPL(spec_ctrl_current);
  92
  93 /*
  94  * AMD specific MSR info for Speculative Store Bypass control.
  95  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  96  */
  97 u64 __ro_after_init x86_amd_ls_cfg_base;
  98 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  99
 100 /* Control conditional STIBP in switch_to() */
 101 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 102 /* Control conditional IBPB in switch_mm() */
 103 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 104 /* Control unconditional IBPB in switch_mm() */
 105 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 106
 107 /* Control MDS CPU buffer clear before returning to user space */
 108 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
 109 EXPORT_SYMBOL_GPL(mds_user_clear);
 110 /* Control MDS CPU buffer clear before idling (halt, mwait) */
 111 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
 112 EXPORT_SYMBOL_GPL(mds_idle_clear);
 113
 114 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
 115 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 116 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
 117
 118 void __init check_bugs(void)
 119 {
 120         identify_boot_cpu();
 121
 122         /*
 123          * identify_boot_cpu() initialized SMT support information, let the
 124          * core code know.
 125          */
 126         cpu_smt_check_topology();
 127
 128         if (!IS_ENABLED(CONFIG_SMP)) {
 129                 pr_info("CPU: ");
 130                 print_cpu_info(&boot_cpu_data);
 131         }
 132
 133         /*
 134          * Read the SPEC_CTRL MSR to account for reserved bits which may
 135          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
 136          * init code as it is not enumerated and depends on the family.
 137          */
 138         if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
 139                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 140
 141                 /*
 142                  * Previously running kernel (kexec), may have some controls
 143                  * turned ON. Clear them and let the mitigations setup below
 144                  * rediscover them based on configuration.
 145                  */
 146                 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
 147         }
 148
 149         /* Select the proper CPU mitigations before patching alternatives: */
 150         spectre_v1_select_mitigation();
 151         spectre_v2_select_mitigation();
 152         /*
 153          * retbleed_select_mitigation() relies on the state set by
 154          * spectre_v2_select_mitigation(); specifically it wants to know about
 155          * spectre_v2=ibrs.
 156          */
 157         retbleed_select_mitigation();
 158         /*
 159          * spectre_v2_user_select_mitigation() relies on the state set by
 160          * retbleed_select_mitigation(); specifically the STIBP selection is
 161          * forced for UNRET.
 162          */
 163         spectre_v2_user_select_mitigation();
 164         ssb_select_mitigation();
 165         l1tf_select_mitigation();
 166         md_clear_select_mitigation();
 167         srbds_select_mitigation();
 168
 169         arch_smt_update();
 170
 171 #ifdef CONFIG_X86_32
 172         /*
 173          * Check whether we are able to run this kernel safely on SMP.
 174          *
 175          * - i386 is no longer supported.
 176          * - In order to run on anything without a TSC, we need to be
 177          *   compiled for a i486.
 178          */
 179         if (boot_cpu_data.x86 < 4)
 180                 panic("Kernel requires i486+ for 'invlpg' and other features");
 181
 182         init_utsname()->machine[1] =
 183                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 184         alternative_instructions();
 185
 186         fpu__init_check_bugs();
 187 #else /* CONFIG_X86_64 */
 188         alternative_instructions();
 189
 190         /*
 191          * Make sure the first 2MB area is not mapped by huge pages
 192          * There are typically fixed size MTRRs in there and overlapping
 193          * MTRRs into large pages causes slow downs.
 194          *
 195          * Right now we don't do that with gbpages because there seems
 196          * very little benefit for that case.
 197          */
 198         if (!direct_gbpages)
 199                 set_memory_4k((unsigned long)__va(0), 1);
 200 #endif
 201 }
 202
 203 /*
 204  * NOTE: For VMX, this function is not called in the vmexit path.
 205  * It uses vmx_spec_ctrl_restore_host() instead.
 206  */
 207 void
 208 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 209 {
 210         u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
 211         struct thread_info *ti = current_thread_info();
 212
 213         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 214                 if (hostval != guestval) {
 215                         msrval = setguest ? guestval : hostval;
 216                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 217                 }
 218         }
 219
 220         /*
 221          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 222          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 223          */
 224         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 225             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 226                 return;
 227
 228         /*
 229          * If the host has SSBD mitigation enabled, force it in the host's
 230          * virtual MSR value. If its not permanently enabled, evaluate
 231          * current's TIF_SSBD thread flag.
 232          */
 233         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 234                 hostval = SPEC_CTRL_SSBD;
 235         else
 236                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 237
 238         /* Sanitize the guest value */
 239         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 240
 241         if (hostval != guestval) {
 242                 unsigned long tif;
 243
 244                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 245                                  ssbd_spec_ctrl_to_tif(hostval);
 246
 247                 speculation_ctrl_update(tif);
 248         }
 249 }
 250 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 251
 252 static void x86_amd_ssb_disable(void)
 253 {
 254         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 255
 256         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 257                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 258         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 259                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 260 }
 261
 262 #undef pr_fmt
 263 #define pr_fmt(fmt)     "MDS: " fmt
 264
 265 /* Default mitigation for MDS-affected CPUs */
 266 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 267 static bool mds_nosmt __ro_after_init = false;
 268
 269 static const char * const mds_strings[] = {
 270         [MDS_MITIGATION_OFF]    = "Vulnerable",
 271         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 272         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 273 };
 274
 275 static void __init mds_select_mitigation(void)
 276 {
 277         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 278                 mds_mitigation = MDS_MITIGATION_OFF;
 279                 return;
 280         }
 281
 282         if (mds_mitigation == MDS_MITIGATION_FULL) {
 283                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 284                         mds_mitigation = MDS_MITIGATION_VMWERV;
 285
 286                 static_branch_enable(&mds_user_clear);
 287
 288                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 289                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 290                         cpu_smt_disable(false);
 291         }
 292 }
 293
 294 static int __init mds_cmdline(char *str)
 295 {
 296         if (!boot_cpu_has_bug(X86_BUG_MDS))
 297                 return 0;
 298
 299         if (!str)
 300                 return -EINVAL;
 301
 302         if (!strcmp(str, "off"))
 303                 mds_mitigation = MDS_MITIGATION_OFF;
 304         else if (!strcmp(str, "full"))
 305                 mds_mitigation = MDS_MITIGATION_FULL;
 306         else if (!strcmp(str, "full,nosmt")) {
 307                 mds_mitigation = MDS_MITIGATION_FULL;
 308                 mds_nosmt = true;
 309         }
 310
 311         return 0;
 312 }
 313 early_param("mds", mds_cmdline);
 314
 315 #undef pr_fmt
 316 #define pr_fmt(fmt)     "TAA: " fmt
 317
 318 /* Default mitigation for TAA-affected CPUs */
 319 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 320 static bool taa_nosmt __ro_after_init;
 321
 322 static const char * const taa_strings[] = {
 323         [TAA_MITIGATION_OFF]            = "Vulnerable",
 324         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 325         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 326         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 327 };
 328
 329 static void __init taa_select_mitigation(void)
 330 {
 331         u64 ia32_cap;
 332
 333         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 334                 taa_mitigation = TAA_MITIGATION_OFF;
 335                 return;
 336         }
 337
 338         /* TSX previously disabled by tsx=off */
 339         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 340                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 341                 return;
 342         }
 343
 344         if (cpu_mitigations_off()) {
 345                 taa_mitigation = TAA_MITIGATION_OFF;
 346                 return;
 347         }
 348
 349         /*
 350          * TAA mitigation via VERW is turned off if both
 351          * tsx_async_abort=off and mds=off are specified.
 352          */
 353         if (taa_mitigation == TAA_MITIGATION_OFF &&
 354             mds_mitigation == MDS_MITIGATION_OFF)
 355                 return;
 356
 357         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 358                 taa_mitigation = TAA_MITIGATION_VERW;
 359         else
 360                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 361
 362         /*
 363          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 364          * A microcode update fixes this behavior to clear CPU buffers. It also
 365          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 366          * ARCH_CAP_TSX_CTRL_MSR bit.
 367          *
 368          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 369          * update is required.
 370          */
 371         ia32_cap = x86_read_arch_cap_msr();
 372         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 373             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 374                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 375
 376         /*
 377          * TSX is enabled, select alternate mitigation for TAA which is
 378          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 379          *
 380          * For guests that can't determine whether the correct microcode is
 381          * present on host, enable the mitigation for UCODE_NEEDED as well.
 382          */
 383         static_branch_enable(&mds_user_clear);
 384
 385         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 386                 cpu_smt_disable(false);
 387 }
 388
 389 static int __init tsx_async_abort_parse_cmdline(char *str)
 390 {
 391         if (!boot_cpu_has_bug(X86_BUG_TAA))
 392                 return 0;
 393
 394         if (!str)
 395                 return -EINVAL;
 396
 397         if (!strcmp(str, "off")) {
 398                 taa_mitigation = TAA_MITIGATION_OFF;
 399         } else if (!strcmp(str, "full")) {
 400                 taa_mitigation = TAA_MITIGATION_VERW;
 401         } else if (!strcmp(str, "full,nosmt")) {
 402                 taa_mitigation = TAA_MITIGATION_VERW;
 403                 taa_nosmt = true;
 404         }
 405
 406         return 0;
 407 }
 408 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 409
 410 #undef pr_fmt
 411 #define pr_fmt(fmt)     "MMIO Stale Data: " fmt
 412
 413 enum mmio_mitigations {
 414         MMIO_MITIGATION_OFF,
 415         MMIO_MITIGATION_UCODE_NEEDED,
 416         MMIO_MITIGATION_VERW,
 417 };
 418
 419 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
 420 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
 421 static bool mmio_nosmt __ro_after_init = false;
 422
 423 static const char * const mmio_strings[] = {
 424         [MMIO_MITIGATION_OFF]           = "Vulnerable",
 425         [MMIO_MITIGATION_UCODE_NEEDED]  = "Vulnerable: Clear CPU buffers attempted, no microcode",
 426         [MMIO_MITIGATION_VERW]          = "Mitigation: Clear CPU buffers",
 427 };
 428
 429 static void __init mmio_select_mitigation(void)
 430 {
 431         u64 ia32_cap;
 432
 433         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
 434              boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
 435              cpu_mitigations_off()) {
 436                 mmio_mitigation = MMIO_MITIGATION_OFF;
 437                 return;
 438         }
 439
 440         if (mmio_mitigation == MMIO_MITIGATION_OFF)
 441                 return;
 442
 443         ia32_cap = x86_read_arch_cap_msr();
 444
 445         /*
 446          * Enable CPU buffer clear mitigation for host and VMM, if also affected
 447          * by MDS or TAA. Otherwise, enable mitigation for VMM only.
 448          */
 449         if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
 450                                               boot_cpu_has(X86_FEATURE_RTM)))
 451                 static_branch_enable(&mds_user_clear);
 452         else
 453                 static_branch_enable(&mmio_stale_data_clear);
 454
 455         /*
 456          * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
 457          * be propagated to uncore buffers, clearing the Fill buffers on idle
 458          * is required irrespective of SMT state.
 459          */
 460         if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
 461                 static_branch_enable(&mds_idle_clear);
 462
 463         /*
 464          * Check if the system has the right microcode.
 465          *
 466          * CPU Fill buffer clear mitigation is enumerated by either an explicit
 467          * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
 468          * affected systems.
 469          */
 470         if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
 471             (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
 472              boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
 473              !(ia32_cap & ARCH_CAP_MDS_NO)))
 474                 mmio_mitigation = MMIO_MITIGATION_VERW;
 475         else
 476                 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
 477
 478         if (mmio_nosmt || cpu_mitigations_auto_nosmt())
 479                 cpu_smt_disable(false);
 480 }
 481
 482 static int __init mmio_stale_data_parse_cmdline(char *str)
 483 {
 484         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 485                 return 0;
 486
 487         if (!str)
 488                 return -EINVAL;
 489
 490         if (!strcmp(str, "off")) {
 491                 mmio_mitigation = MMIO_MITIGATION_OFF;
 492         } else if (!strcmp(str, "full")) {
 493                 mmio_mitigation = MMIO_MITIGATION_VERW;
 494         } else if (!strcmp(str, "full,nosmt")) {
 495                 mmio_mitigation = MMIO_MITIGATION_VERW;
 496                 mmio_nosmt = true;
 497         }
 498
 499         return 0;
 500 }
 501 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
 502
 503 #undef pr_fmt
 504 #define pr_fmt(fmt)     "" fmt
 505
 506 static void __init md_clear_update_mitigation(void)
 507 {
 508         if (cpu_mitigations_off())
 509                 return;
 510
 511         if (!static_key_enabled(&mds_user_clear))
 512                 goto out;
 513
 514         /*
 515          * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
 516          * mitigation, if necessary.
 517          */
 518         if (mds_mitigation == MDS_MITIGATION_OFF &&
 519             boot_cpu_has_bug(X86_BUG_MDS)) {
 520                 mds_mitigation = MDS_MITIGATION_FULL;
 521                 mds_select_mitigation();
 522         }
 523         if (taa_mitigation == TAA_MITIGATION_OFF &&
 524             boot_cpu_has_bug(X86_BUG_TAA)) {
 525                 taa_mitigation = TAA_MITIGATION_VERW;
 526                 taa_select_mitigation();
 527         }
 528         if (mmio_mitigation == MMIO_MITIGATION_OFF &&
 529             boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
 530                 mmio_mitigation = MMIO_MITIGATION_VERW;
 531                 mmio_select_mitigation();
 532         }
 533 out:
 534         if (boot_cpu_has_bug(X86_BUG_MDS))
 535                 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
 536         if (boot_cpu_has_bug(X86_BUG_TAA))
 537                 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
 538         if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 539                 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
 540         else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
 541                 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
 542 }
 543
 544 static void __init md_clear_select_mitigation(void)
 545 {
 546         mds_select_mitigation();
 547         taa_select_mitigation();
 548         mmio_select_mitigation();
 549
 550         /*
 551          * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
 552          * and print their mitigation after MDS, TAA and MMIO Stale Data
 553          * mitigation selection is done.
 554          */
 555         md_clear_update_mitigation();
 556 }
 557
 558 #undef pr_fmt
 559 #define pr_fmt(fmt)     "SRBDS: " fmt
 560
 561 enum srbds_mitigations {
 562         SRBDS_MITIGATION_OFF,
 563         SRBDS_MITIGATION_UCODE_NEEDED,
 564         SRBDS_MITIGATION_FULL,
 565         SRBDS_MITIGATION_TSX_OFF,
 566         SRBDS_MITIGATION_HYPERVISOR,
 567 };
 568
 569 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 570
 571 static const char * const srbds_strings[] = {
 572         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 573         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 574         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 575         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 576         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 577 };
 578
 579 static bool srbds_off;
 580
 581 void update_srbds_msr(void)
 582 {
 583         u64 mcu_ctrl;
 584
 585         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 586                 return;
 587
 588         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 589                 return;
 590
 591         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 592                 return;
 593
 594         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 595
 596         switch (srbds_mitigation) {
 597         case SRBDS_MITIGATION_OFF:
 598         case SRBDS_MITIGATION_TSX_OFF:
 599                 mcu_ctrl |= RNGDS_MITG_DIS;
 600                 break;
 601         case SRBDS_MITIGATION_FULL:
 602                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 603                 break;
 604         default:
 605                 break;
 606         }
 607
 608         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 609 }
 610
 611 static void __init srbds_select_mitigation(void)
 612 {
 613         u64 ia32_cap;
 614
 615         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 616                 return;
 617
 618         /*
 619          * Check to see if this is one of the MDS_NO systems supporting TSX that
 620          * are only exposed to SRBDS when TSX is enabled or when CPU is affected
 621          * by Processor MMIO Stale Data vulnerability.
 622          */
 623         ia32_cap = x86_read_arch_cap_msr();
 624         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
 625             !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 626                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 627         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 628                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 629         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 630                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 631         else if (cpu_mitigations_off() || srbds_off)
 632                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 633
 634         update_srbds_msr();
 635         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 636 }
 637
 638 static int __init srbds_parse_cmdline(char *str)
 639 {
 640         if (!str)
 641                 return -EINVAL;
 642
 643         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 644                 return 0;
 645
 646         srbds_off = !strcmp(str, "off");
 647         return 0;
 648 }
 649 early_param("srbds", srbds_parse_cmdline);
 650
 651 #undef pr_fmt
 652 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 653
 654 enum spectre_v1_mitigation {
 655         SPECTRE_V1_MITIGATION_NONE,
 656         SPECTRE_V1_MITIGATION_AUTO,
 657 };
 658
 659 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 660         SPECTRE_V1_MITIGATION_AUTO;
 661
 662 static const char * const spectre_v1_strings[] = {
 663         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 664         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 665 };
 666
 667 /*
 668  * Does SMAP provide full mitigation against speculative kernel access to
 669  * userspace?
 670  */
 671 static bool smap_works_speculatively(void)
 672 {
 673         if (!boot_cpu_has(X86_FEATURE_SMAP))
 674                 return false;
 675
 676         /*
 677          * On CPUs which are vulnerable to Meltdown, SMAP does not
 678          * prevent speculative access to user data in the L1 cache.
 679          * Consider SMAP to be non-functional as a mitigation on these
 680          * CPUs.
 681          */
 682         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 683                 return false;
 684
 685         return true;
 686 }
 687
 688 static void __init spectre_v1_select_mitigation(void)
 689 {
 690         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 691                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 692                 return;
 693         }
 694
 695         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 696                 /*
 697                  * With Spectre v1, a user can speculatively control either
 698                  * path of a conditional swapgs with a user-controlled GS
 699                  * value.  The mitigation is to add lfences to both code paths.
 700                  *
 701                  * If FSGSBASE is enabled, the user can put a kernel address in
 702                  * GS, in which case SMAP provides no protection.
 703                  *
 704                  * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
 705                  *         FSGSBASE enablement patches have been merged. ]
 706                  *
 707                  * If FSGSBASE is disabled, the user can only put a user space
 708                  * address in GS.  That makes an attack harder, but still
 709                  * possible if there's no SMAP protection.
 710                  */
 711                 if (!smap_works_speculatively()) {
 712                         /*
 713                          * Mitigation can be provided from SWAPGS itself or
 714                          * PTI as the CR3 write in the Meltdown mitigation
 715                          * is serializing.
 716                          *
 717                          * If neither is there, mitigate with an LFENCE to
 718                          * stop speculation through swapgs.
 719                          */
 720                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 721                             !boot_cpu_has(X86_FEATURE_PTI))
 722                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 723
 724                         /*
 725                          * Enable lfences in the kernel entry (non-swapgs)
 726                          * paths, to prevent user entry from speculatively
 727                          * skipping swapgs.
 728                          */
 729                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 730                 }
 731         }
 732
 733         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 734 }
 735
 736 static int __init nospectre_v1_cmdline(char *str)
 737 {
 738         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 739         return 0;
 740 }
 741 early_param("nospectre_v1", nospectre_v1_cmdline);
 742
 743 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 744         SPECTRE_V2_NONE;
 745
 746 #undef pr_fmt
 747 #define pr_fmt(fmt)     "RETBleed: " fmt
 748
 749 enum retbleed_mitigation {
 750         RETBLEED_MITIGATION_NONE,
 751         RETBLEED_MITIGATION_IBRS,
 752         RETBLEED_MITIGATION_EIBRS,
 753 };
 754
 755 enum retbleed_mitigation_cmd {
 756         RETBLEED_CMD_OFF,
 757         RETBLEED_CMD_AUTO
 758 };
 759
 760 const char * const retbleed_strings[] = {
 761         [RETBLEED_MITIGATION_NONE]      = "Vulnerable",
 762         [RETBLEED_MITIGATION_IBRS]      = "Mitigation: IBRS",
 763         [RETBLEED_MITIGATION_EIBRS]     = "Mitigation: Enhanced IBRS",
 764 };
 765
 766 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
 767         RETBLEED_MITIGATION_NONE;
 768 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
 769         RETBLEED_CMD_AUTO;
 770
 771 static int __init retbleed_parse_cmdline(char *str)
 772 {
 773         if (!str)
 774                 return -EINVAL;
 775
 776         if (!strcmp(str, "off"))
 777                 retbleed_cmd = RETBLEED_CMD_OFF;
 778         else if (!strcmp(str, "auto"))
 779                 retbleed_cmd = RETBLEED_CMD_AUTO;
 780         else
 781                 pr_err("Unknown retbleed option (%s). Defaulting to 'auto'\n", str);
 782
 783         return 0;
 784 }
 785 early_param("retbleed", retbleed_parse_cmdline);
 786
 787 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
 788
 789 static void __init retbleed_select_mitigation(void)
 790 {
 791         if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
 792                 return;
 793
 794         switch (retbleed_cmd) {
 795         case RETBLEED_CMD_OFF:
 796                 return;
 797
 798         case RETBLEED_CMD_AUTO:
 799         default:
 800                 /*
 801                  * The Intel mitigation (IBRS) was already selected in
 802                  * spectre_v2_select_mitigation().
 803                  */
 804
 805                 break;
 806         }
 807
 808         switch (retbleed_mitigation) {
 809         default:
 810                 break;
 811         }
 812
 813         /*
 814          * Let IBRS trump all on Intel without affecting the effects of the
 815          * retbleed= cmdline option.
 816          */
 817         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
 818                 switch (spectre_v2_enabled) {
 819                 case SPECTRE_V2_IBRS:
 820                         retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
 821                         break;
 822                 case SPECTRE_V2_EIBRS:
 823                 case SPECTRE_V2_EIBRS_RETPOLINE:
 824                 case SPECTRE_V2_EIBRS_LFENCE:
 825                         retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
 826                         break;
 827                 default:
 828                         pr_err(RETBLEED_INTEL_MSG);
 829                 }
 830         }
 831
 832         pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
 833 }
 834
 835 #undef pr_fmt
 836 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 837
 838 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
 839         SPECTRE_V2_USER_NONE;
 840 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
 841         SPECTRE_V2_USER_NONE;
 842
 843 #ifdef CONFIG_RETPOLINE
 844 static bool spectre_v2_bad_module;
 845
 846 bool retpoline_module_ok(bool has_retpoline)
 847 {
 848         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 849                 return true;
 850
 851         pr_err("System may be vulnerable to spectre v2\n");
 852         spectre_v2_bad_module = true;
 853         return false;
 854 }
 855
 856 static inline const char *spectre_v2_module_string(void)
 857 {
 858         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 859 }
 860 #else
 861 static inline const char *spectre_v2_module_string(void) { return ""; }
 862 #endif
 863
 864 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
 865 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
 866 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
 867 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
 868
 869 #ifdef CONFIG_BPF_SYSCALL
 870 void unpriv_ebpf_notify(int new_state)
 871 {
 872         if (new_state)
 873                 return;
 874
 875         /* Unprivileged eBPF is enabled */
 876
 877         switch (spectre_v2_enabled) {
 878         case SPECTRE_V2_EIBRS:
 879                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
 880                 break;
 881         case SPECTRE_V2_EIBRS_LFENCE:
 882                 if (sched_smt_active())
 883                         pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
 884                 break;
 885         default:
 886                 break;
 887         }
 888 }
 889 #endif
 890
 891 static inline bool match_option(const char *arg, int arglen, const char *opt)
 892 {
 893         int len = strlen(opt);
 894
 895         return len == arglen && !strncmp(arg, opt, len);
 896 }
 897
 898 /* The kernel command line selection for spectre v2 */
 899 enum spectre_v2_mitigation_cmd {
 900         SPECTRE_V2_CMD_NONE,
 901         SPECTRE_V2_CMD_AUTO,
 902         SPECTRE_V2_CMD_FORCE,
 903         SPECTRE_V2_CMD_RETPOLINE,
 904         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 905         SPECTRE_V2_CMD_RETPOLINE_LFENCE,
 906         SPECTRE_V2_CMD_EIBRS,
 907         SPECTRE_V2_CMD_EIBRS_RETPOLINE,
 908         SPECTRE_V2_CMD_EIBRS_LFENCE,
 909         SPECTRE_V2_CMD_IBRS,
 910 };
 911
 912 enum spectre_v2_user_cmd {
 913         SPECTRE_V2_USER_CMD_NONE,
 914         SPECTRE_V2_USER_CMD_AUTO,
 915         SPECTRE_V2_USER_CMD_FORCE,
 916         SPECTRE_V2_USER_CMD_PRCTL,
 917         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 918         SPECTRE_V2_USER_CMD_SECCOMP,
 919         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 920 };
 921
 922 static const char * const spectre_v2_user_strings[] = {
 923         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
 924         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
 925         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
 926         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
 927         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
 928 };
 929
 930 static const struct {
 931         const char                      *option;
 932         enum spectre_v2_user_cmd        cmd;
 933         bool                            secure;
 934 } v2_user_options[] __initconst = {
 935         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 936         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 937         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 938         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 939         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 940         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 941         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 942 };
 943
 944 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 945 {
 946         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 947                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 948 }
 949
 950 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
 951
 952 static enum spectre_v2_user_cmd __init
 953 spectre_v2_parse_user_cmdline(void)
 954 {
 955         char arg[20];
 956         int ret, i;
 957
 958         switch (spectre_v2_cmd) {
 959         case SPECTRE_V2_CMD_NONE:
 960                 return SPECTRE_V2_USER_CMD_NONE;
 961         case SPECTRE_V2_CMD_FORCE:
 962                 return SPECTRE_V2_USER_CMD_FORCE;
 963         default:
 964                 break;
 965         }
 966
 967         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 968                                   arg, sizeof(arg));
 969         if (ret < 0)
 970                 return SPECTRE_V2_USER_CMD_AUTO;
 971
 972         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 973                 if (match_option(arg, ret, v2_user_options[i].option)) {
 974                         spec_v2_user_print_cond(v2_user_options[i].option,
 975                                                 v2_user_options[i].secure);
 976                         return v2_user_options[i].cmd;
 977                 }
 978         }
 979
 980         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 981         return SPECTRE_V2_USER_CMD_AUTO;
 982 }
 983
 984 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
 985 {
 986         return mode == SPECTRE_V2_EIBRS ||
 987                mode == SPECTRE_V2_EIBRS_RETPOLINE ||
 988                mode == SPECTRE_V2_EIBRS_LFENCE;
 989 }
 990
 991 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
 992 {
 993         return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
 994 }
 995
 996 static void __init
 997 spectre_v2_user_select_mitigation(void)
 998 {
 999         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1000         bool smt_possible = IS_ENABLED(CONFIG_SMP);
1001         enum spectre_v2_user_cmd cmd;
1002
1003         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1004                 return;
1005
1006         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1007             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1008                 smt_possible = false;
1009
1010         cmd = spectre_v2_parse_user_cmdline();
1011         switch (cmd) {
1012         case SPECTRE_V2_USER_CMD_NONE:
1013                 goto set_mode;
1014         case SPECTRE_V2_USER_CMD_FORCE:
1015                 mode = SPECTRE_V2_USER_STRICT;
1016                 break;
1017         case SPECTRE_V2_USER_CMD_PRCTL:
1018         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1019                 mode = SPECTRE_V2_USER_PRCTL;
1020                 break;
1021         case SPECTRE_V2_USER_CMD_AUTO:
1022         case SPECTRE_V2_USER_CMD_SECCOMP:
1023         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1024                 if (IS_ENABLED(CONFIG_SECCOMP))
1025                         mode = SPECTRE_V2_USER_SECCOMP;
1026                 else
1027                         mode = SPECTRE_V2_USER_PRCTL;
1028                 break;
1029         }
1030
1031         /* Initialize Indirect Branch Prediction Barrier */
1032         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1033                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1034
1035                 spectre_v2_user_ibpb = mode;
1036                 switch (cmd) {
1037                 case SPECTRE_V2_USER_CMD_FORCE:
1038                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1039                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1040                         static_branch_enable(&switch_mm_always_ibpb);
1041                         spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1042                         break;
1043                 case SPECTRE_V2_USER_CMD_PRCTL:
1044                 case SPECTRE_V2_USER_CMD_AUTO:
1045                 case SPECTRE_V2_USER_CMD_SECCOMP:
1046                         static_branch_enable(&switch_mm_cond_ibpb);
1047                         break;
1048                 default:
1049                         break;
1050                 }
1051
1052                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1053                         static_key_enabled(&switch_mm_always_ibpb) ?
1054                         "always-on" : "conditional");
1055         }
1056
1057         /*
1058          * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
1059          * is not required.
1060          *
1061          * Enhanced IBRS also protects against cross-thread branch target
1062          * injection in user-mode as the IBRS bit remains always set which
1063          * implicitly enables cross-thread protections.  However, in legacy IBRS
1064          * mode, the IBRS bit is set only on kernel entry and cleared on return
1065          * to userspace. This disables the implicit cross-thread protection,
1066          * so allow for STIBP to be selected in that case.
1067          */
1068         if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1069             !smt_possible ||
1070             spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1071                 return;
1072
1073         /*
1074          * At this point, an STIBP mode other than "off" has been set.
1075          * If STIBP support is not being forced, check if STIBP always-on
1076          * is preferred.
1077          */
1078         if (mode != SPECTRE_V2_USER_STRICT &&
1079             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1080                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1081
1082         spectre_v2_user_stibp = mode;
1083
1084 set_mode:
1085         pr_info("%s\n", spectre_v2_user_strings[mode]);
1086 }
1087
1088 static const char * const spectre_v2_strings[] = {
1089         [SPECTRE_V2_NONE]                       = "Vulnerable",
1090         [SPECTRE_V2_RETPOLINE]                  = "Mitigation: Retpolines",
1091         [SPECTRE_V2_LFENCE]                     = "Mitigation: LFENCE",
1092         [SPECTRE_V2_EIBRS]                      = "Mitigation: Enhanced IBRS",
1093         [SPECTRE_V2_EIBRS_LFENCE]               = "Mitigation: Enhanced IBRS + LFENCE",
1094         [SPECTRE_V2_EIBRS_RETPOLINE]            = "Mitigation: Enhanced IBRS + Retpolines",
1095         [SPECTRE_V2_IBRS]                       = "Mitigation: IBRS",
1096 };
1097
1098 static const struct {
1099         const char *option;
1100         enum spectre_v2_mitigation_cmd cmd;
1101         bool secure;
1102 } mitigation_options[] __initconst = {
1103         { "off",                SPECTRE_V2_CMD_NONE,              false },
1104         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
1105         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
1106         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1107         { "retpoline,lfence",   SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1108         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1109         { "eibrs",              SPECTRE_V2_CMD_EIBRS,             false },
1110         { "eibrs,lfence",       SPECTRE_V2_CMD_EIBRS_LFENCE,      false },
1111         { "eibrs,retpoline",    SPECTRE_V2_CMD_EIBRS_RETPOLINE,   false },
1112         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
1113         { "ibrs",               SPECTRE_V2_CMD_IBRS,              false },
1114 };
1115
1116 static void __init spec_v2_print_cond(const char *reason, bool secure)
1117 {
1118         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1119                 pr_info("%s selected on command line.\n", reason);
1120 }
1121
1122 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1123 {
1124         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1125         char arg[20];
1126         int ret, i;
1127
1128         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1129             cpu_mitigations_off())
1130                 return SPECTRE_V2_CMD_NONE;
1131
1132         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1133         if (ret < 0)
1134                 return SPECTRE_V2_CMD_AUTO;
1135
1136         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1137                 if (!match_option(arg, ret, mitigation_options[i].option))
1138                         continue;
1139                 cmd = mitigation_options[i].cmd;
1140                 break;
1141         }
1142
1143         if (i >= ARRAY_SIZE(mitigation_options)) {
1144                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1145                 return SPECTRE_V2_CMD_AUTO;
1146         }
1147
1148         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1149              cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1150              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1151              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1152              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1153             !IS_ENABLED(CONFIG_RETPOLINE)) {
1154                 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1155                        mitigation_options[i].option);
1156                 return SPECTRE_V2_CMD_AUTO;
1157         }
1158
1159         if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1160              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1161              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1162             !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1163                 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1164                        mitigation_options[i].option);
1165                 return SPECTRE_V2_CMD_AUTO;
1166         }
1167
1168         if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1169              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1170             !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1171                 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1172                        mitigation_options[i].option);
1173                 return SPECTRE_V2_CMD_AUTO;
1174         }
1175
1176         if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1177                 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1178                        mitigation_options[i].option);
1179                 return SPECTRE_V2_CMD_AUTO;
1180         }
1181
1182         if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1183                 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1184                        mitigation_options[i].option);
1185                 return SPECTRE_V2_CMD_AUTO;
1186         }
1187
1188         if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1189                 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1190                        mitigation_options[i].option);
1191                 return SPECTRE_V2_CMD_AUTO;
1192         }
1193
1194         spec_v2_print_cond(mitigation_options[i].option,
1195                            mitigation_options[i].secure);
1196         return cmd;
1197 }
1198
1199 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1200 {
1201         if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1202                 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1203                 return SPECTRE_V2_NONE;
1204         }
1205
1206         return SPECTRE_V2_RETPOLINE;
1207 }
1208
1209 /* Disable in-kernel use of non-RSB RET predictors */
1210 static void __init spec_ctrl_disable_kernel_rrsba(void)
1211 {
1212         u64 ia32_cap;
1213
1214         if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1215                 return;
1216
1217         ia32_cap = x86_read_arch_cap_msr();
1218
1219         if (ia32_cap & ARCH_CAP_RRSBA) {
1220                 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1221                 update_spec_ctrl(x86_spec_ctrl_base);
1222         }
1223 }
1224
1225 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1226 {
1227         /*
1228          * Similar to context switches, there are two types of RSB attacks
1229          * after VM exit:
1230          *
1231          * 1) RSB underflow
1232          *
1233          * 2) Poisoned RSB entry
1234          *
1235          * When retpoline is enabled, both are mitigated by filling/clearing
1236          * the RSB.
1237          *
1238          * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1239          * prediction isolation protections, RSB still needs to be cleared
1240          * because of #2.  Note that SMEP provides no protection here, unlike
1241          * user-space-poisoned RSB entries.
1242          *
1243          * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1244          * bug is present then a LITE version of RSB protection is required,
1245          * just a single call needs to retire before a RET is executed.
1246          */
1247         switch (mode) {
1248         case SPECTRE_V2_NONE:
1249                 return;
1250
1251         case SPECTRE_V2_EIBRS_LFENCE:
1252         case SPECTRE_V2_EIBRS:
1253                 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB) &&
1254                     (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)) {
1255                         setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1256                         pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1257                 }
1258                 return;
1259
1260         case SPECTRE_V2_EIBRS_RETPOLINE:
1261         case SPECTRE_V2_RETPOLINE:
1262         case SPECTRE_V2_LFENCE:
1263         case SPECTRE_V2_IBRS:
1264                 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1265                 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1266                 return;
1267         }
1268
1269         pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1270         dump_stack();
1271 }
1272
1273 static void __init spectre_v2_select_mitigation(void)
1274 {
1275         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1276         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1277
1278         /*
1279          * If the CPU is not affected and the command line mode is NONE or AUTO
1280          * then nothing to do.
1281          */
1282         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1283             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1284                 return;
1285
1286         switch (cmd) {
1287         case SPECTRE_V2_CMD_NONE:
1288                 return;
1289
1290         case SPECTRE_V2_CMD_FORCE:
1291         case SPECTRE_V2_CMD_AUTO:
1292                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1293                         mode = SPECTRE_V2_EIBRS;
1294                         break;
1295                 }
1296
1297                 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1298                     retbleed_cmd != RETBLEED_CMD_OFF &&
1299                     boot_cpu_has(X86_FEATURE_IBRS) &&
1300                     boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1301                         mode = SPECTRE_V2_IBRS;
1302                         break;
1303                 }
1304
1305                 mode = spectre_v2_select_retpoline();
1306                 break;
1307
1308         case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1309                 pr_err(SPECTRE_V2_LFENCE_MSG);
1310                 mode = SPECTRE_V2_LFENCE;
1311                 break;
1312
1313         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1314                 mode = SPECTRE_V2_RETPOLINE;
1315                 break;
1316
1317         case SPECTRE_V2_CMD_RETPOLINE:
1318                 mode = spectre_v2_select_retpoline();
1319                 break;
1320
1321         case SPECTRE_V2_CMD_IBRS:
1322                 mode = SPECTRE_V2_IBRS;
1323                 break;
1324
1325         case SPECTRE_V2_CMD_EIBRS:
1326                 mode = SPECTRE_V2_EIBRS;
1327                 break;
1328
1329         case SPECTRE_V2_CMD_EIBRS_LFENCE:
1330                 mode = SPECTRE_V2_EIBRS_LFENCE;
1331                 break;
1332
1333         case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1334                 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1335                 break;
1336         }
1337
1338         if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1339                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1340
1341         if (spectre_v2_in_ibrs_mode(mode)) {
1342                 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1343                 update_spec_ctrl(x86_spec_ctrl_base);
1344         }
1345
1346         switch (mode) {
1347         case SPECTRE_V2_NONE:
1348         case SPECTRE_V2_EIBRS:
1349                 break;
1350
1351         case SPECTRE_V2_IBRS:
1352                 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1353                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1354                         pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1355                 break;
1356
1357         case SPECTRE_V2_LFENCE:
1358         case SPECTRE_V2_EIBRS_LFENCE:
1359                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1360                 /* fallthrough */
1361
1362         case SPECTRE_V2_RETPOLINE:
1363         case SPECTRE_V2_EIBRS_RETPOLINE:
1364                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1365                 break;
1366         }
1367
1368         /*
1369          * Disable alternate RSB predictions in kernel when indirect CALLs and
1370          * JMPs gets protection against BHI and Intramode-BTI, but RET
1371          * prediction from a non-RSB predictor is still a risk.
1372          */
1373         if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1374             mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1375             mode == SPECTRE_V2_RETPOLINE)
1376                 spec_ctrl_disable_kernel_rrsba();
1377
1378         spectre_v2_enabled = mode;
1379         pr_info("%s\n", spectre_v2_strings[mode]);
1380
1381         /*
1382          * If Spectre v2 protection has been enabled, fill the RSB during a
1383          * context switch.  In general there are two types of RSB attacks
1384          * across context switches, for which the CALLs/RETs may be unbalanced.
1385          *
1386          * 1) RSB underflow
1387          *
1388          *    Some Intel parts have "bottomless RSB".  When the RSB is empty,
1389          *    speculated return targets may come from the branch predictor,
1390          *    which could have a user-poisoned BTB or BHB entry.
1391          *
1392          *    AMD has it even worse: *all* returns are speculated from the BTB,
1393          *    regardless of the state of the RSB.
1394          *
1395          *    When IBRS or eIBRS is enabled, the "user -> kernel" attack
1396          *    scenario is mitigated by the IBRS branch prediction isolation
1397          *    properties, so the RSB buffer filling wouldn't be necessary to
1398          *    protect against this type of attack.
1399          *
1400          *    The "user -> user" attack scenario is mitigated by RSB filling.
1401          *
1402          * 2) Poisoned RSB entry
1403          *
1404          *    If the 'next' in-kernel return stack is shorter than 'prev',
1405          *    'next' could be tricked into speculating with a user-poisoned RSB
1406          *    entry.
1407          *
1408          *    The "user -> kernel" attack scenario is mitigated by SMEP and
1409          *    eIBRS.
1410          *
1411          *    The "user -> user" scenario, also known as SpectreBHB, requires
1412          *    RSB clearing.
1413          *
1414          * So to mitigate all cases, unconditionally fill RSB on context
1415          * switches.
1416          *
1417          * FIXME: Is this pointless for retbleed-affected AMD?
1418          */
1419         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1420         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1421
1422         spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1423
1424         /*
1425          * Retpoline protects the kernel, but doesn't protect firmware.  IBRS
1426          * and Enhanced IBRS protect firmware too, so enable IBRS around
1427          * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1428          * enabled.
1429          *
1430          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1431          * the user might select retpoline on the kernel command line and if
1432          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1433          * enable IBRS around firmware calls.
1434          */
1435         if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1436                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1437                 pr_info("Enabling Restricted Speculation for firmware calls\n");
1438         }
1439
1440         /* Set up IBPB and STIBP depending on the general spectre V2 command */
1441         spectre_v2_cmd = cmd;
1442 }
1443
1444 static void update_stibp_msr(void * __unused)
1445 {
1446         u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1447         update_spec_ctrl(val);
1448 }
1449
1450 /* Update x86_spec_ctrl_base in case SMT state changed. */
1451 static void update_stibp_strict(void)
1452 {
1453         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1454
1455         if (sched_smt_active())
1456                 mask |= SPEC_CTRL_STIBP;
1457
1458         if (mask == x86_spec_ctrl_base)
1459                 return;
1460
1461         pr_info("Update user space SMT mitigation: STIBP %s\n",
1462                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1463         x86_spec_ctrl_base = mask;
1464         on_each_cpu(update_stibp_msr, NULL, 1);
1465 }
1466
1467 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1468 static void update_indir_branch_cond(void)
1469 {
1470         if (sched_smt_active())
1471                 static_branch_enable(&switch_to_cond_stibp);
1472         else
1473                 static_branch_disable(&switch_to_cond_stibp);
1474 }
1475
1476 #undef pr_fmt
1477 #define pr_fmt(fmt) fmt
1478
1479 /* Update the static key controlling the MDS CPU buffer clear in idle */
1480 static void update_mds_branch_idle(void)
1481 {
1482         u64 ia32_cap = x86_read_arch_cap_msr();
1483
1484         /*
1485          * Enable the idle clearing if SMT is active on CPUs which are
1486          * affected only by MSBDS and not any other MDS variant.
1487          *
1488          * The other variants cannot be mitigated when SMT is enabled, so
1489          * clearing the buffers on idle just to prevent the Store Buffer
1490          * repartitioning leak would be a window dressing exercise.
1491          */
1492         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1493                 return;
1494
1495         if (sched_smt_active()) {
1496                 static_branch_enable(&mds_idle_clear);
1497         } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1498                    (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1499                 static_branch_disable(&mds_idle_clear);
1500         }
1501 }
1502
1503 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1504 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1505 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1506
1507 void arch_smt_update(void)
1508 {
1509         mutex_lock(&spec_ctrl_mutex);
1510
1511         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1512             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1513                 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1514
1515         switch (spectre_v2_user_stibp) {
1516         case SPECTRE_V2_USER_NONE:
1517                 break;
1518         case SPECTRE_V2_USER_STRICT:
1519         case SPECTRE_V2_USER_STRICT_PREFERRED:
1520                 update_stibp_strict();
1521                 break;
1522         case SPECTRE_V2_USER_PRCTL:
1523         case SPECTRE_V2_USER_SECCOMP:
1524                 update_indir_branch_cond();
1525                 break;
1526         }
1527
1528         switch (mds_mitigation) {
1529         case MDS_MITIGATION_FULL:
1530         case MDS_MITIGATION_VMWERV:
1531                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1532                         pr_warn_once(MDS_MSG_SMT);
1533                 update_mds_branch_idle();
1534                 break;
1535         case MDS_MITIGATION_OFF:
1536                 break;
1537         }
1538
1539         switch (taa_mitigation) {
1540         case TAA_MITIGATION_VERW:
1541         case TAA_MITIGATION_UCODE_NEEDED:
1542                 if (sched_smt_active())
1543                         pr_warn_once(TAA_MSG_SMT);
1544                 break;
1545         case TAA_MITIGATION_TSX_DISABLED:
1546         case TAA_MITIGATION_OFF:
1547                 break;
1548         }
1549
1550         switch (mmio_mitigation) {
1551         case MMIO_MITIGATION_VERW:
1552         case MMIO_MITIGATION_UCODE_NEEDED:
1553                 if (sched_smt_active())
1554                         pr_warn_once(MMIO_MSG_SMT);
1555                 break;
1556         case MMIO_MITIGATION_OFF:
1557                 break;
1558         }
1559
1560         mutex_unlock(&spec_ctrl_mutex);
1561 }
1562
1563 #undef pr_fmt
1564 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1565
1566 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1567
1568 /* The kernel command line selection */
1569 enum ssb_mitigation_cmd {
1570         SPEC_STORE_BYPASS_CMD_NONE,
1571         SPEC_STORE_BYPASS_CMD_AUTO,
1572         SPEC_STORE_BYPASS_CMD_ON,
1573         SPEC_STORE_BYPASS_CMD_PRCTL,
1574         SPEC_STORE_BYPASS_CMD_SECCOMP,
1575 };
1576
1577 static const char * const ssb_strings[] = {
1578         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1579         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1580         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1581         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1582 };
1583
1584 static const struct {
1585         const char *option;
1586         enum ssb_mitigation_cmd cmd;
1587 } ssb_mitigation_options[]  __initconst = {
1588         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1589         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1590         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1591         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1592         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1593 };
1594
1595 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1596 {
1597         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1598         char arg[20];
1599         int ret, i;
1600
1601         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1602             cpu_mitigations_off()) {
1603                 return SPEC_STORE_BYPASS_CMD_NONE;
1604         } else {
1605                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1606                                           arg, sizeof(arg));
1607                 if (ret < 0)
1608                         return SPEC_STORE_BYPASS_CMD_AUTO;
1609
1610                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1611                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1612                                 continue;
1613
1614                         cmd = ssb_mitigation_options[i].cmd;
1615                         break;
1616                 }
1617
1618                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1619                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1620                         return SPEC_STORE_BYPASS_CMD_AUTO;
1621                 }
1622         }
1623
1624         return cmd;
1625 }
1626
1627 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1628 {
1629         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1630         enum ssb_mitigation_cmd cmd;
1631
1632         if (!boot_cpu_has(X86_FEATURE_SSBD))
1633                 return mode;
1634
1635         cmd = ssb_parse_cmdline();
1636         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1637             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1638              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1639                 return mode;
1640
1641         switch (cmd) {
1642         case SPEC_STORE_BYPASS_CMD_AUTO:
1643         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1644                 /*
1645                  * Choose prctl+seccomp as the default mode if seccomp is
1646                  * enabled.
1647                  */
1648                 if (IS_ENABLED(CONFIG_SECCOMP))
1649                         mode = SPEC_STORE_BYPASS_SECCOMP;
1650                 else
1651                         mode = SPEC_STORE_BYPASS_PRCTL;
1652                 break;
1653         case SPEC_STORE_BYPASS_CMD_ON:
1654                 mode = SPEC_STORE_BYPASS_DISABLE;
1655                 break;
1656         case SPEC_STORE_BYPASS_CMD_PRCTL:
1657                 mode = SPEC_STORE_BYPASS_PRCTL;
1658                 break;
1659         case SPEC_STORE_BYPASS_CMD_NONE:
1660                 break;
1661         }
1662
1663         /*
1664          * We have three CPU feature flags that are in play here:
1665          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1666          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1667          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1668          */
1669         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1670                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1671                 /*
1672                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1673                  * use a completely different MSR and bit dependent on family.
1674                  */
1675                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1676                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1677                         x86_amd_ssb_disable();
1678                 } else {
1679                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1680                         update_spec_ctrl(x86_spec_ctrl_base);
1681                 }
1682         }
1683
1684         return mode;
1685 }
1686
1687 static void ssb_select_mitigation(void)
1688 {
1689         ssb_mode = __ssb_select_mitigation();
1690
1691         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1692                 pr_info("%s\n", ssb_strings[ssb_mode]);
1693 }
1694
1695 #undef pr_fmt
1696 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1697
1698 static void task_update_spec_tif(struct task_struct *tsk)
1699 {
1700         /* Force the update of the real TIF bits */
1701         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1702
1703         /*
1704          * Immediately update the speculation control MSRs for the current
1705          * task, but for a non-current task delay setting the CPU
1706          * mitigation until it is scheduled next.
1707          *
1708          * This can only happen for SECCOMP mitigation. For PRCTL it's
1709          * always the current task.
1710          */
1711         if (tsk == current)
1712                 speculation_ctrl_update_current();
1713 }
1714
1715 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1716 {
1717         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1718             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1719                 return -ENXIO;
1720
1721         switch (ctrl) {
1722         case PR_SPEC_ENABLE:
1723                 /* If speculation is force disabled, enable is not allowed */
1724                 if (task_spec_ssb_force_disable(task))
1725                         return -EPERM;
1726                 task_clear_spec_ssb_disable(task);
1727                 task_update_spec_tif(task);
1728                 break;
1729         case PR_SPEC_DISABLE:
1730                 task_set_spec_ssb_disable(task);
1731                 task_update_spec_tif(task);
1732                 break;
1733         case PR_SPEC_FORCE_DISABLE:
1734                 task_set_spec_ssb_disable(task);
1735                 task_set_spec_ssb_force_disable(task);
1736                 task_update_spec_tif(task);
1737                 break;
1738         default:
1739                 return -ERANGE;
1740         }
1741         return 0;
1742 }
1743
1744 static bool is_spec_ib_user_controlled(void)
1745 {
1746         return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1747                 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1748                 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1749                 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1750 }
1751
1752 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1753 {
1754         switch (ctrl) {
1755         case PR_SPEC_ENABLE:
1756                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1757                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1758                         return 0;
1759                 /*
1760                  * With strict mode for both IBPB and STIBP, the instruction
1761                  * code paths avoid checking this task flag and instead,
1762                  * unconditionally run the instruction. However, STIBP and IBPB
1763                  * are independent and either can be set to conditionally
1764                  * enabled regardless of the mode of the other.
1765                  *
1766                  * If either is set to conditional, allow the task flag to be
1767                  * updated, unless it was force-disabled by a previous prctl
1768                  * call. Currently, this is possible on an AMD CPU which has the
1769                  * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1770                  * kernel is booted with 'spectre_v2_user=seccomp', then
1771                  * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1772                  * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1773                  */
1774                 if (!is_spec_ib_user_controlled() ||
1775                     task_spec_ib_force_disable(task))
1776                         return -EPERM;
1777
1778                 task_clear_spec_ib_disable(task);
1779                 task_update_spec_tif(task);
1780                 break;
1781         case PR_SPEC_DISABLE:
1782         case PR_SPEC_FORCE_DISABLE:
1783                 /*
1784                  * Indirect branch speculation is always allowed when
1785                  * mitigation is force disabled.
1786                  */
1787                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1788                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1789                         return -EPERM;
1790
1791                 if (!is_spec_ib_user_controlled())
1792                         return 0;
1793
1794                 task_set_spec_ib_disable(task);
1795                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1796                         task_set_spec_ib_force_disable(task);
1797                 task_update_spec_tif(task);
1798                 if (task == current)
1799                         indirect_branch_prediction_barrier();
1800                 break;
1801         default:
1802                 return -ERANGE;
1803         }
1804         return 0;
1805 }
1806
1807 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1808                              unsigned long ctrl)
1809 {
1810         switch (which) {
1811         case PR_SPEC_STORE_BYPASS:
1812                 return ssb_prctl_set(task, ctrl);
1813         case PR_SPEC_INDIRECT_BRANCH:
1814                 return ib_prctl_set(task, ctrl);
1815         default:
1816                 return -ENODEV;
1817         }
1818 }
1819
1820 #ifdef CONFIG_SECCOMP
1821 void arch_seccomp_spec_mitigate(struct task_struct *task)
1822 {
1823         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1824                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1825         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1826             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1827                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1828 }
1829 #endif
1830
1831 static int ssb_prctl_get(struct task_struct *task)
1832 {
1833         switch (ssb_mode) {
1834         case SPEC_STORE_BYPASS_DISABLE:
1835                 return PR_SPEC_DISABLE;
1836         case SPEC_STORE_BYPASS_SECCOMP:
1837         case SPEC_STORE_BYPASS_PRCTL:
1838                 if (task_spec_ssb_force_disable(task))
1839                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1840                 if (task_spec_ssb_disable(task))
1841                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1842                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1843         default:
1844                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1845                         return PR_SPEC_ENABLE;
1846                 return PR_SPEC_NOT_AFFECTED;
1847         }
1848 }
1849
1850 static int ib_prctl_get(struct task_struct *task)
1851 {
1852         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1853                 return PR_SPEC_NOT_AFFECTED;
1854
1855         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1856             spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1857                 return PR_SPEC_ENABLE;
1858         else if (is_spec_ib_user_controlled()) {
1859                 if (task_spec_ib_force_disable(task))
1860                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1861                 if (task_spec_ib_disable(task))
1862                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1863                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1864         } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1865             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1866             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1867                 return PR_SPEC_DISABLE;
1868         else
1869                 return PR_SPEC_NOT_AFFECTED;
1870 }
1871
1872 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1873 {
1874         switch (which) {
1875         case PR_SPEC_STORE_BYPASS:
1876                 return ssb_prctl_get(task);
1877         case PR_SPEC_INDIRECT_BRANCH:
1878                 return ib_prctl_get(task);
1879         default:
1880                 return -ENODEV;
1881         }
1882 }
1883
1884 void x86_spec_ctrl_setup_ap(void)
1885 {
1886         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1887                 update_spec_ctrl(x86_spec_ctrl_base);
1888
1889         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1890                 x86_amd_ssb_disable();
1891 }
1892
1893 bool itlb_multihit_kvm_mitigation;
1894 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1895
1896 #undef pr_fmt
1897 #define pr_fmt(fmt)     "L1TF: " fmt
1898
1899 /* Default mitigation for L1TF-affected CPUs */
1900 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1901 #if IS_ENABLED(CONFIG_KVM_INTEL)
1902 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1903 #endif
1904 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1905 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1906
1907 /*
1908  * These CPUs all support 44bits physical address space internally in the
1909  * cache but CPUID can report a smaller number of physical address bits.
1910  *
1911  * The L1TF mitigation uses the top most address bit for the inversion of
1912  * non present PTEs. When the installed memory reaches into the top most
1913  * address bit due to memory holes, which has been observed on machines
1914  * which report 36bits physical address bits and have 32G RAM installed,
1915  * then the mitigation range check in l1tf_select_mitigation() triggers.
1916  * This is a false positive because the mitigation is still possible due to
1917  * the fact that the cache uses 44bit internally. Use the cache bits
1918  * instead of the reported physical bits and adjust them on the affected
1919  * machines to 44bit if the reported bits are less than 44.
1920  */
1921 static void override_cache_bits(struct cpuinfo_x86 *c)
1922 {
1923         if (c->x86 != 6)
1924                 return;
1925
1926         switch (c->x86_model) {
1927         case INTEL_FAM6_NEHALEM:
1928         case INTEL_FAM6_WESTMERE:
1929         case INTEL_FAM6_SANDYBRIDGE:
1930         case INTEL_FAM6_IVYBRIDGE:
1931         case INTEL_FAM6_HASWELL_CORE:
1932         case INTEL_FAM6_HASWELL_ULT:
1933         case INTEL_FAM6_HASWELL_GT3E:
1934         case INTEL_FAM6_BROADWELL_CORE:
1935         case INTEL_FAM6_BROADWELL_GT3E:
1936         case INTEL_FAM6_SKYLAKE_MOBILE:
1937         case INTEL_FAM6_SKYLAKE_DESKTOP:
1938         case INTEL_FAM6_KABYLAKE_MOBILE:
1939         case INTEL_FAM6_KABYLAKE_DESKTOP:
1940                 if (c->x86_cache_bits < 44)
1941                         c->x86_cache_bits = 44;
1942                 break;
1943         }
1944 }
1945
1946 static void __init l1tf_select_mitigation(void)
1947 {
1948         u64 half_pa;
1949
1950         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1951                 return;
1952
1953         if (cpu_mitigations_off())
1954                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1955         else if (cpu_mitigations_auto_nosmt())
1956                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1957
1958         override_cache_bits(&boot_cpu_data);
1959
1960         switch (l1tf_mitigation) {
1961         case L1TF_MITIGATION_OFF:
1962         case L1TF_MITIGATION_FLUSH_NOWARN:
1963         case L1TF_MITIGATION_FLUSH:
1964                 break;
1965         case L1TF_MITIGATION_FLUSH_NOSMT:
1966         case L1TF_MITIGATION_FULL:
1967                 cpu_smt_disable(false);
1968                 break;
1969         case L1TF_MITIGATION_FULL_FORCE:
1970                 cpu_smt_disable(true);
1971                 break;
1972         }
1973
1974 #if CONFIG_PGTABLE_LEVELS == 2
1975         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1976         return;
1977 #endif
1978
1979         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1980         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1981                         e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1982                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1983                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1984                                 half_pa);
1985                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1986                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1987                 return;
1988         }
1989
1990         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1991 }
1992
1993 static int __init l1tf_cmdline(char *str)
1994 {
1995         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1996                 return 0;
1997
1998         if (!str)
1999                 return -EINVAL;
2000
2001         if (!strcmp(str, "off"))
2002                 l1tf_mitigation = L1TF_MITIGATION_OFF;
2003         else if (!strcmp(str, "flush,nowarn"))
2004                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2005         else if (!strcmp(str, "flush"))
2006                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2007         else if (!strcmp(str, "flush,nosmt"))
2008                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2009         else if (!strcmp(str, "full"))
2010                 l1tf_mitigation = L1TF_MITIGATION_FULL;
2011         else if (!strcmp(str, "full,force"))
2012                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2013
2014         return 0;
2015 }
2016 early_param("l1tf", l1tf_cmdline);
2017
2018 #undef pr_fmt
2019 #define pr_fmt(fmt) fmt
2020
2021 #ifdef CONFIG_SYSFS
2022
2023 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2024
2025 #if IS_ENABLED(CONFIG_KVM_INTEL)
2026 static const char * const l1tf_vmx_states[] = {
2027         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
2028         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
2029         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
2030         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
2031         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
2032         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
2033 };
2034
2035 static ssize_t l1tf_show_state(char *buf)
2036 {
2037         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2038                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2039
2040         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2041             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2042              sched_smt_active())) {
2043                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2044                                l1tf_vmx_states[l1tf_vmx_mitigation]);
2045         }
2046
2047         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2048                        l1tf_vmx_states[l1tf_vmx_mitigation],
2049                        sched_smt_active() ? "vulnerable" : "disabled");
2050 }
2051
2052 static ssize_t itlb_multihit_show_state(char *buf)
2053 {
2054         if (itlb_multihit_kvm_mitigation)
2055                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2056         else
2057                 return sprintf(buf, "KVM: Vulnerable\n");
2058 }
2059 #else
2060 static ssize_t l1tf_show_state(char *buf)
2061 {
2062         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2063 }
2064
2065 static ssize_t itlb_multihit_show_state(char *buf)
2066 {
2067         return sprintf(buf, "Processor vulnerable\n");
2068 }
2069 #endif
2070
2071 static ssize_t mds_show_state(char *buf)
2072 {
2073         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2074                 return sprintf(buf, "%s; SMT Host state unknown\n",
2075                                mds_strings[mds_mitigation]);
2076         }
2077
2078         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2079                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2080                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2081                                 sched_smt_active() ? "mitigated" : "disabled"));
2082         }
2083
2084         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2085                        sched_smt_active() ? "vulnerable" : "disabled");
2086 }
2087
2088 static ssize_t tsx_async_abort_show_state(char *buf)
2089 {
2090         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2091             (taa_mitigation == TAA_MITIGATION_OFF))
2092                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2093
2094         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2095                 return sprintf(buf, "%s; SMT Host state unknown\n",
2096                                taa_strings[taa_mitigation]);
2097         }
2098
2099         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2100                        sched_smt_active() ? "vulnerable" : "disabled");
2101 }
2102
2103 static ssize_t mmio_stale_data_show_state(char *buf)
2104 {
2105         if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2106                 return sysfs_emit(buf, "Unknown: No mitigations\n");
2107
2108         if (mmio_mitigation == MMIO_MITIGATION_OFF)
2109                 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2110
2111         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2112                 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2113                                   mmio_strings[mmio_mitigation]);
2114         }
2115
2116         return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2117                           sched_smt_active() ? "vulnerable" : "disabled");
2118 }
2119
2120 static char *stibp_state(void)
2121 {
2122         if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
2123                 return "";
2124
2125         switch (spectre_v2_user_stibp) {
2126         case SPECTRE_V2_USER_NONE:
2127                 return ", STIBP: disabled";
2128         case SPECTRE_V2_USER_STRICT:
2129                 return ", STIBP: forced";
2130         case SPECTRE_V2_USER_STRICT_PREFERRED:
2131                 return ", STIBP: always-on";
2132         case SPECTRE_V2_USER_PRCTL:
2133         case SPECTRE_V2_USER_SECCOMP:
2134                 if (static_key_enabled(&switch_to_cond_stibp))
2135                         return ", STIBP: conditional";
2136         }
2137         return "";
2138 }
2139
2140 static char *ibpb_state(void)
2141 {
2142         if (boot_cpu_has(X86_FEATURE_IBPB)) {
2143                 if (static_key_enabled(&switch_mm_always_ibpb))
2144                         return ", IBPB: always-on";
2145                 if (static_key_enabled(&switch_mm_cond_ibpb))
2146                         return ", IBPB: conditional";
2147                 return ", IBPB: disabled";
2148         }
2149         return "";
2150 }
2151
2152 static char *pbrsb_eibrs_state(void)
2153 {
2154         if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2155                 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2156                     boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2157                         return ", PBRSB-eIBRS: SW sequence";
2158                 else
2159                         return ", PBRSB-eIBRS: Vulnerable";
2160         } else {
2161                 return ", PBRSB-eIBRS: Not affected";
2162         }
2163 }
2164
2165 static ssize_t spectre_v2_show_state(char *buf)
2166 {
2167         if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2168                 return sprintf(buf, "Vulnerable: LFENCE\n");
2169
2170         if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2171                 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2172
2173         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2174             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2175                 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2176
2177         return sprintf(buf, "%s%s%s%s%s%s%s\n",
2178                        spectre_v2_strings[spectre_v2_enabled],
2179                        ibpb_state(),
2180                        boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2181                        stibp_state(),
2182                        boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2183                        pbrsb_eibrs_state(),
2184                        spectre_v2_module_string());
2185 }
2186
2187 static ssize_t srbds_show_state(char *buf)
2188 {
2189         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2190 }
2191
2192 static ssize_t retbleed_show_state(char *buf)
2193 {
2194         return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2195 }
2196
2197 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2198                                char *buf, unsigned int bug)
2199 {
2200         if (!boot_cpu_has_bug(bug))
2201                 return sprintf(buf, "Not affected\n");
2202
2203         switch (bug) {
2204         case X86_BUG_CPU_MELTDOWN:
2205                 if (boot_cpu_has(X86_FEATURE_PTI))
2206                         return sprintf(buf, "Mitigation: PTI\n");
2207
2208                 break;
2209
2210         case X86_BUG_SPECTRE_V1:
2211                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2212
2213         case X86_BUG_SPECTRE_V2:
2214                 return spectre_v2_show_state(buf);
2215
2216         case X86_BUG_SPEC_STORE_BYPASS:
2217                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2218
2219         case X86_BUG_L1TF:
2220                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2221                         return l1tf_show_state(buf);
2222                 break;
2223
2224         case X86_BUG_MDS:
2225                 return mds_show_state(buf);
2226
2227         case X86_BUG_TAA:
2228                 return tsx_async_abort_show_state(buf);
2229
2230         case X86_BUG_ITLB_MULTIHIT:
2231                 return itlb_multihit_show_state(buf);
2232
2233         case X86_BUG_SRBDS:
2234                 return srbds_show_state(buf);
2235
2236         case X86_BUG_MMIO_STALE_DATA:
2237         case X86_BUG_MMIO_UNKNOWN:
2238                 return mmio_stale_data_show_state(buf);
2239
2240         case X86_BUG_RETBLEED:
2241                 return retbleed_show_state(buf);
2242
2243         default:
2244                 break;
2245         }
2246
2247         return sprintf(buf, "Vulnerable\n");
2248 }
2249
2250 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2251 {
2252         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2253 }
2254
2255 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2256 {
2257         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2258 }
2259
2260 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2261 {
2262         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2263 }
2264
2265 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2266 {
2267         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2268 }
2269
2270 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2271 {
2272         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2273 }
2274
2275 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2276 {
2277         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2278 }
2279
2280 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2281 {
2282         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2283 }
2284
2285 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2286 {
2287         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2288 }
2289
2290 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2291 {
2292         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2293 }
2294
2295 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2296 {
2297         if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2298                 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2299         else
2300                 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2301 }
2302
2303 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2304 {
2305         return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2306 }
2307 #endif