1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
14 #include <asm/cacheinfo.h>
16 #include <asm/spec-ctrl.h>
19 #include <asm/pci-direct.h>
20 #include <asm/delay.h>
21 #include <asm/debugreg.h>
22 #include <asm/resctrl.h>
25 # include <asm/mmconfig.h>
30 static const int amd_erratum_383[];
31 static const int amd_erratum_400[];
32 static const int amd_erratum_1054[];
33 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
36 * nodes_per_socket: Stores the number of nodes per socket.
37 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
38 * Node Identifiers[10:8]
40 static u32 nodes_per_socket = 1;
42 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
47 WARN_ONCE((boot_cpu_data.x86 != 0xf),
48 "%s should only be used on K8!\n", __func__);
53 err = rdmsr_safe_regs(gprs);
55 *p = gprs[0] | ((u64)gprs[2] << 32);
60 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
64 WARN_ONCE((boot_cpu_data.x86 != 0xf),
65 "%s should only be used on K8!\n", __func__);
72 return wrmsr_safe_regs(gprs);
76 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
77 * misexecution of code under Linux. Owners of such processors should
78 * contact AMD for precise details and a CPU swap.
80 * See http://www.multimania.com/poulot/k6bug.html
81 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
82 * (Publication # 21266 Issue Date: August 1998)
84 * The following test is erm.. interesting. AMD neglected to up
85 * the chip setting when fixing the bug but they also tweaked some
86 * performance at the same time..
90 extern __visible void vide(void);
93 ".type vide, @function\n"
98 static void init_amd_k5(struct cpuinfo_x86 *c)
102 * General Systems BIOSen alias the cpu frequency registers
103 * of the Elan at 0x000df000. Unfortunately, one of the Linux
104 * drivers subsequently pokes it, and changes the CPU speed.
105 * Workaround : Remove the unneeded alias.
107 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
108 #define CBAR_ENB (0x80000000)
109 #define CBAR_KEY (0X000000CB)
110 if (c->x86_model == 9 || c->x86_model == 10) {
111 if (inl(CBAR) & CBAR_ENB)
112 outl(0 | CBAR_KEY, CBAR);
117 static void init_amd_k6(struct cpuinfo_x86 *c)
121 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
123 if (c->x86_model < 6) {
124 /* Based on AMD doc 20734R - June 2000 */
125 if (c->x86_model == 0) {
126 clear_cpu_cap(c, X86_FEATURE_APIC);
127 set_cpu_cap(c, X86_FEATURE_PGE);
132 if (c->x86_model == 6 && c->x86_stepping == 1) {
133 const int K6_BUG_LOOP = 1000000;
135 void (*f_vide)(void);
138 pr_info("AMD K6 stepping B detected - ");
141 * It looks like AMD fixed the 2.6.2 bug and improved indirect
142 * calls at the same time.
147 OPTIMIZER_HIDE_VAR(f_vide);
154 if (d > 20*K6_BUG_LOOP)
155 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
157 pr_cont("probably OK (after B9730xxxx).\n");
160 /* K6 with old style WHCR */
161 if (c->x86_model < 8 ||
162 (c->x86_model == 8 && c->x86_stepping < 8)) {
163 /* We can only write allocate on the low 508Mb */
167 rdmsr(MSR_K6_WHCR, l, h);
168 if ((l&0x0000FFFF) == 0) {
170 l = (1<<0)|((mbytes/4)<<1);
171 local_irq_save(flags);
173 wrmsr(MSR_K6_WHCR, l, h);
174 local_irq_restore(flags);
175 pr_info("Enabling old style K6 write allocation for %d Mb\n",
181 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
182 c->x86_model == 9 || c->x86_model == 13) {
183 /* The more serious chips .. */
188 rdmsr(MSR_K6_WHCR, l, h);
189 if ((l&0xFFFF0000) == 0) {
191 l = ((mbytes>>2)<<22)|(1<<16);
192 local_irq_save(flags);
194 wrmsr(MSR_K6_WHCR, l, h);
195 local_irq_restore(flags);
196 pr_info("Enabling new style K6 write allocation for %d Mb\n",
203 if (c->x86_model == 10) {
204 /* AMD Geode LX is model 10 */
205 /* placeholder for any needed mods */
211 static void init_amd_k7(struct cpuinfo_x86 *c)
217 * Bit 15 of Athlon specific MSR 15, needs to be 0
218 * to enable SSE on Palomino/Morgan/Barton CPU's.
219 * If the BIOS didn't enable it already, enable it here.
221 if (c->x86_model >= 6 && c->x86_model <= 10) {
222 if (!cpu_has(c, X86_FEATURE_XMM)) {
223 pr_info("Enabling disabled K7/SSE Support.\n");
224 msr_clear_bit(MSR_K7_HWCR, 15);
225 set_cpu_cap(c, X86_FEATURE_XMM);
230 * It's been determined by AMD that Athlons since model 8 stepping 1
231 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
232 * As per AMD technical note 27212 0.2
234 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
235 rdmsr(MSR_K7_CLK_CTL, l, h);
236 if ((l & 0xfff00000) != 0x20000000) {
237 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
238 l, ((l & 0x000fffff)|0x20000000));
239 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
243 /* calling is from identify_secondary_cpu() ? */
248 * Certain Athlons might work (for various values of 'work') in SMP
249 * but they are not certified as MP capable.
251 /* Athlon 660/661 is valid. */
252 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
253 (c->x86_stepping == 1)))
256 /* Duron 670 is valid */
257 if ((c->x86_model == 7) && (c->x86_stepping == 0))
261 * Athlon 662, Duron 671, and Athlon >model 7 have capability
262 * bit. It's worth noting that the A5 stepping (662) of some
263 * Athlon XP's have the MP bit set.
264 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
267 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
268 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
270 if (cpu_has(c, X86_FEATURE_MP))
273 /* If we get here, not a certified SMP capable AMD system. */
276 * Don't taint if we are running SMP kernel on a single non-MP
279 WARN_ONCE(1, "WARNING: This combination of AMD"
280 " processors is not suitable for SMP.\n");
281 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
287 * To workaround broken NUMA config. Read the comment in
288 * srat_detect_node().
290 static int nearby_node(int apicid)
294 for (i = apicid - 1; i >= 0; i--) {
295 node = __apicid_to_node[i];
296 if (node != NUMA_NO_NODE && node_online(node))
299 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
300 node = __apicid_to_node[i];
301 if (node != NUMA_NO_NODE && node_online(node))
304 return first_node(node_online_map); /* Shouldn't happen */
309 * Fix up cpu_core_id for pre-F17h systems to be in the
310 * [0 .. cores_per_node - 1] range. Not really needed but
311 * kept so as not to break existing setups.
313 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
320 cus_per_node = c->x86_max_cores / nodes_per_socket;
321 c->cpu_core_id %= cus_per_node;
325 * Fixup core topology information for
326 * (1) AMD multi-node processors
327 * Assumption: Number of cores in each internal node is the same.
328 * (2) AMD processors supporting compute units
330 static void amd_get_topology(struct cpuinfo_x86 *c)
332 int cpu = smp_processor_id();
334 /* get information required for multi-node processors */
335 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
337 u32 eax, ebx, ecx, edx;
339 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
341 c->cpu_die_id = ecx & 0xff;
344 c->cu_id = ebx & 0xff;
346 if (c->x86 >= 0x17) {
347 c->cpu_core_id = ebx & 0xff;
349 if (smp_num_siblings > 1)
350 c->x86_max_cores /= smp_num_siblings;
354 * In case leaf B is available, use it to derive
355 * topology information.
357 err = detect_extended_topology(c);
359 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
361 cacheinfo_amd_init_llc_id(c, cpu);
363 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
366 rdmsrl(MSR_FAM10H_NODE_ID, value);
367 c->cpu_die_id = value & 7;
369 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
373 if (nodes_per_socket > 1) {
374 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
375 legacy_fixup_core_id(c);
380 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
381 * Assumes number of cores is a power of two.
383 static void amd_detect_cmp(struct cpuinfo_x86 *c)
386 int cpu = smp_processor_id();
388 bits = c->x86_coreid_bits;
389 /* Low order bits define the core id (index of core in socket) */
390 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
391 /* Convert the initial APIC ID into the socket ID */
392 c->phys_proc_id = c->initial_apicid >> bits;
393 /* use socket ID also for last level cache */
394 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
397 u32 amd_get_nodes_per_socket(void)
399 return nodes_per_socket;
401 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
403 static void srat_detect_node(struct cpuinfo_x86 *c)
406 int cpu = smp_processor_id();
408 unsigned apicid = c->apicid;
410 node = numa_cpu_node(cpu);
411 if (node == NUMA_NO_NODE)
412 node = get_llc_id(cpu);
415 * On multi-fabric platform (e.g. Numascale NumaChip) a
416 * platform-specific handler needs to be called to fixup some
419 if (x86_cpuinit.fixup_cpu_id)
420 x86_cpuinit.fixup_cpu_id(c, node);
422 if (!node_online(node)) {
424 * Two possibilities here:
426 * - The CPU is missing memory and no node was created. In
427 * that case try picking one from a nearby CPU.
429 * - The APIC IDs differ from the HyperTransport node IDs
430 * which the K8 northbridge parsing fills in. Assume
431 * they are all increased by a constant offset, but in
432 * the same order as the HT nodeids. If that doesn't
433 * result in a usable node fall back to the path for the
436 * This workaround operates directly on the mapping between
437 * APIC ID and NUMA node, assuming certain relationship
438 * between APIC ID, HT node ID and NUMA topology. As going
439 * through CPU mapping may alter the outcome, directly
440 * access __apicid_to_node[].
442 int ht_nodeid = c->initial_apicid;
444 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
445 node = __apicid_to_node[ht_nodeid];
446 /* Pick a nearby node */
447 if (!node_online(node))
448 node = nearby_node(apicid);
450 numa_set_node(cpu, node);
454 static void early_init_amd_mc(struct cpuinfo_x86 *c)
459 /* Multi core CPU? */
460 if (c->extended_cpuid_level < 0x80000008)
463 ecx = cpuid_ecx(0x80000008);
465 c->x86_max_cores = (ecx & 0xff) + 1;
467 /* CPU telling us the core id bits shift? */
468 bits = (ecx >> 12) & 0xF;
470 /* Otherwise recompute */
472 while ((1 << bits) < c->x86_max_cores)
476 c->x86_coreid_bits = bits;
480 static void bsp_init_amd(struct cpuinfo_x86 *c)
482 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
485 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
488 rdmsrl(MSR_K7_HWCR, val);
489 if (!(val & BIT(24)))
490 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
494 if (c->x86 == 0x15) {
495 unsigned long upperbit;
498 cpuid = cpuid_edx(0x80000005);
499 assoc = cpuid >> 16 & 0xff;
500 upperbit = ((cpuid >> 24) << 10) / assoc;
502 va_align.mask = (upperbit - 1) & PAGE_MASK;
503 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
505 /* A random value per boot for bit slice [12:upper_bit) */
506 va_align.bits = get_random_int() & va_align.mask;
509 if (cpu_has(c, X86_FEATURE_MWAITX))
512 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
515 ecx = cpuid_ecx(0x8000001e);
516 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
517 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
520 rdmsrl(MSR_FAM10H_NODE_ID, value);
521 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
524 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
525 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
526 c->x86 >= 0x15 && c->x86 <= 0x17) {
530 case 0x15: bit = 54; break;
531 case 0x16: bit = 33; break;
532 case 0x17: bit = 10; break;
536 * Try to cache the base value so further operations can
537 * avoid RMW. If that faults, do not enable SSBD.
539 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
540 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
541 setup_force_cpu_cap(X86_FEATURE_SSBD);
542 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
546 resctrl_cpu_detect(c);
549 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
554 * BIOS support is required for SME and SEV.
555 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
556 * the SME physical address space reduction value.
557 * If BIOS has not enabled SME then don't advertise the
558 * SME feature (set in scattered.c).
559 * If the kernel has not enabled SME via any means then
560 * don't advertise the SME feature.
561 * For SEV: If BIOS has not enabled SEV then don't advertise the
562 * SEV and SEV_ES feature (set in scattered.c).
564 * In all cases, since support for SME and SEV requires long mode,
565 * don't advertise the feature under CONFIG_X86_32.
567 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
568 /* Check if memory encryption is enabled */
569 rdmsrl(MSR_AMD64_SYSCFG, msr);
570 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
574 * Always adjust physical address bits. Even though this
575 * will be a value above 32-bits this is still done for
576 * CONFIG_X86_32 so that accurate values are reported.
578 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
580 if (IS_ENABLED(CONFIG_X86_32))
584 setup_clear_cpu_cap(X86_FEATURE_SME);
586 rdmsrl(MSR_K7_HWCR, msr);
587 if (!(msr & MSR_K7_HWCR_SMMLOCK))
593 setup_clear_cpu_cap(X86_FEATURE_SME);
595 setup_clear_cpu_cap(X86_FEATURE_SEV);
596 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
600 static void early_init_amd(struct cpuinfo_x86 *c)
605 early_init_amd_mc(c);
608 set_cpu_cap(c, X86_FEATURE_K8);
610 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
613 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
614 * with P/T states and does not stop in deep C-states
616 if (c->x86_power & (1 << 8)) {
617 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
618 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
621 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
622 if (c->x86_power & BIT(12))
623 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
625 /* Bit 14 indicates the Runtime Average Power Limit interface. */
626 if (c->x86_power & BIT(14))
627 set_cpu_cap(c, X86_FEATURE_RAPL);
630 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
632 /* Set MTRR capability flag if appropriate */
634 if (c->x86_model == 13 || c->x86_model == 9 ||
635 (c->x86_model == 8 && c->x86_stepping >= 8))
636 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
638 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
640 * ApicID can always be treated as an 8-bit value for AMD APIC versions
641 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
642 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
645 if (boot_cpu_has(X86_FEATURE_APIC)) {
647 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
648 else if (c->x86 >= 0xf) {
649 /* check CPU config space for extended APIC ID */
652 val = read_pci_config(0, 24, 0, 0x68);
653 if ((val >> 17 & 0x3) == 0x3)
654 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
660 * This is only needed to tell the kernel whether to use VMCALL
661 * and VMMCALL. VMMCALL is never executed except under virt, so
662 * we can set it unconditionally.
664 set_cpu_cap(c, X86_FEATURE_VMMCALL);
666 /* F16h erratum 793, CVE-2013-6885 */
667 if (c->x86 == 0x16 && c->x86_model <= 0xf)
668 msr_set_bit(MSR_AMD64_LS_CFG, 15);
671 * Check whether the machine is affected by erratum 400. This is
672 * used to select the proper idle routine and to enable the check
673 * whether the machine is affected in arch_post_acpi_init(), which
674 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
676 if (cpu_has_amd_erratum(c, amd_erratum_400))
677 set_cpu_bug(c, X86_BUG_AMD_E400);
679 early_detect_mem_encrypt(c);
681 /* Re-enable TopologyExtensions if switched off by BIOS */
682 if (c->x86 == 0x15 &&
683 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
684 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
686 if (msr_set_bit(0xc0011005, 54) > 0) {
687 rdmsrl(0xc0011005, value);
688 if (value & BIT_64(54)) {
689 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
690 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
695 if (cpu_has(c, X86_FEATURE_TOPOEXT))
696 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
699 static void init_amd_k8(struct cpuinfo_x86 *c)
704 /* On C+ stepping K8 rep microcode works well for copy/memset */
705 level = cpuid_eax(1);
706 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
707 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
710 * Some BIOSes incorrectly force this feature, but only K8 revision D
711 * (model = 0x14) and later actually support it.
712 * (AMD Erratum #110, docId: 25759).
714 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
715 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
716 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
717 value &= ~BIT_64(32);
718 wrmsrl_amd_safe(0xc001100d, value);
722 if (!c->x86_model_id[0])
723 strcpy(c->x86_model_id, "Hammer");
727 * Disable TLB flush filter by setting HWCR.FFDIS on K8
728 * bit 6 of msr C001_0015
730 * Errata 63 for SH-B3 steppings
731 * Errata 122 for all steppings (F+ have it disabled by default)
733 msr_set_bit(MSR_K7_HWCR, 6);
735 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
738 static void init_amd_gh(struct cpuinfo_x86 *c)
740 #ifdef CONFIG_MMCONF_FAM10H
741 /* do this for boot cpu */
742 if (c == &boot_cpu_data)
743 check_enable_amd_mmconf_dmi();
745 fam10h_check_enable_mmcfg();
749 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
750 * is always needed when GART is enabled, even in a kernel which has no
751 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
752 * If it doesn't, we do it here as suggested by the BKDG.
754 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
756 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
759 * On family 10h BIOS may not have properly enabled WC+ support, causing
760 * it to be converted to CD memtype. This may result in performance
761 * degradation for certain nested-paging guests. Prevent this conversion
762 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
764 * NOTE: we want to use the _safe accessors so as not to #GP kvm
765 * guests on older kvm hosts.
767 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
769 if (cpu_has_amd_erratum(c, amd_erratum_383))
770 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
773 #define MSR_AMD64_DE_CFG 0xC0011029
775 static void init_amd_ln(struct cpuinfo_x86 *c)
778 * Apply erratum 665 fix unconditionally so machines without a BIOS
781 msr_set_bit(MSR_AMD64_DE_CFG, 31);
784 static bool rdrand_force;
786 static int __init rdrand_cmdline(char *str)
791 if (!strcmp(str, "force"))
798 early_param("rdrand", rdrand_cmdline);
800 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
803 * Saving of the MSR used to hide the RDRAND support during
804 * suspend/resume is done by arch/x86/power/cpu.c, which is
805 * dependent on CONFIG_PM_SLEEP.
807 if (!IS_ENABLED(CONFIG_PM_SLEEP))
811 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
812 * RDRAND support using the CPUID function directly.
814 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
817 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
820 * Verify that the CPUID change has occurred in case the kernel is
821 * running virtualized and the hypervisor doesn't support the MSR.
823 if (cpuid_ecx(1) & BIT(30)) {
824 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
828 clear_cpu_cap(c, X86_FEATURE_RDRAND);
829 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
832 static void init_amd_jg(struct cpuinfo_x86 *c)
835 * Some BIOS implementations do not restore proper RDRAND support
836 * across suspend and resume. Check on whether to hide the RDRAND
837 * instruction support via CPUID.
839 clear_rdrand_cpuid_bit(c);
842 static void init_amd_bd(struct cpuinfo_x86 *c)
847 * The way access filter has a performance penalty on some workloads.
848 * Disable it on the affected CPUs.
850 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
851 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
853 wrmsrl_safe(MSR_F15H_IC_CFG, value);
858 * Some BIOS implementations do not restore proper RDRAND support
859 * across suspend and resume. Check on whether to hide the RDRAND
860 * instruction support via CPUID.
862 clear_rdrand_cpuid_bit(c);
865 static void init_amd_zn(struct cpuinfo_x86 *c)
867 set_cpu_cap(c, X86_FEATURE_ZEN);
870 node_reclaim_distance = 32;
874 * Fix erratum 1076: CPB feature bit not being set in CPUID.
875 * Always set it, except when running under a hypervisor.
877 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
878 set_cpu_cap(c, X86_FEATURE_CPB);
881 static void init_amd(struct cpuinfo_x86 *c)
886 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
887 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
889 clear_cpu_cap(c, 0*32+31);
892 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
894 /* get apicid instead of initial apic id from cpuid */
895 c->apicid = hard_smp_processor_id();
897 /* K6s reports MCEs but don't actually have all the MSRs */
899 clear_cpu_cap(c, X86_FEATURE_MCE);
902 case 4: init_amd_k5(c); break;
903 case 5: init_amd_k6(c); break;
904 case 6: init_amd_k7(c); break;
905 case 0xf: init_amd_k8(c); break;
906 case 0x10: init_amd_gh(c); break;
907 case 0x12: init_amd_ln(c); break;
908 case 0x15: init_amd_bd(c); break;
909 case 0x16: init_amd_jg(c); break;
910 case 0x17: fallthrough;
911 case 0x19: init_amd_zn(c); break;
915 * Enable workaround for FXSAVE leak on CPUs
916 * without a XSaveErPtr feature
918 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
919 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
921 cpu_detect_cache_sizes(c);
927 init_amd_cacheinfo(c);
929 if (cpu_has(c, X86_FEATURE_XMM2)) {
931 * Use LFENCE for execution serialization. On families which
932 * don't have that MSR, LFENCE is already serializing.
933 * msr_set_bit() uses the safe accessors, too, even if the MSR
936 msr_set_bit(MSR_F10H_DECFG,
937 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
939 /* A serializing LFENCE stops RDTSC speculation */
940 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
944 * Family 0x12 and above processors have APIC timer
945 * running in deep C states.
948 set_cpu_cap(c, X86_FEATURE_ARAT);
950 /* 3DNow or LM implies PREFETCHW */
951 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
952 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
953 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
955 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
956 if (!cpu_has(c, X86_FEATURE_XENPV))
957 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
960 * Turn on the Instructions Retired free counter on machines not
961 * susceptible to erratum #1054 "Instructions Retired Performance
962 * Counter May Be Inaccurate".
964 if (cpu_has(c, X86_FEATURE_IRPERF) &&
965 !cpu_has_amd_erratum(c, amd_erratum_1054))
966 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
968 check_null_seg_clears_base(c);
972 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
974 /* AMD errata T13 (order #21922) */
977 if (c->x86_model == 3 && c->x86_stepping == 0)
979 /* Tbird rev A1/A2 */
980 if (c->x86_model == 4 &&
981 (c->x86_stepping == 0 || c->x86_stepping == 1))
988 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
990 u32 ebx, eax, ecx, edx;
996 if (c->extended_cpuid_level < 0x80000006)
999 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1001 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1002 tlb_lli_4k[ENTRIES] = ebx & mask;
1005 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1006 * characteristics from the CPUID function 0x80000005 instead.
1008 if (c->x86 == 0xf) {
1009 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1013 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1014 if (!((eax >> 16) & mask))
1015 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1017 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1019 /* a 4M entry uses two 2M entries */
1020 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1022 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1023 if (!(eax & mask)) {
1025 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1026 tlb_lli_2m[ENTRIES] = 1024;
1028 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1029 tlb_lli_2m[ENTRIES] = eax & 0xff;
1032 tlb_lli_2m[ENTRIES] = eax & mask;
1034 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1037 static const struct cpu_dev amd_cpu_dev = {
1039 .c_ident = { "AuthenticAMD" },
1040 #ifdef CONFIG_X86_32
1042 { .family = 4, .model_names =
1045 [7] = "486 DX/2-WB",
1047 [9] = "486 DX/4-WB",
1053 .legacy_cache_size = amd_size_cache,
1055 .c_early_init = early_init_amd,
1056 .c_detect_tlb = cpu_detect_tlb_amd,
1057 .c_bsp_init = bsp_init_amd,
1059 .c_x86_vendor = X86_VENDOR_AMD,
1062 cpu_dev_register(amd_cpu_dev);
1065 * AMD errata checking
1067 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1068 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1069 * have an OSVW id assigned, which it takes as first argument. Both take a
1070 * variable number of family-specific model-stepping ranges created by
1071 * AMD_MODEL_RANGE().
1075 * const int amd_erratum_319[] =
1076 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1077 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1078 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1081 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1082 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1083 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1084 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1085 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1086 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1087 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1089 static const int amd_erratum_400[] =
1090 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1091 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1093 static const int amd_erratum_383[] =
1094 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1096 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
1097 static const int amd_erratum_1054[] =
1098 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
1100 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1102 int osvw_id = *erratum++;
1106 if (osvw_id >= 0 && osvw_id < 65536 &&
1107 cpu_has(cpu, X86_FEATURE_OSVW)) {
1110 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1111 if (osvw_id < osvw_len) {
1114 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1116 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1120 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1121 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1122 while ((range = *erratum++))
1123 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1124 (ms >= AMD_MODEL_RANGE_START(range)) &&
1125 (ms <= AMD_MODEL_RANGE_END(range)))
1131 void set_dr_addr_mask(unsigned long mask, int dr)
1133 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1138 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1143 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1150 u32 amd_get_highest_perf(void)
1152 struct cpuinfo_x86 *c = &boot_cpu_data;
1154 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
1155 (c->x86_model >= 0x70 && c->x86_model < 0x80)))
1158 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
1159 (c->x86_model >= 0x40 && c->x86_model < 0x70)))
1164 EXPORT_SYMBOL_GPL(amd_get_highest_perf);