arch/x86/kernel/apic/x2apic_cluster.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/threads.h>
   3 #include <linux/cpumask.h>
   4 #include <linux/string.h>
   5 #include <linux/kernel.h>
   6 #include <linux/ctype.h>
   7 #include <linux/dmar.h>
   8 #include <linux/irq.h>
   9 #include <linux/cpu.h>
  10
  11 #include <asm/smp.h>
  12 #include <asm/x2apic.h>
  13
  14 static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
  15 static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
  16 static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
  17
  18 static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  19 {
  20         return x2apic_enabled();
  21 }
  22
  23 static inline u32 x2apic_cluster(int cpu)
  24 {
  25         return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
  26 }
  27
  28 static void x2apic_send_IPI(int cpu, int vector)
  29 {
  30         u32 dest = per_cpu(x86_cpu_to_logical_apicid, cpu);
  31
  32         /* x2apic MSRs are special and need a special fence: */
  33         weak_wrmsr_fence();
  34         __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
  35 }
  36
  37 static void
  38 __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
  39 {
  40         struct cpumask *cpus_in_cluster_ptr;
  41         struct cpumask *ipi_mask_ptr;
  42         unsigned int cpu, this_cpu;
  43         unsigned long flags;
  44         u32 dest;
  45
  46         /* x2apic MSRs are special and need a special fence: */
  47         weak_wrmsr_fence();
  48
  49         local_irq_save(flags);
  50
  51         this_cpu = smp_processor_id();
  52
  53         /*
  54          * We are to modify mask, so we need an own copy
  55          * and be sure it's manipulated with irq off.
  56          */
  57         ipi_mask_ptr = this_cpu_cpumask_var_ptr(ipi_mask);
  58         cpumask_copy(ipi_mask_ptr, mask);
  59
  60         /*
  61          * The idea is to send one IPI per cluster.
  62          */
  63         for_each_cpu(cpu, ipi_mask_ptr) {
  64                 unsigned long i;
  65
  66                 cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
  67                 dest = 0;
  68
  69                 /* Collect cpus in cluster. */
  70                 for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
  71                         if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
  72                                 dest |= per_cpu(x86_cpu_to_logical_apicid, i);
  73                 }
  74
  75                 if (!dest)
  76                         continue;
  77
  78                 __x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
  79                 /*
  80                  * Cluster sibling cpus should be discared now so
  81                  * we would not send IPI them second time.
  82                  */
  83                 cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
  84         }
  85
  86         local_irq_restore(flags);
  87 }
  88
  89 static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
  90 {
  91         __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
  92 }
  93
  94 static void
  95 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
  96 {
  97         __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
  98 }
  99
 100 static void x2apic_send_IPI_allbutself(int vector)
 101 {
 102         __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
 103 }
 104
 105 static void x2apic_send_IPI_all(int vector)
 106 {
 107         __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
 108 }
 109
 110 static int
 111 x2apic_cpu_mask_to_apicid(const struct cpumask *mask, struct irq_data *irqdata,
 112                           unsigned int *apicid)
 113 {
 114         struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
 115         unsigned int cpu;
 116         u32 dest = 0;
 117         u16 cluster;
 118
 119         cpu = cpumask_first(mask);
 120         if (cpu >= nr_cpu_ids)
 121                 return -EINVAL;
 122
 123         dest = per_cpu(x86_cpu_to_logical_apicid, cpu);
 124         cluster = x2apic_cluster(cpu);
 125
 126         cpumask_clear(effmsk);
 127         for_each_cpu(cpu, mask) {
 128                 if (cluster != x2apic_cluster(cpu))
 129                         continue;
 130                 dest |= per_cpu(x86_cpu_to_logical_apicid, cpu);
 131                 cpumask_set_cpu(cpu, effmsk);
 132         }
 133
 134         *apicid = dest;
 135         return 0;
 136 }
 137
 138 static void init_x2apic_ldr(void)
 139 {
 140         unsigned int this_cpu = smp_processor_id();
 141         unsigned int cpu;
 142
 143         per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
 144
 145         cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
 146         for_each_online_cpu(cpu) {
 147                 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
 148                         continue;
 149                 cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu));
 150                 cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu));
 151         }
 152 }
 153
 154 /*
 155  * At CPU state changes, update the x2apic cluster sibling info.
 156  */
 157 static int x2apic_prepare_cpu(unsigned int cpu)
 158 {
 159         if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL))
 160                 return -ENOMEM;
 161
 162         if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL)) {
 163                 free_cpumask_var(per_cpu(cpus_in_cluster, cpu));
 164                 return -ENOMEM;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static int x2apic_dead_cpu(unsigned int this_cpu)
 171 {
 172         int cpu;
 173
 174         for_each_online_cpu(cpu) {
 175                 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
 176                         continue;
 177                 cpumask_clear_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu));
 178                 cpumask_clear_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu));
 179         }
 180         free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
 181         free_cpumask_var(per_cpu(ipi_mask, this_cpu));
 182         return 0;
 183 }
 184
 185 static int x2apic_cluster_probe(void)
 186 {
 187         int cpu = smp_processor_id();
 188         int ret;
 189
 190         if (!x2apic_mode)
 191                 return 0;
 192
 193         ret = cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare",
 194                                 x2apic_prepare_cpu, x2apic_dead_cpu);
 195         if (ret < 0) {
 196                 pr_err("Failed to register X2APIC_PREPARE\n");
 197                 return 0;
 198         }
 199         cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, cpu));
 200         return 1;
 201 }
 202
 203 static const struct cpumask *x2apic_cluster_target_cpus(void)
 204 {
 205         return cpu_all_mask;
 206 }
 207
 208 /*
 209  * Each x2apic cluster is an allocation domain.
 210  */
 211 static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask,
 212                                              const struct cpumask *mask)
 213 {
 214         /*
 215          * To minimize vector pressure, default case of boot, device bringup
 216          * etc will use a single cpu for the interrupt destination.
 217          *
 218          * On explicit migration requests coming from irqbalance etc,
 219          * interrupts will be routed to the x2apic cluster (cluster-id
 220          * derived from the first cpu in the mask) members specified
 221          * in the mask.
 222          */
 223         if (mask == x2apic_cluster_target_cpus())
 224                 cpumask_copy(retmask, cpumask_of(cpu));
 225         else
 226                 cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu));
 227 }
 228
 229 static struct apic apic_x2apic_cluster __ro_after_init = {
 230
 231         .name                           = "cluster x2apic",
 232         .probe                          = x2apic_cluster_probe,
 233         .acpi_madt_oem_check            = x2apic_acpi_madt_oem_check,
 234         .apic_id_valid                  = x2apic_apic_id_valid,
 235         .apic_id_registered             = x2apic_apic_id_registered,
 236
 237         .irq_delivery_mode              = dest_LowestPrio,
 238         .irq_dest_mode                  = 1, /* logical */
 239
 240         .target_cpus                    = x2apic_cluster_target_cpus,
 241         .disable_esr                    = 0,
 242         .dest_logical                   = APIC_DEST_LOGICAL,
 243         .check_apicid_used              = NULL,
 244
 245         .vector_allocation_domain       = cluster_vector_allocation_domain,
 246         .init_apic_ldr                  = init_x2apic_ldr,
 247
 248         .ioapic_phys_id_map             = NULL,
 249         .setup_apic_routing             = NULL,
 250         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 251         .apicid_to_cpu_present          = NULL,
 252         .check_phys_apicid_present      = default_check_phys_apicid_present,
 253         .phys_pkg_id                    = x2apic_phys_pkg_id,
 254
 255         .get_apic_id                    = x2apic_get_apic_id,
 256         .set_apic_id                    = x2apic_set_apic_id,
 257
 258         .cpu_mask_to_apicid             = x2apic_cpu_mask_to_apicid,
 259
 260         .send_IPI                       = x2apic_send_IPI,
 261         .send_IPI_mask                  = x2apic_send_IPI_mask,
 262         .send_IPI_mask_allbutself       = x2apic_send_IPI_mask_allbutself,
 263         .send_IPI_allbutself            = x2apic_send_IPI_allbutself,
 264         .send_IPI_all                   = x2apic_send_IPI_all,
 265         .send_IPI_self                  = x2apic_send_IPI_self,
 266
 267         .inquire_remote_apic            = NULL,
 268
 269         .read                           = native_apic_msr_read,
 270         .write                          = native_apic_msr_write,
 271         .eoi_write                      = native_apic_msr_eoi_write,
 272         .icr_read                       = native_x2apic_icr_read,
 273         .icr_write                      = native_x2apic_icr_write,
 274         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 275         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 276 };
 277
 278 apic_driver(apic_x2apic_cluster);