2 * Support of MSI, HPET and DMAR interrupts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/pci.h>
17 #include <linux/dmar.h>
18 #include <linux/hpet.h>
19 #include <linux/msi.h>
20 #include <asm/irqdomain.h>
21 #include <asm/msidef.h>
23 #include <asm/hw_irq.h>
25 #include <asm/irq_remapping.h>
27 static struct irq_domain *msi_default_domain;
29 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
31 struct irq_cfg *cfg = irqd_cfg(data);
33 msg->address_hi = MSI_ADDR_BASE_HI;
36 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
40 ((apic->irq_dest_mode == 0) ?
41 MSI_ADDR_DEST_MODE_PHYSICAL :
42 MSI_ADDR_DEST_MODE_LOGICAL) |
43 ((apic->irq_delivery_mode != dest_LowestPrio) ?
44 MSI_ADDR_REDIRECTION_CPU :
45 MSI_ADDR_REDIRECTION_LOWPRI) |
46 MSI_ADDR_DEST_ID(cfg->dest_apicid);
49 MSI_DATA_TRIGGER_EDGE |
50 MSI_DATA_LEVEL_ASSERT |
51 ((apic->irq_delivery_mode != dest_LowestPrio) ?
52 MSI_DATA_DELIVERY_FIXED :
53 MSI_DATA_DELIVERY_LOWPRI) |
54 MSI_DATA_VECTOR(cfg->vector);
58 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
59 * which implement the MSI or MSI-X Capability Structure.
61 static struct irq_chip pci_msi_controller = {
63 .irq_unmask = pci_msi_unmask_irq,
64 .irq_mask = pci_msi_mask_irq,
65 .irq_ack = irq_chip_ack_parent,
66 .irq_retrigger = irq_chip_retrigger_hierarchy,
67 .irq_compose_msi_msg = irq_msi_compose_msg,
68 .flags = IRQCHIP_SKIP_SET_WAKE,
71 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
73 struct irq_domain *domain;
74 struct irq_alloc_info info;
76 init_irq_alloc_info(&info, NULL);
77 info.type = X86_IRQ_ALLOC_TYPE_MSI;
80 domain = irq_remapping_get_irq_domain(&info);
82 domain = msi_default_domain;
86 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
89 void native_teardown_msi_irq(unsigned int irq)
91 irq_domain_free_irqs(irq, 1);
94 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
95 msi_alloc_info_t *arg)
97 return arg->msi_hwirq;
100 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
101 msi_alloc_info_t *arg)
103 struct pci_dev *pdev = to_pci_dev(dev);
104 struct msi_desc *desc = first_pci_msi_entry(pdev);
106 init_irq_alloc_info(arg, NULL);
108 if (desc->msi_attrib.is_msix) {
109 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
111 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
112 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
117 EXPORT_SYMBOL_GPL(pci_msi_prepare);
119 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
121 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
123 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
125 static struct msi_domain_ops pci_msi_domain_ops = {
126 .get_hwirq = pci_msi_get_hwirq,
127 .msi_prepare = pci_msi_prepare,
128 .set_desc = pci_msi_set_desc,
131 static struct msi_domain_info pci_msi_domain_info = {
132 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
134 .ops = &pci_msi_domain_ops,
135 .chip = &pci_msi_controller,
136 .handler = handle_edge_irq,
137 .handler_name = "edge",
140 void arch_init_msi_domain(struct irq_domain *parent)
145 msi_default_domain = pci_msi_create_irq_domain(NULL,
146 &pci_msi_domain_info, parent);
147 if (!msi_default_domain)
148 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
151 #ifdef CONFIG_IRQ_REMAP
152 static struct irq_chip pci_msi_ir_controller = {
153 .name = "IR-PCI-MSI",
154 .irq_unmask = pci_msi_unmask_irq,
155 .irq_mask = pci_msi_mask_irq,
156 .irq_ack = irq_chip_ack_parent,
157 .irq_retrigger = irq_chip_retrigger_hierarchy,
158 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
159 .flags = IRQCHIP_SKIP_SET_WAKE,
162 static struct msi_domain_info pci_msi_ir_domain_info = {
163 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
164 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
165 .ops = &pci_msi_domain_ops,
166 .chip = &pci_msi_ir_controller,
167 .handler = handle_edge_irq,
168 .handler_name = "edge",
171 struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
173 return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
177 #ifdef CONFIG_DMAR_TABLE
178 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
180 dmar_msi_write(data->irq, msg);
183 static struct irq_chip dmar_msi_controller = {
185 .irq_unmask = dmar_msi_unmask,
186 .irq_mask = dmar_msi_mask,
187 .irq_ack = irq_chip_ack_parent,
188 .irq_set_affinity = msi_domain_set_affinity,
189 .irq_retrigger = irq_chip_retrigger_hierarchy,
190 .irq_compose_msi_msg = irq_msi_compose_msg,
191 .irq_write_msi_msg = dmar_msi_write_msg,
192 .flags = IRQCHIP_SKIP_SET_WAKE,
195 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
196 msi_alloc_info_t *arg)
201 static int dmar_msi_init(struct irq_domain *domain,
202 struct msi_domain_info *info, unsigned int virq,
203 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
205 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
206 handle_edge_irq, arg->dmar_data, "edge");
211 static struct msi_domain_ops dmar_msi_domain_ops = {
212 .get_hwirq = dmar_msi_get_hwirq,
213 .msi_init = dmar_msi_init,
216 static struct msi_domain_info dmar_msi_domain_info = {
217 .ops = &dmar_msi_domain_ops,
218 .chip = &dmar_msi_controller,
221 static struct irq_domain *dmar_get_irq_domain(void)
223 static struct irq_domain *dmar_domain;
224 static DEFINE_MUTEX(dmar_lock);
226 mutex_lock(&dmar_lock);
227 if (dmar_domain == NULL)
228 dmar_domain = msi_create_irq_domain(NULL, &dmar_msi_domain_info,
230 mutex_unlock(&dmar_lock);
235 int dmar_alloc_hwirq(int id, int node, void *arg)
237 struct irq_domain *domain = dmar_get_irq_domain();
238 struct irq_alloc_info info;
243 init_irq_alloc_info(&info, NULL);
244 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
246 info.dmar_data = arg;
248 return irq_domain_alloc_irqs(domain, 1, node, &info);
251 void dmar_free_hwirq(int irq)
253 irq_domain_free_irqs(irq, 1);
258 * MSI message composition
260 #ifdef CONFIG_HPET_TIMER
261 static inline int hpet_dev_id(struct irq_domain *domain)
263 struct msi_domain_info *info = msi_get_domain_info(domain);
265 return (int)(long)info->data;
268 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
270 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
273 static struct irq_chip hpet_msi_controller __ro_after_init = {
275 .irq_unmask = hpet_msi_unmask,
276 .irq_mask = hpet_msi_mask,
277 .irq_ack = irq_chip_ack_parent,
278 .irq_set_affinity = msi_domain_set_affinity,
279 .irq_retrigger = irq_chip_retrigger_hierarchy,
280 .irq_compose_msi_msg = irq_msi_compose_msg,
281 .irq_write_msi_msg = hpet_msi_write_msg,
282 .flags = IRQCHIP_SKIP_SET_WAKE,
285 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
286 msi_alloc_info_t *arg)
288 return arg->hpet_index;
291 static int hpet_msi_init(struct irq_domain *domain,
292 struct msi_domain_info *info, unsigned int virq,
293 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
295 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
296 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
297 handle_edge_irq, arg->hpet_data, "edge");
302 static void hpet_msi_free(struct irq_domain *domain,
303 struct msi_domain_info *info, unsigned int virq)
305 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
308 static struct msi_domain_ops hpet_msi_domain_ops = {
309 .get_hwirq = hpet_msi_get_hwirq,
310 .msi_init = hpet_msi_init,
311 .msi_free = hpet_msi_free,
314 static struct msi_domain_info hpet_msi_domain_info = {
315 .ops = &hpet_msi_domain_ops,
316 .chip = &hpet_msi_controller,
319 struct irq_domain *hpet_create_irq_domain(int hpet_id)
321 struct irq_domain *parent;
322 struct irq_alloc_info info;
323 struct msi_domain_info *domain_info;
325 if (x86_vector_domain == NULL)
328 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
332 *domain_info = hpet_msi_domain_info;
333 domain_info->data = (void *)(long)hpet_id;
335 init_irq_alloc_info(&info, NULL);
336 info.type = X86_IRQ_ALLOC_TYPE_HPET;
337 info.hpet_id = hpet_id;
338 parent = irq_remapping_get_ir_irq_domain(&info);
340 parent = x86_vector_domain;
342 hpet_msi_controller.name = "IR-HPET-MSI";
344 return msi_create_irq_domain(NULL, domain_info, parent);
347 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
350 struct irq_alloc_info info;
352 init_irq_alloc_info(&info, NULL);
353 info.type = X86_IRQ_ALLOC_TYPE_HPET;
354 info.hpet_data = dev;
355 info.hpet_id = hpet_dev_id(domain);
356 info.hpet_index = dev_num;
358 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);