1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
23 * Historical information which is worth to be preserved:
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h> /* time_after() */
49 #include <linux/slab.h>
50 #include <linux/bootmem.h>
52 #include <asm/irqdomain.h>
57 #include <asm/proto.h>
60 #include <asm/timer.h>
61 #include <asm/i8259.h>
62 #include <asm/setup.h>
63 #include <asm/irq_remapping.h>
64 #include <asm/hw_irq.h>
68 #define for_each_ioapic(idx) \
69 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
70 #define for_each_ioapic_reverse(idx) \
71 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
72 #define for_each_pin(idx, pin) \
73 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
74 #define for_each_ioapic_pin(idx, pin) \
75 for_each_ioapic((idx)) \
76 for_each_pin((idx), (pin))
77 #define for_each_irq_pin(entry, head) \
78 list_for_each_entry(entry, &head, list)
80 static DEFINE_RAW_SPINLOCK(ioapic_lock);
81 static DEFINE_MUTEX(ioapic_mutex);
82 static unsigned int ioapic_dynirq_base;
83 static int ioapic_initialized;
86 struct list_head list;
91 struct list_head irq_2_pin;
92 struct IO_APIC_route_entry entry;
99 struct mp_ioapic_gsi {
104 static struct ioapic {
106 * # of IRQ routing registers
110 * Saved state during suspend/resume, or while enabling intr-remap.
112 struct IO_APIC_route_entry *saved_registers;
113 /* I/O APIC config */
114 struct mpc_ioapic mp_config;
115 /* IO APIC gsi routing info */
116 struct mp_ioapic_gsi gsi_config;
117 struct ioapic_domain_cfg irqdomain_cfg;
118 struct irq_domain *irqdomain;
119 struct resource *iomem_res;
120 } ioapics[MAX_IO_APICS];
122 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
124 int mpc_ioapic_id(int ioapic_idx)
126 return ioapics[ioapic_idx].mp_config.apicid;
129 unsigned int mpc_ioapic_addr(int ioapic_idx)
131 return ioapics[ioapic_idx].mp_config.apicaddr;
134 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
136 return &ioapics[ioapic_idx].gsi_config;
139 static inline int mp_ioapic_pin_count(int ioapic)
141 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
143 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
146 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
148 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
151 static inline bool mp_is_legacy_irq(int irq)
153 return irq >= 0 && irq < nr_legacy_irqs();
157 * Initialize all legacy IRQs and all pins on the first IOAPIC
158 * if we have legacy interrupt controller. Kernel boot option "pirq="
159 * may rely on non-legacy pins on the first IOAPIC.
161 static inline int mp_init_irq_at_boot(int ioapic, int irq)
163 if (!nr_legacy_irqs())
166 return ioapic == 0 || mp_is_legacy_irq(irq);
169 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
171 return ioapics[ioapic].irqdomain;
176 /* The one past the highest gsi number used */
179 /* MP IRQ source entries */
180 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
182 /* # of MP IRQ source entries */
186 int mp_bus_id_to_type[MAX_MP_BUSSES];
189 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
191 int skip_ioapic_setup;
194 * disable_ioapic_support() - disables ioapic support at runtime
196 void disable_ioapic_support(void)
200 noioapicreroute = -1;
202 skip_ioapic_setup = 1;
205 static int __init parse_noapic(char *str)
207 /* disable IO-APIC */
208 disable_ioapic_support();
211 early_param("noapic", parse_noapic);
213 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
214 void mp_save_irq(struct mpc_intsrc *m)
218 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
219 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
220 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
221 m->srcbusirq, m->dstapic, m->dstirq);
223 for (i = 0; i < mp_irq_entries; i++) {
224 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
228 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
229 if (++mp_irq_entries == MAX_IRQ_SOURCES)
230 panic("Max # of irq sources exceeded!!\n");
233 static void alloc_ioapic_saved_registers(int idx)
237 if (ioapics[idx].saved_registers)
240 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
241 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
242 if (!ioapics[idx].saved_registers)
243 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
246 static void free_ioapic_saved_registers(int idx)
248 kfree(ioapics[idx].saved_registers);
249 ioapics[idx].saved_registers = NULL;
252 int __init arch_early_ioapic_init(void)
256 if (!nr_legacy_irqs())
260 alloc_ioapic_saved_registers(i);
267 unsigned int unused[3];
269 unsigned int unused2[11];
273 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
275 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
276 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
279 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
281 struct io_apic __iomem *io_apic = io_apic_base(apic);
282 writel(vector, &io_apic->eoi);
285 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
287 struct io_apic __iomem *io_apic = io_apic_base(apic);
288 writel(reg, &io_apic->index);
289 return readl(&io_apic->data);
292 static void io_apic_write(unsigned int apic, unsigned int reg,
295 struct io_apic __iomem *io_apic = io_apic_base(apic);
297 writel(reg, &io_apic->index);
298 writel(value, &io_apic->data);
302 struct { u32 w1, w2; };
303 struct IO_APIC_route_entry entry;
306 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
308 union entry_union eu;
310 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
311 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
316 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
318 union entry_union eu;
321 raw_spin_lock_irqsave(&ioapic_lock, flags);
322 eu.entry = __ioapic_read_entry(apic, pin);
323 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
329 * When we write a new IO APIC routing entry, we need to write the high
330 * word first! If the mask bit in the low word is clear, we will enable
331 * the interrupt, and we need to make sure the entry is fully populated
332 * before that happens.
334 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
336 union entry_union eu = {{0, 0}};
339 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
340 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
343 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
347 raw_spin_lock_irqsave(&ioapic_lock, flags);
348 __ioapic_write_entry(apic, pin, e);
349 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
353 * When we mask an IO APIC routing entry, we need to write the low
354 * word first, in order to set the mask bit before we change the
357 static void ioapic_mask_entry(int apic, int pin)
360 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
362 raw_spin_lock_irqsave(&ioapic_lock, flags);
363 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
364 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
369 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
370 * shared ISA-space IRQs, so we have to support them. We are super
371 * fast in the common case, and fast for shared ISA-space IRQs.
373 static int __add_pin_to_irq_node(struct mp_chip_data *data,
374 int node, int apic, int pin)
376 struct irq_pin_list *entry;
378 /* don't allow duplicates */
379 for_each_irq_pin(entry, data->irq_2_pin)
380 if (entry->apic == apic && entry->pin == pin)
383 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
385 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
391 list_add_tail(&entry->list, &data->irq_2_pin);
396 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
398 struct irq_pin_list *tmp, *entry;
400 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
401 if (entry->apic == apic && entry->pin == pin) {
402 list_del(&entry->list);
408 static void add_pin_to_irq_node(struct mp_chip_data *data,
409 int node, int apic, int pin)
411 if (__add_pin_to_irq_node(data, node, apic, pin))
412 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
416 * Reroute an IRQ to a different pin.
418 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
419 int oldapic, int oldpin,
420 int newapic, int newpin)
422 struct irq_pin_list *entry;
424 for_each_irq_pin(entry, data->irq_2_pin) {
425 if (entry->apic == oldapic && entry->pin == oldpin) {
426 entry->apic = newapic;
428 /* every one is different, right? */
433 /* old apic/pin didn't exist, so just add new ones */
434 add_pin_to_irq_node(data, node, newapic, newpin);
437 static void io_apic_modify_irq(struct mp_chip_data *data,
438 int mask_and, int mask_or,
439 void (*final)(struct irq_pin_list *entry))
441 union entry_union eu;
442 struct irq_pin_list *entry;
444 eu.entry = data->entry;
447 data->entry = eu.entry;
449 for_each_irq_pin(entry, data->irq_2_pin) {
450 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
456 static void io_apic_sync(struct irq_pin_list *entry)
459 * Synchronize the IO-APIC and the CPU by doing
460 * a dummy read from the IO-APIC
462 struct io_apic __iomem *io_apic;
464 io_apic = io_apic_base(entry->apic);
465 readl(&io_apic->data);
468 static void mask_ioapic_irq(struct irq_data *irq_data)
470 struct mp_chip_data *data = irq_data->chip_data;
473 raw_spin_lock_irqsave(&ioapic_lock, flags);
474 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
475 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
478 static void __unmask_ioapic(struct mp_chip_data *data)
480 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
483 static void unmask_ioapic_irq(struct irq_data *irq_data)
485 struct mp_chip_data *data = irq_data->chip_data;
488 raw_spin_lock_irqsave(&ioapic_lock, flags);
489 __unmask_ioapic(data);
490 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
494 * IO-APIC versions below 0x20 don't support EOI register.
495 * For the record, here is the information about various versions:
497 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
498 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
501 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
502 * version as 0x2. This is an error with documentation and these ICH chips
503 * use io-apic's of version 0x20.
505 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
506 * Otherwise, we simulate the EOI message manually by changing the trigger
507 * mode to edge and then back to level, with RTE being masked during this.
509 static void __eoi_ioapic_pin(int apic, int pin, int vector)
511 if (mpc_ioapic_ver(apic) >= 0x20) {
512 io_apic_eoi(apic, vector);
514 struct IO_APIC_route_entry entry, entry1;
516 entry = entry1 = __ioapic_read_entry(apic, pin);
519 * Mask the entry and change the trigger mode to edge.
521 entry1.mask = IOAPIC_MASKED;
522 entry1.trigger = IOAPIC_EDGE;
524 __ioapic_write_entry(apic, pin, entry1);
527 * Restore the previous level triggered entry.
529 __ioapic_write_entry(apic, pin, entry);
533 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
536 struct irq_pin_list *entry;
538 raw_spin_lock_irqsave(&ioapic_lock, flags);
539 for_each_irq_pin(entry, data->irq_2_pin)
540 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
541 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
544 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
546 struct IO_APIC_route_entry entry;
548 /* Check delivery_mode to be sure we're not clearing an SMI pin */
549 entry = ioapic_read_entry(apic, pin);
550 if (entry.delivery_mode == dest_SMI)
554 * Make sure the entry is masked and re-read the contents to check
555 * if it is a level triggered pin and if the remote-IRR is set.
557 if (entry.mask == IOAPIC_UNMASKED) {
558 entry.mask = IOAPIC_MASKED;
559 ioapic_write_entry(apic, pin, entry);
560 entry = ioapic_read_entry(apic, pin);
567 * Make sure the trigger mode is set to level. Explicit EOI
568 * doesn't clear the remote-IRR if the trigger mode is not
571 if (entry.trigger == IOAPIC_EDGE) {
572 entry.trigger = IOAPIC_LEVEL;
573 ioapic_write_entry(apic, pin, entry);
575 raw_spin_lock_irqsave(&ioapic_lock, flags);
576 __eoi_ioapic_pin(apic, pin, entry.vector);
577 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
581 * Clear the rest of the bits in the IO-APIC RTE except for the mask
584 ioapic_mask_entry(apic, pin);
585 entry = ioapic_read_entry(apic, pin);
587 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
588 mpc_ioapic_id(apic), pin);
591 void clear_IO_APIC (void)
595 for_each_ioapic_pin(apic, pin)
596 clear_IO_APIC_pin(apic, pin);
601 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
602 * specific CPU-side IRQs.
606 static int pirq_entries[MAX_PIRQS] = {
607 [0 ... MAX_PIRQS - 1] = -1
610 static int __init ioapic_pirq_setup(char *str)
613 int ints[MAX_PIRQS+1];
615 get_options(str, ARRAY_SIZE(ints), ints);
617 apic_printk(APIC_VERBOSE, KERN_INFO
618 "PIRQ redirection, working around broken MP-BIOS.\n");
620 if (ints[0] < MAX_PIRQS)
623 for (i = 0; i < max; i++) {
624 apic_printk(APIC_VERBOSE, KERN_DEBUG
625 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
627 * PIRQs are mapped upside down, usually.
629 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
634 __setup("pirq=", ioapic_pirq_setup);
635 #endif /* CONFIG_X86_32 */
638 * Saves all the IO-APIC RTE's
640 int save_ioapic_entries(void)
645 for_each_ioapic(apic) {
646 if (!ioapics[apic].saved_registers) {
651 for_each_pin(apic, pin)
652 ioapics[apic].saved_registers[pin] =
653 ioapic_read_entry(apic, pin);
660 * Mask all IO APIC entries.
662 void mask_ioapic_entries(void)
666 for_each_ioapic(apic) {
667 if (!ioapics[apic].saved_registers)
670 for_each_pin(apic, pin) {
671 struct IO_APIC_route_entry entry;
673 entry = ioapics[apic].saved_registers[pin];
674 if (entry.mask == IOAPIC_UNMASKED) {
675 entry.mask = IOAPIC_MASKED;
676 ioapic_write_entry(apic, pin, entry);
683 * Restore IO APIC entries which was saved in the ioapic structure.
685 int restore_ioapic_entries(void)
689 for_each_ioapic(apic) {
690 if (!ioapics[apic].saved_registers)
693 for_each_pin(apic, pin)
694 ioapic_write_entry(apic, pin,
695 ioapics[apic].saved_registers[pin]);
701 * Find the IRQ entry number of a certain pin.
703 static int find_irq_entry(int ioapic_idx, int pin, int type)
707 for (i = 0; i < mp_irq_entries; i++)
708 if (mp_irqs[i].irqtype == type &&
709 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
710 mp_irqs[i].dstapic == MP_APIC_ALL) &&
711 mp_irqs[i].dstirq == pin)
718 * Find the pin to which IRQ[irq] (ISA) is connected
720 static int __init find_isa_irq_pin(int irq, int type)
724 for (i = 0; i < mp_irq_entries; i++) {
725 int lbus = mp_irqs[i].srcbus;
727 if (test_bit(lbus, mp_bus_not_pci) &&
728 (mp_irqs[i].irqtype == type) &&
729 (mp_irqs[i].srcbusirq == irq))
731 return mp_irqs[i].dstirq;
736 static int __init find_isa_irq_apic(int irq, int type)
740 for (i = 0; i < mp_irq_entries; i++) {
741 int lbus = mp_irqs[i].srcbus;
743 if (test_bit(lbus, mp_bus_not_pci) &&
744 (mp_irqs[i].irqtype == type) &&
745 (mp_irqs[i].srcbusirq == irq))
749 if (i < mp_irq_entries) {
752 for_each_ioapic(ioapic_idx)
753 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
762 * EISA Edge/Level control register, ELCR
764 static int EISA_ELCR(unsigned int irq)
766 if (irq < nr_legacy_irqs()) {
767 unsigned int port = 0x4d0 + (irq >> 3);
768 return (inb(port) >> (irq & 7)) & 1;
770 apic_printk(APIC_VERBOSE, KERN_INFO
771 "Broken MPtable reports ISA irq %d\n", irq);
777 /* ISA interrupts are always active high edge triggered,
778 * when listed as conforming in the MP table. */
780 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
781 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
783 /* EISA interrupts are always polarity zero and can be edge or level
784 * trigger depending on the ELCR value. If an interrupt is listed as
785 * EISA conforming in the MP table, that means its trigger type must
786 * be read in from the ELCR */
788 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
789 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
791 /* PCI interrupts are always active low level triggered,
792 * when listed as conforming in the MP table. */
794 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
795 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
797 static int irq_polarity(int idx)
799 int bus = mp_irqs[idx].srcbus;
802 * Determine IRQ line polarity (high active or low active):
804 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
805 case MP_IRQPOL_DEFAULT:
806 /* conforms to spec, ie. bus-type dependent polarity */
807 if (test_bit(bus, mp_bus_not_pci))
808 return default_ISA_polarity(idx);
810 return default_PCI_polarity(idx);
811 case MP_IRQPOL_ACTIVE_HIGH:
812 return IOAPIC_POL_HIGH;
813 case MP_IRQPOL_RESERVED:
814 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
815 case MP_IRQPOL_ACTIVE_LOW:
816 default: /* Pointless default required due to do gcc stupidity */
817 return IOAPIC_POL_LOW;
822 static int eisa_irq_trigger(int idx, int bus, int trigger)
824 switch (mp_bus_id_to_type[bus]) {
829 return default_EISA_trigger(idx);
831 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
835 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
841 static int irq_trigger(int idx)
843 int bus = mp_irqs[idx].srcbus;
847 * Determine IRQ trigger mode (edge or level sensitive):
849 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
850 case MP_IRQTRIG_DEFAULT:
851 /* conforms to spec, ie. bus-type dependent trigger mode */
852 if (test_bit(bus, mp_bus_not_pci))
853 trigger = default_ISA_trigger(idx);
855 trigger = default_PCI_trigger(idx);
856 /* Take EISA into account */
857 return eisa_irq_trigger(idx, bus, trigger);
858 case MP_IRQTRIG_EDGE:
860 case MP_IRQTRIG_RESERVED:
861 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
862 case MP_IRQTRIG_LEVEL:
863 default: /* Pointless default required due to do gcc stupidity */
868 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
869 int trigger, int polarity)
871 init_irq_alloc_info(info, NULL);
872 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
873 info->ioapic_node = node;
874 info->ioapic_trigger = trigger;
875 info->ioapic_polarity = polarity;
876 info->ioapic_valid = 1;
880 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
883 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
884 struct irq_alloc_info *src,
885 u32 gsi, int ioapic_idx, int pin)
887 int trigger, polarity;
889 copy_irq_alloc_info(dst, src);
890 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
891 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
892 dst->ioapic_pin = pin;
893 dst->ioapic_valid = 1;
894 if (src && src->ioapic_valid) {
895 dst->ioapic_node = src->ioapic_node;
896 dst->ioapic_trigger = src->ioapic_trigger;
897 dst->ioapic_polarity = src->ioapic_polarity;
899 dst->ioapic_node = NUMA_NO_NODE;
900 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
901 dst->ioapic_trigger = trigger;
902 dst->ioapic_polarity = polarity;
905 * PCI interrupts are always active low level
908 dst->ioapic_trigger = IOAPIC_LEVEL;
909 dst->ioapic_polarity = IOAPIC_POL_LOW;
914 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
916 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
919 static void mp_register_handler(unsigned int irq, unsigned long trigger)
921 irq_flow_handler_t hdl;
925 irq_set_status_flags(irq, IRQ_LEVEL);
928 irq_clear_status_flags(irq, IRQ_LEVEL);
932 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
933 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
936 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
938 struct mp_chip_data *data = irq_get_chip_data(irq);
941 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
942 * and polarity attirbutes. So allow the first user to reprogram the
943 * pin with real trigger and polarity attributes.
945 if (irq < nr_legacy_irqs() && data->count == 1) {
946 if (info->ioapic_trigger != data->trigger)
947 mp_register_handler(irq, info->ioapic_trigger);
948 data->entry.trigger = data->trigger = info->ioapic_trigger;
949 data->entry.polarity = data->polarity = info->ioapic_polarity;
952 return data->trigger == info->ioapic_trigger &&
953 data->polarity == info->ioapic_polarity;
956 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
957 struct irq_alloc_info *info)
961 int type = ioapics[ioapic].irqdomain_cfg.type;
964 case IOAPIC_DOMAIN_LEGACY:
966 * Dynamically allocate IRQ number for non-ISA IRQs in the first
967 * 16 GSIs on some weird platforms.
969 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
971 legacy = mp_is_legacy_irq(irq);
973 case IOAPIC_DOMAIN_STRICT:
976 case IOAPIC_DOMAIN_DYNAMIC:
979 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
983 return __irq_domain_alloc_irqs(domain, irq, 1,
984 ioapic_alloc_attr_node(info),
989 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
990 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
991 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
992 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
993 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
994 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
995 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
996 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
998 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
999 int irq, int ioapic, int pin,
1000 struct irq_alloc_info *info)
1002 struct mp_chip_data *data;
1003 struct irq_data *irq_data = irq_get_irq_data(irq);
1004 int node = ioapic_alloc_attr_node(info);
1007 * Legacy ISA IRQ has already been allocated, just add pin to
1008 * the pin list assoicated with this IRQ and program the IOAPIC
1009 * entry. The IOAPIC entry
1011 if (irq_data && irq_data->parent_data) {
1012 if (!mp_check_pin_attr(irq, info))
1014 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1018 info->flags |= X86_IRQ_ALLOC_LEGACY;
1019 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1022 irq_data = irq_domain_get_irq_data(domain, irq);
1023 data = irq_data->chip_data;
1024 data->isa_irq = true;
1031 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1032 unsigned int flags, struct irq_alloc_info *info)
1035 bool legacy = false;
1036 struct irq_alloc_info tmp;
1037 struct mp_chip_data *data;
1038 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1043 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1044 irq = mp_irqs[idx].srcbusirq;
1045 legacy = mp_is_legacy_irq(irq);
1047 * IRQ2 is unusable for historical reasons on systems which
1048 * have a legacy PIC. See the comment vs. IRQ2 further down.
1050 * If this gets removed at some point then the related code
1051 * in lapic_assign_system_vectors() needs to be adjusted as
1054 if (legacy && irq == PIC_CASCADE_IR)
1058 mutex_lock(&ioapic_mutex);
1059 if (!(flags & IOAPIC_MAP_ALLOC)) {
1061 irq = irq_find_mapping(domain, pin);
1066 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1068 irq = alloc_isa_irq_from_domain(domain, irq,
1070 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1071 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1072 else if (!mp_check_pin_attr(irq, &tmp))
1075 data = irq_get_chip_data(irq);
1079 mutex_unlock(&ioapic_mutex);
1084 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1086 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1089 * Debugging check, we are in big trouble if this message pops up!
1091 if (mp_irqs[idx].dstirq != pin)
1092 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1094 #ifdef CONFIG_X86_32
1096 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1098 if ((pin >= 16) && (pin <= 23)) {
1099 if (pirq_entries[pin-16] != -1) {
1100 if (!pirq_entries[pin-16]) {
1101 apic_printk(APIC_VERBOSE, KERN_DEBUG
1102 "disabling PIRQ%d\n", pin-16);
1104 int irq = pirq_entries[pin-16];
1105 apic_printk(APIC_VERBOSE, KERN_DEBUG
1106 "using PIRQ%d -> IRQ %d\n",
1114 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1117 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1119 int ioapic, pin, idx;
1121 ioapic = mp_find_ioapic(gsi);
1125 pin = mp_find_ioapic_pin(ioapic, gsi);
1126 idx = find_irq_entry(ioapic, pin, mp_INT);
1127 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1130 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1133 void mp_unmap_irq(int irq)
1135 struct irq_data *irq_data = irq_get_irq_data(irq);
1136 struct mp_chip_data *data;
1138 if (!irq_data || !irq_data->domain)
1141 data = irq_data->chip_data;
1142 if (!data || data->isa_irq)
1145 mutex_lock(&ioapic_mutex);
1146 if (--data->count == 0)
1147 irq_domain_free_irqs(irq, 1);
1148 mutex_unlock(&ioapic_mutex);
1152 * Find a specific PCI IRQ entry.
1153 * Not an __init, possibly needed by modules
1155 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1157 int irq, i, best_ioapic = -1, best_idx = -1;
1159 apic_printk(APIC_DEBUG,
1160 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1162 if (test_bit(bus, mp_bus_not_pci)) {
1163 apic_printk(APIC_VERBOSE,
1164 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1168 for (i = 0; i < mp_irq_entries; i++) {
1169 int lbus = mp_irqs[i].srcbus;
1170 int ioapic_idx, found = 0;
1172 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1173 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1176 for_each_ioapic(ioapic_idx)
1177 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1178 mp_irqs[i].dstapic == MP_APIC_ALL) {
1186 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1187 if (irq > 0 && !IO_APIC_IRQ(irq))
1190 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1192 best_ioapic = ioapic_idx;
1197 * Use the first all-but-pin matching entry as a
1198 * best-guess fuzzy result for broken mptables.
1202 best_ioapic = ioapic_idx;
1209 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1212 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1214 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1216 static void __init setup_IO_APIC_irqs(void)
1218 unsigned int ioapic, pin;
1221 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1223 for_each_ioapic_pin(ioapic, pin) {
1224 idx = find_irq_entry(ioapic, pin, mp_INT);
1226 apic_printk(APIC_VERBOSE,
1227 KERN_DEBUG " apic %d pin %d not connected\n",
1228 mpc_ioapic_id(ioapic), pin);
1230 pin_2_irq(idx, ioapic, pin,
1231 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1235 void ioapic_zap_locks(void)
1237 raw_spin_lock_init(&ioapic_lock);
1240 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1244 struct IO_APIC_route_entry entry;
1245 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1247 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1248 for (i = 0; i <= nr_entries; i++) {
1249 entry = ioapic_read_entry(apic, i);
1250 snprintf(buf, sizeof(buf),
1251 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1253 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1254 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1255 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1256 entry.vector, entry.irr, entry.delivery_status);
1257 if (ir_entry->format)
1258 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1259 buf, (ir_entry->index2 << 15) | ir_entry->index,
1262 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1264 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1265 "logical " : "physical",
1266 entry.dest, entry.delivery_mode);
1270 static void __init print_IO_APIC(int ioapic_idx)
1272 union IO_APIC_reg_00 reg_00;
1273 union IO_APIC_reg_01 reg_01;
1274 union IO_APIC_reg_02 reg_02;
1275 union IO_APIC_reg_03 reg_03;
1276 unsigned long flags;
1278 raw_spin_lock_irqsave(&ioapic_lock, flags);
1279 reg_00.raw = io_apic_read(ioapic_idx, 0);
1280 reg_01.raw = io_apic_read(ioapic_idx, 1);
1281 if (reg_01.bits.version >= 0x10)
1282 reg_02.raw = io_apic_read(ioapic_idx, 2);
1283 if (reg_01.bits.version >= 0x20)
1284 reg_03.raw = io_apic_read(ioapic_idx, 3);
1285 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1287 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1288 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1289 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1290 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1291 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1293 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1294 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1295 reg_01.bits.entries);
1297 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1298 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1299 reg_01.bits.version);
1302 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1303 * but the value of reg_02 is read as the previous read register
1304 * value, so ignore it if reg_02 == reg_01.
1306 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1307 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1308 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1312 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1313 * or reg_03, but the value of reg_0[23] is read as the previous read
1314 * register value, so ignore it if reg_03 == reg_0[12].
1316 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1317 reg_03.raw != reg_01.raw) {
1318 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1319 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1322 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1323 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1326 void __init print_IO_APICs(void)
1331 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1332 for_each_ioapic(ioapic_idx)
1333 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1334 mpc_ioapic_id(ioapic_idx),
1335 ioapics[ioapic_idx].nr_registers);
1338 * We are a bit conservative about what we expect. We have to
1339 * know about every hardware change ASAP.
1341 printk(KERN_INFO "testing the IO APIC.......................\n");
1343 for_each_ioapic(ioapic_idx)
1344 print_IO_APIC(ioapic_idx);
1346 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1347 for_each_active_irq(irq) {
1348 struct irq_pin_list *entry;
1349 struct irq_chip *chip;
1350 struct mp_chip_data *data;
1352 chip = irq_get_chip(irq);
1353 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1355 data = irq_get_chip_data(irq);
1358 if (list_empty(&data->irq_2_pin))
1361 printk(KERN_DEBUG "IRQ%d ", irq);
1362 for_each_irq_pin(entry, data->irq_2_pin)
1363 pr_cont("-> %d:%d", entry->apic, entry->pin);
1367 printk(KERN_INFO ".................................... done.\n");
1370 /* Where if anywhere is the i8259 connect in external int mode */
1371 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1373 void __init enable_IO_APIC(void)
1375 int i8259_apic, i8259_pin;
1378 if (skip_ioapic_setup)
1381 if (!nr_legacy_irqs() || !nr_ioapics)
1384 for_each_ioapic_pin(apic, pin) {
1385 /* See if any of the pins is in ExtINT mode */
1386 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1388 /* If the interrupt line is enabled and in ExtInt mode
1389 * I have found the pin where the i8259 is connected.
1391 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1392 ioapic_i8259.apic = apic;
1393 ioapic_i8259.pin = pin;
1398 /* Look to see what if the MP table has reported the ExtINT */
1399 /* If we could not find the appropriate pin by looking at the ioapic
1400 * the i8259 probably is not connected the ioapic but give the
1401 * mptable a chance anyway.
1403 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1404 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1405 /* Trust the MP table if nothing is setup in the hardware */
1406 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1407 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1408 ioapic_i8259.pin = i8259_pin;
1409 ioapic_i8259.apic = i8259_apic;
1411 /* Complain if the MP table and the hardware disagree */
1412 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1413 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1415 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1419 * Do not trust the IO-APIC being empty at bootup
1424 void native_restore_boot_irq_mode(void)
1427 * If the i8259 is routed through an IOAPIC
1428 * Put that IOAPIC in virtual wire mode
1429 * so legacy interrupts can be delivered.
1431 if (ioapic_i8259.pin != -1) {
1432 struct IO_APIC_route_entry entry;
1434 memset(&entry, 0, sizeof(entry));
1435 entry.mask = IOAPIC_UNMASKED;
1436 entry.trigger = IOAPIC_EDGE;
1437 entry.polarity = IOAPIC_POL_HIGH;
1438 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1439 entry.delivery_mode = dest_ExtINT;
1440 entry.dest = read_apic_id();
1443 * Add it to the IO-APIC irq-routing table:
1445 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1448 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1449 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1452 void restore_boot_irq_mode(void)
1454 if (!nr_legacy_irqs())
1457 x86_apic_ops.restore();
1460 #ifdef CONFIG_X86_32
1462 * function to set the IO-APIC physical IDs based on the
1463 * values stored in the MPC table.
1465 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1467 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1469 union IO_APIC_reg_00 reg_00;
1470 physid_mask_t phys_id_present_map;
1473 unsigned char old_id;
1474 unsigned long flags;
1477 * This is broken; anything with a real cpu count has to
1478 * circumvent this idiocy regardless.
1480 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1483 * Set the IOAPIC ID to the value stored in the MPC table.
1485 for_each_ioapic(ioapic_idx) {
1486 /* Read the register 0 value */
1487 raw_spin_lock_irqsave(&ioapic_lock, flags);
1488 reg_00.raw = io_apic_read(ioapic_idx, 0);
1489 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1491 old_id = mpc_ioapic_id(ioapic_idx);
1493 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1494 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1495 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1496 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1498 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1502 * Sanity check, is the ID really free? Every APIC in a
1503 * system must have a unique ID or we get lots of nice
1504 * 'stuck on smp_invalidate_needed IPI wait' messages.
1506 if (apic->check_apicid_used(&phys_id_present_map,
1507 mpc_ioapic_id(ioapic_idx))) {
1508 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1509 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1510 for (i = 0; i < get_physical_broadcast(); i++)
1511 if (!physid_isset(i, phys_id_present_map))
1513 if (i >= get_physical_broadcast())
1514 panic("Max APIC ID exceeded!\n");
1515 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1517 physid_set(i, phys_id_present_map);
1518 ioapics[ioapic_idx].mp_config.apicid = i;
1521 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1523 apic_printk(APIC_VERBOSE, "Setting %d in the "
1524 "phys_id_present_map\n",
1525 mpc_ioapic_id(ioapic_idx));
1526 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1530 * We need to adjust the IRQ routing table
1531 * if the ID changed.
1533 if (old_id != mpc_ioapic_id(ioapic_idx))
1534 for (i = 0; i < mp_irq_entries; i++)
1535 if (mp_irqs[i].dstapic == old_id)
1537 = mpc_ioapic_id(ioapic_idx);
1540 * Update the ID register according to the right value
1541 * from the MPC table if they are different.
1543 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1546 apic_printk(APIC_VERBOSE, KERN_INFO
1547 "...changing IO-APIC physical APIC ID to %d ...",
1548 mpc_ioapic_id(ioapic_idx));
1550 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1551 raw_spin_lock_irqsave(&ioapic_lock, flags);
1552 io_apic_write(ioapic_idx, 0, reg_00.raw);
1553 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1558 raw_spin_lock_irqsave(&ioapic_lock, flags);
1559 reg_00.raw = io_apic_read(ioapic_idx, 0);
1560 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1561 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1562 pr_cont("could not set ID!\n");
1564 apic_printk(APIC_VERBOSE, " ok.\n");
1568 void __init setup_ioapic_ids_from_mpc(void)
1574 * Don't check I/O APIC IDs for xAPIC systems. They have
1575 * no meaning without the serial APIC bus.
1577 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1578 || APIC_XAPIC(boot_cpu_apic_version))
1580 setup_ioapic_ids_from_mpc_nocheck();
1584 int no_timer_check __initdata;
1586 static int __init notimercheck(char *s)
1591 __setup("no_timer_check", notimercheck);
1593 static void __init delay_with_tsc(void)
1595 unsigned long long start, now;
1596 unsigned long end = jiffies + 4;
1601 * We don't know the TSC frequency yet, but waiting for
1602 * 40000000000/HZ TSC cycles is safe:
1603 * 4 GHz == 10 jiffies
1604 * 1 GHz == 40 jiffies
1609 } while ((now - start) < 40000000000ULL / HZ &&
1610 time_before_eq(jiffies, end));
1613 static void __init delay_without_tsc(void)
1615 unsigned long end = jiffies + 4;
1619 * We don't know any frequency yet, but waiting for
1620 * 40940000000/HZ cycles is safe:
1621 * 4 GHz == 10 jiffies
1622 * 1 GHz == 40 jiffies
1623 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1626 __delay(((1U << band++) * 10000000UL) / HZ);
1627 } while (band < 12 && time_before_eq(jiffies, end));
1631 * There is a nasty bug in some older SMP boards, their mptable lies
1632 * about the timer IRQ. We do the following to work around the situation:
1634 * - timer IRQ defaults to IO-APIC IRQ
1635 * - if this function detects that timer IRQs are defunct, then we fall
1636 * back to ISA timer IRQs
1638 static int __init timer_irq_works(void)
1640 unsigned long t1 = jiffies;
1641 unsigned long flags;
1646 local_save_flags(flags);
1649 if (boot_cpu_has(X86_FEATURE_TSC))
1652 delay_without_tsc();
1654 local_irq_restore(flags);
1657 * Expect a few ticks at least, to be sure some possible
1658 * glue logic does not lock up after one or two first
1659 * ticks in a non-ExtINT mode. Also the local APIC
1660 * might have cached one ExtINT interrupt. Finally, at
1661 * least one tick may be lost due to delays.
1665 if (time_after(jiffies, t1 + 4))
1671 * In the SMP+IOAPIC case it might happen that there are an unspecified
1672 * number of pending IRQ events unhandled. These cases are very rare,
1673 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1674 * better to do it this way as thus we do not have to be aware of
1675 * 'pending' interrupts in the IRQ path, except at this point.
1678 * Edge triggered needs to resend any interrupt
1679 * that was delayed but this is now handled in the device
1684 * Starting up a edge-triggered IO-APIC interrupt is
1685 * nasty - we need to make sure that we get the edge.
1686 * If it is already asserted for some reason, we need
1687 * return 1 to indicate that is was pending.
1689 * This is not complete - we should be able to fake
1690 * an edge even if it isn't on the 8259A...
1692 static unsigned int startup_ioapic_irq(struct irq_data *data)
1694 int was_pending = 0, irq = data->irq;
1695 unsigned long flags;
1697 raw_spin_lock_irqsave(&ioapic_lock, flags);
1698 if (irq < nr_legacy_irqs()) {
1699 legacy_pic->mask(irq);
1700 if (legacy_pic->irq_pending(irq))
1703 __unmask_ioapic(data->chip_data);
1704 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1709 atomic_t irq_mis_count;
1711 #ifdef CONFIG_GENERIC_PENDING_IRQ
1712 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1714 struct irq_pin_list *entry;
1715 unsigned long flags;
1717 raw_spin_lock_irqsave(&ioapic_lock, flags);
1718 for_each_irq_pin(entry, data->irq_2_pin) {
1723 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1724 /* Is the remote IRR bit set? */
1725 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1726 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1730 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1735 static inline bool ioapic_irqd_mask(struct irq_data *data)
1737 /* If we are moving the IRQ we need to mask it */
1738 if (unlikely(irqd_is_setaffinity_pending(data))) {
1739 if (!irqd_irq_masked(data))
1740 mask_ioapic_irq(data);
1746 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1748 if (unlikely(masked)) {
1749 /* Only migrate the irq if the ack has been received.
1751 * On rare occasions the broadcast level triggered ack gets
1752 * delayed going to ioapics, and if we reprogram the
1753 * vector while Remote IRR is still set the irq will never
1756 * To prevent this scenario we read the Remote IRR bit
1757 * of the ioapic. This has two effects.
1758 * - On any sane system the read of the ioapic will
1759 * flush writes (and acks) going to the ioapic from
1761 * - We get to see if the ACK has actually been delivered.
1763 * Based on failed experiments of reprogramming the
1764 * ioapic entry from outside of irq context starting
1765 * with masking the ioapic entry and then polling until
1766 * Remote IRR was clear before reprogramming the
1767 * ioapic I don't trust the Remote IRR bit to be
1768 * completey accurate.
1770 * However there appears to be no other way to plug
1771 * this race, so if the Remote IRR bit is not
1772 * accurate and is causing problems then it is a hardware bug
1773 * and you can go talk to the chipset vendor about it.
1775 if (!io_apic_level_ack_pending(data->chip_data))
1776 irq_move_masked_irq(data);
1777 /* If the IRQ is masked in the core, leave it: */
1778 if (!irqd_irq_masked(data))
1779 unmask_ioapic_irq(data);
1783 static inline bool ioapic_irqd_mask(struct irq_data *data)
1787 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1792 static void ioapic_ack_level(struct irq_data *irq_data)
1794 struct irq_cfg *cfg = irqd_cfg(irq_data);
1799 irq_complete_move(cfg);
1800 masked = ioapic_irqd_mask(irq_data);
1803 * It appears there is an erratum which affects at least version 0x11
1804 * of I/O APIC (that's the 82093AA and cores integrated into various
1805 * chipsets). Under certain conditions a level-triggered interrupt is
1806 * erroneously delivered as edge-triggered one but the respective IRR
1807 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1808 * message but it will never arrive and further interrupts are blocked
1809 * from the source. The exact reason is so far unknown, but the
1810 * phenomenon was observed when two consecutive interrupt requests
1811 * from a given source get delivered to the same CPU and the source is
1812 * temporarily disabled in between.
1814 * A workaround is to simulate an EOI message manually. We achieve it
1815 * by setting the trigger mode to edge and then to level when the edge
1816 * trigger mode gets detected in the TMR of a local APIC for a
1817 * level-triggered interrupt. We mask the source for the time of the
1818 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1819 * The idea is from Manfred Spraul. --macro
1821 * Also in the case when cpu goes offline, fixup_irqs() will forward
1822 * any unhandled interrupt on the offlined cpu to the new cpu
1823 * destination that is handling the corresponding interrupt. This
1824 * interrupt forwarding is done via IPI's. Hence, in this case also
1825 * level-triggered io-apic interrupt will be seen as an edge
1826 * interrupt in the IRR. And we can't rely on the cpu's EOI
1827 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1828 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1829 * supporting EOI register, we do an explicit EOI to clear the
1830 * remote IRR and on IO-APIC's which don't have an EOI register,
1831 * we use the above logic (mask+edge followed by unmask+level) from
1832 * Manfred Spraul to clear the remote IRR.
1835 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1838 * We must acknowledge the irq before we move it or the acknowledge will
1839 * not propagate properly.
1844 * Tail end of clearing remote IRR bit (either by delivering the EOI
1845 * message via io-apic EOI register write or simulating it using
1846 * mask+edge followed by unnask+level logic) manually when the
1847 * level triggered interrupt is seen as the edge triggered interrupt
1850 if (!(v & (1 << (i & 0x1f)))) {
1851 atomic_inc(&irq_mis_count);
1852 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1855 ioapic_irqd_unmask(irq_data, masked);
1858 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1860 struct mp_chip_data *data = irq_data->chip_data;
1863 * Intr-remapping uses pin number as the virtual vector
1864 * in the RTE. Actual vector is programmed in
1865 * intr-remapping table entry. Hence for the io-apic
1866 * EOI we use the pin number.
1868 apic_ack_irq(irq_data);
1869 eoi_ioapic_pin(data->entry.vector, data);
1872 static void ioapic_configure_entry(struct irq_data *irqd)
1874 struct mp_chip_data *mpd = irqd->chip_data;
1875 struct irq_cfg *cfg = irqd_cfg(irqd);
1876 struct irq_pin_list *entry;
1879 * Only update when the parent is the vector domain, don't touch it
1880 * if the parent is the remapping domain. Check the installed
1881 * ioapic chip to verify that.
1883 if (irqd->chip == &ioapic_chip) {
1884 mpd->entry.dest = cfg->dest_apicid;
1885 mpd->entry.vector = cfg->vector;
1887 for_each_irq_pin(entry, mpd->irq_2_pin)
1888 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1891 static int ioapic_set_affinity(struct irq_data *irq_data,
1892 const struct cpumask *mask, bool force)
1894 struct irq_data *parent = irq_data->parent_data;
1895 unsigned long flags;
1898 ret = parent->chip->irq_set_affinity(parent, mask, force);
1899 raw_spin_lock_irqsave(&ioapic_lock, flags);
1900 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1901 ioapic_configure_entry(irq_data);
1902 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1908 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1909 * be in flight, but not yet serviced by the target CPU. That means
1910 * __synchronize_hardirq() would return and claim that everything is calmed
1911 * down. So free_irq() would proceed and deactivate the interrupt and free
1914 * Once the target CPU comes around to service it it will find a cleared
1915 * vector and complain. While the spurious interrupt is harmless, the full
1916 * release of resources might prevent the interrupt from being acknowledged
1917 * which keeps the hardware in a weird state.
1919 * Verify that the corresponding Remote-IRR bits are clear.
1921 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1922 enum irqchip_irq_state which,
1925 struct mp_chip_data *mcd = irqd->chip_data;
1926 struct IO_APIC_route_entry rentry;
1927 struct irq_pin_list *p;
1929 if (which != IRQCHIP_STATE_ACTIVE)
1933 raw_spin_lock(&ioapic_lock);
1934 for_each_irq_pin(p, mcd->irq_2_pin) {
1935 rentry = __ioapic_read_entry(p->apic, p->pin);
1937 * The remote IRR is only valid in level trigger mode. It's
1938 * meaning is undefined for edge triggered interrupts and
1939 * irrelevant because the IO-APIC treats them as fire and
1942 if (rentry.irr && rentry.trigger) {
1947 raw_spin_unlock(&ioapic_lock);
1951 static struct irq_chip ioapic_chip __read_mostly = {
1953 .irq_startup = startup_ioapic_irq,
1954 .irq_mask = mask_ioapic_irq,
1955 .irq_unmask = unmask_ioapic_irq,
1956 .irq_ack = irq_chip_ack_parent,
1957 .irq_eoi = ioapic_ack_level,
1958 .irq_set_affinity = ioapic_set_affinity,
1959 .irq_retrigger = irq_chip_retrigger_hierarchy,
1960 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1961 .flags = IRQCHIP_SKIP_SET_WAKE |
1962 IRQCHIP_AFFINITY_PRE_STARTUP,
1965 static struct irq_chip ioapic_ir_chip __read_mostly = {
1966 .name = "IR-IO-APIC",
1967 .irq_startup = startup_ioapic_irq,
1968 .irq_mask = mask_ioapic_irq,
1969 .irq_unmask = unmask_ioapic_irq,
1970 .irq_ack = irq_chip_ack_parent,
1971 .irq_eoi = ioapic_ir_ack_level,
1972 .irq_set_affinity = ioapic_set_affinity,
1973 .irq_retrigger = irq_chip_retrigger_hierarchy,
1974 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1975 .flags = IRQCHIP_SKIP_SET_WAKE |
1976 IRQCHIP_AFFINITY_PRE_STARTUP,
1979 static inline void init_IO_APIC_traps(void)
1981 struct irq_cfg *cfg;
1984 for_each_active_irq(irq) {
1986 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1988 * Hmm.. We don't have an entry for this,
1989 * so default to an old-fashioned 8259
1990 * interrupt if we can..
1992 if (irq < nr_legacy_irqs())
1993 legacy_pic->make_irq(irq);
1995 /* Strange. Oh, well.. */
1996 irq_set_chip(irq, &no_irq_chip);
2002 * The local APIC irq-chip implementation:
2005 static void mask_lapic_irq(struct irq_data *data)
2009 v = apic_read(APIC_LVT0);
2010 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2013 static void unmask_lapic_irq(struct irq_data *data)
2017 v = apic_read(APIC_LVT0);
2018 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2021 static void ack_lapic_irq(struct irq_data *data)
2026 static struct irq_chip lapic_chip __read_mostly = {
2027 .name = "local-APIC",
2028 .irq_mask = mask_lapic_irq,
2029 .irq_unmask = unmask_lapic_irq,
2030 .irq_ack = ack_lapic_irq,
2033 static void lapic_register_intr(int irq)
2035 irq_clear_status_flags(irq, IRQ_LEVEL);
2036 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2041 * This looks a bit hackish but it's about the only one way of sending
2042 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2043 * not support the ExtINT mode, unfortunately. We need to send these
2044 * cycles as some i82489DX-based boards have glue logic that keeps the
2045 * 8259A interrupt line asserted until INTA. --macro
2047 static inline void __init unlock_ExtINT_logic(void)
2050 struct IO_APIC_route_entry entry0, entry1;
2051 unsigned char save_control, save_freq_select;
2053 pin = find_isa_irq_pin(8, mp_INT);
2058 apic = find_isa_irq_apic(8, mp_INT);
2064 entry0 = ioapic_read_entry(apic, pin);
2065 clear_IO_APIC_pin(apic, pin);
2067 memset(&entry1, 0, sizeof(entry1));
2069 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2070 entry1.mask = IOAPIC_UNMASKED;
2071 entry1.dest = hard_smp_processor_id();
2072 entry1.delivery_mode = dest_ExtINT;
2073 entry1.polarity = entry0.polarity;
2074 entry1.trigger = IOAPIC_EDGE;
2077 ioapic_write_entry(apic, pin, entry1);
2079 save_control = CMOS_READ(RTC_CONTROL);
2080 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2081 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2083 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2088 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2092 CMOS_WRITE(save_control, RTC_CONTROL);
2093 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2094 clear_IO_APIC_pin(apic, pin);
2096 ioapic_write_entry(apic, pin, entry0);
2099 static int disable_timer_pin_1 __initdata;
2100 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2101 static int __init disable_timer_pin_setup(char *arg)
2103 disable_timer_pin_1 = 1;
2106 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2108 static int mp_alloc_timer_irq(int ioapic, int pin)
2111 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2114 struct irq_alloc_info info;
2116 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2117 info.ioapic_id = mpc_ioapic_id(ioapic);
2118 info.ioapic_pin = pin;
2119 mutex_lock(&ioapic_mutex);
2120 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2121 mutex_unlock(&ioapic_mutex);
2128 * This code may look a bit paranoid, but it's supposed to cooperate with
2129 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2130 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2131 * fanatically on his truly buggy board.
2133 * FIXME: really need to revamp this for all platforms.
2135 static inline void __init check_timer(void)
2137 struct irq_data *irq_data = irq_get_irq_data(0);
2138 struct mp_chip_data *data = irq_data->chip_data;
2139 struct irq_cfg *cfg = irqd_cfg(irq_data);
2140 int node = cpu_to_node(0);
2141 int apic1, pin1, apic2, pin2;
2142 unsigned long flags;
2145 local_irq_save(flags);
2148 * get/set the timer IRQ vector:
2150 legacy_pic->mask(0);
2153 * As IRQ0 is to be enabled in the 8259A, the virtual
2154 * wire has to be disabled in the local APIC. Also
2155 * timer interrupts need to be acknowledged manually in
2156 * the 8259A for the i82489DX when using the NMI
2157 * watchdog as that APIC treats NMIs as level-triggered.
2158 * The AEOI mode will finish them in the 8259A
2161 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2162 legacy_pic->init(1);
2164 pin1 = find_isa_irq_pin(0, mp_INT);
2165 apic1 = find_isa_irq_apic(0, mp_INT);
2166 pin2 = ioapic_i8259.pin;
2167 apic2 = ioapic_i8259.apic;
2169 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2170 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2171 cfg->vector, apic1, pin1, apic2, pin2);
2174 * Some BIOS writers are clueless and report the ExtINTA
2175 * I/O APIC input from the cascaded 8259A as the timer
2176 * interrupt input. So just in case, if only one pin
2177 * was found above, try it both directly and through the
2181 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2185 } else if (pin2 == -1) {
2191 /* Ok, does IRQ0 through the IOAPIC work? */
2193 mp_alloc_timer_irq(apic1, pin1);
2196 * for edge trigger, it's already unmasked,
2197 * so only need to unmask if it is level-trigger
2198 * do we really have level trigger timer?
2201 idx = find_irq_entry(apic1, pin1, mp_INT);
2202 if (idx != -1 && irq_trigger(idx))
2203 unmask_ioapic_irq(irq_get_irq_data(0));
2205 irq_domain_deactivate_irq(irq_data);
2206 irq_domain_activate_irq(irq_data, false);
2207 if (timer_irq_works()) {
2208 if (disable_timer_pin_1 > 0)
2209 clear_IO_APIC_pin(0, pin1);
2212 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2213 local_irq_disable();
2214 clear_IO_APIC_pin(apic1, pin1);
2216 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2217 "8254 timer not connected to IO-APIC\n");
2219 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2220 "(IRQ0) through the 8259A ...\n");
2221 apic_printk(APIC_QUIET, KERN_INFO
2222 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2224 * legacy devices should be connected to IO APIC #0
2226 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2227 irq_domain_deactivate_irq(irq_data);
2228 irq_domain_activate_irq(irq_data, false);
2229 legacy_pic->unmask(0);
2230 if (timer_irq_works()) {
2231 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2235 * Cleanup, just in case ...
2237 local_irq_disable();
2238 legacy_pic->mask(0);
2239 clear_IO_APIC_pin(apic2, pin2);
2240 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2243 apic_printk(APIC_QUIET, KERN_INFO
2244 "...trying to set up timer as Virtual Wire IRQ...\n");
2246 lapic_register_intr(0);
2247 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2248 legacy_pic->unmask(0);
2250 if (timer_irq_works()) {
2251 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2254 local_irq_disable();
2255 legacy_pic->mask(0);
2256 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2257 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2259 apic_printk(APIC_QUIET, KERN_INFO
2260 "...trying to set up timer as ExtINT IRQ...\n");
2262 legacy_pic->init(0);
2263 legacy_pic->make_irq(0);
2264 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2265 legacy_pic->unmask(0);
2267 unlock_ExtINT_logic();
2269 if (timer_irq_works()) {
2270 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2273 local_irq_disable();
2274 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2275 if (apic_is_x2apic_enabled())
2276 apic_printk(APIC_QUIET, KERN_INFO
2277 "Perhaps problem with the pre-enabled x2apic mode\n"
2278 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2279 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2280 "report. Then try booting with the 'noapic' option.\n");
2282 local_irq_restore(flags);
2286 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2287 * to devices. However there may be an I/O APIC pin available for
2288 * this interrupt regardless. The pin may be left unconnected, but
2289 * typically it will be reused as an ExtINT cascade interrupt for
2290 * the master 8259A. In the MPS case such a pin will normally be
2291 * reported as an ExtINT interrupt in the MP table. With ACPI
2292 * there is no provision for ExtINT interrupts, and in the absence
2293 * of an override it would be treated as an ordinary ISA I/O APIC
2294 * interrupt, that is edge-triggered and unmasked by default. We
2295 * used to do this, but it caused problems on some systems because
2296 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2297 * the same ExtINT cascade interrupt to drive the local APIC of the
2298 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2299 * the I/O APIC in all cases now. No actual device should request
2300 * it anyway. --macro
2302 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2304 static int mp_irqdomain_create(int ioapic)
2306 struct irq_alloc_info info;
2307 struct irq_domain *parent;
2308 int hwirqs = mp_ioapic_pin_count(ioapic);
2309 struct ioapic *ip = &ioapics[ioapic];
2310 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2311 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2312 struct fwnode_handle *fn;
2313 char *name = "IO-APIC";
2315 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2318 init_irq_alloc_info(&info, NULL);
2319 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2320 info.ioapic_id = mpc_ioapic_id(ioapic);
2321 parent = irq_remapping_get_ir_irq_domain(&info);
2323 parent = x86_vector_domain;
2325 name = "IO-APIC-IR";
2327 /* Handle device tree enumerated APICs proper */
2329 fn = of_node_to_fwnode(cfg->dev);
2331 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2336 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2337 (void *)(long)ioapic);
2339 if (!ip->irqdomain) {
2340 /* Release fw handle if it was allocated above */
2342 irq_domain_free_fwnode(fn);
2346 ip->irqdomain->parent = parent;
2348 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2349 cfg->type == IOAPIC_DOMAIN_STRICT)
2350 ioapic_dynirq_base = max(ioapic_dynirq_base,
2351 gsi_cfg->gsi_end + 1);
2356 static void ioapic_destroy_irqdomain(int idx)
2358 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2359 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2361 if (ioapics[idx].irqdomain) {
2362 irq_domain_remove(ioapics[idx].irqdomain);
2364 irq_domain_free_fwnode(fn);
2365 ioapics[idx].irqdomain = NULL;
2369 void __init setup_IO_APIC(void)
2373 if (skip_ioapic_setup || !nr_ioapics)
2376 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2378 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2379 for_each_ioapic(ioapic)
2380 BUG_ON(mp_irqdomain_create(ioapic));
2383 * Set up IO-APIC IRQ routing.
2385 x86_init.mpparse.setup_ioapic_ids();
2388 setup_IO_APIC_irqs();
2389 init_IO_APIC_traps();
2390 if (nr_legacy_irqs())
2393 ioapic_initialized = 1;
2396 static void resume_ioapic_id(int ioapic_idx)
2398 unsigned long flags;
2399 union IO_APIC_reg_00 reg_00;
2401 raw_spin_lock_irqsave(&ioapic_lock, flags);
2402 reg_00.raw = io_apic_read(ioapic_idx, 0);
2403 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2404 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2405 io_apic_write(ioapic_idx, 0, reg_00.raw);
2407 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2410 static void ioapic_resume(void)
2414 for_each_ioapic_reverse(ioapic_idx)
2415 resume_ioapic_id(ioapic_idx);
2417 restore_ioapic_entries();
2420 static struct syscore_ops ioapic_syscore_ops = {
2421 .suspend = save_ioapic_entries,
2422 .resume = ioapic_resume,
2425 static int __init ioapic_init_ops(void)
2427 register_syscore_ops(&ioapic_syscore_ops);
2432 device_initcall(ioapic_init_ops);
2434 static int io_apic_get_redir_entries(int ioapic)
2436 union IO_APIC_reg_01 reg_01;
2437 unsigned long flags;
2439 raw_spin_lock_irqsave(&ioapic_lock, flags);
2440 reg_01.raw = io_apic_read(ioapic, 1);
2441 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2443 /* The register returns the maximum index redir index
2444 * supported, which is one less than the total number of redir
2447 return reg_01.bits.entries + 1;
2450 unsigned int arch_dynirq_lower_bound(unsigned int from)
2453 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2454 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2456 if (!ioapic_initialized)
2459 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2460 * updated. So simply return @from if ioapic_dynirq_base == 0.
2462 return ioapic_dynirq_base ? : from;
2465 #ifdef CONFIG_X86_32
2466 static int io_apic_get_unique_id(int ioapic, int apic_id)
2468 union IO_APIC_reg_00 reg_00;
2469 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2471 unsigned long flags;
2475 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2476 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2477 * supports up to 16 on one shared APIC bus.
2479 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2480 * advantage of new APIC bus architecture.
2483 if (physids_empty(apic_id_map))
2484 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2486 raw_spin_lock_irqsave(&ioapic_lock, flags);
2487 reg_00.raw = io_apic_read(ioapic, 0);
2488 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2490 if (apic_id >= get_physical_broadcast()) {
2491 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2492 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2493 apic_id = reg_00.bits.ID;
2497 * Every APIC in a system must have a unique ID or we get lots of nice
2498 * 'stuck on smp_invalidate_needed IPI wait' messages.
2500 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2502 for (i = 0; i < get_physical_broadcast(); i++) {
2503 if (!apic->check_apicid_used(&apic_id_map, i))
2507 if (i == get_physical_broadcast())
2508 panic("Max apic_id exceeded!\n");
2510 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2511 "trying %d\n", ioapic, apic_id, i);
2516 apic->apicid_to_cpu_present(apic_id, &tmp);
2517 physids_or(apic_id_map, apic_id_map, tmp);
2519 if (reg_00.bits.ID != apic_id) {
2520 reg_00.bits.ID = apic_id;
2522 raw_spin_lock_irqsave(&ioapic_lock, flags);
2523 io_apic_write(ioapic, 0, reg_00.raw);
2524 reg_00.raw = io_apic_read(ioapic, 0);
2525 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2528 if (reg_00.bits.ID != apic_id) {
2529 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2535 apic_printk(APIC_VERBOSE, KERN_INFO
2536 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2541 static u8 io_apic_unique_id(int idx, u8 id)
2543 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2544 !APIC_XAPIC(boot_cpu_apic_version))
2545 return io_apic_get_unique_id(idx, id);
2550 static u8 io_apic_unique_id(int idx, u8 id)
2552 union IO_APIC_reg_00 reg_00;
2553 DECLARE_BITMAP(used, 256);
2554 unsigned long flags;
2558 bitmap_zero(used, 256);
2560 __set_bit(mpc_ioapic_id(i), used);
2562 /* Hand out the requested id if available */
2563 if (!test_bit(id, used))
2567 * Read the current id from the ioapic and keep it if
2570 raw_spin_lock_irqsave(&ioapic_lock, flags);
2571 reg_00.raw = io_apic_read(idx, 0);
2572 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2573 new_id = reg_00.bits.ID;
2574 if (!test_bit(new_id, used)) {
2575 apic_printk(APIC_VERBOSE, KERN_INFO
2576 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2582 * Get the next free id and write it to the ioapic.
2584 new_id = find_first_zero_bit(used, 256);
2585 reg_00.bits.ID = new_id;
2586 raw_spin_lock_irqsave(&ioapic_lock, flags);
2587 io_apic_write(idx, 0, reg_00.raw);
2588 reg_00.raw = io_apic_read(idx, 0);
2589 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2591 BUG_ON(reg_00.bits.ID != new_id);
2597 static int io_apic_get_version(int ioapic)
2599 union IO_APIC_reg_01 reg_01;
2600 unsigned long flags;
2602 raw_spin_lock_irqsave(&ioapic_lock, flags);
2603 reg_01.raw = io_apic_read(ioapic, 1);
2604 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2606 return reg_01.bits.version;
2609 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2611 int ioapic, pin, idx;
2613 if (skip_ioapic_setup)
2616 ioapic = mp_find_ioapic(gsi);
2620 pin = mp_find_ioapic_pin(ioapic, gsi);
2624 idx = find_irq_entry(ioapic, pin, mp_INT);
2628 *trigger = irq_trigger(idx);
2629 *polarity = irq_polarity(idx);
2634 * This function updates target affinity of IOAPIC interrupts to include
2635 * the CPUs which came online during SMP bringup.
2637 #define IOAPIC_RESOURCE_NAME_SIZE 11
2639 static struct resource *ioapic_resources;
2641 static struct resource * __init ioapic_setup_resources(void)
2644 struct resource *res;
2648 if (nr_ioapics == 0)
2651 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2654 mem = alloc_bootmem(n);
2657 mem += sizeof(struct resource) * nr_ioapics;
2659 for_each_ioapic(i) {
2661 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2662 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2663 mem += IOAPIC_RESOURCE_NAME_SIZE;
2664 ioapics[i].iomem_res = &res[i];
2667 ioapic_resources = res;
2672 void __init io_apic_init_mappings(void)
2674 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2675 struct resource *ioapic_res;
2678 ioapic_res = ioapic_setup_resources();
2679 for_each_ioapic(i) {
2680 if (smp_found_config) {
2681 ioapic_phys = mpc_ioapic_addr(i);
2682 #ifdef CONFIG_X86_32
2685 "WARNING: bogus zero IO-APIC "
2686 "address found in MPTABLE, "
2687 "disabling IO/APIC support!\n");
2688 smp_found_config = 0;
2689 skip_ioapic_setup = 1;
2690 goto fake_ioapic_page;
2694 #ifdef CONFIG_X86_32
2697 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2698 ioapic_phys = __pa(ioapic_phys);
2700 set_fixmap_nocache(idx, ioapic_phys);
2701 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2702 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2706 ioapic_res->start = ioapic_phys;
2707 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2712 void __init ioapic_insert_resources(void)
2715 struct resource *r = ioapic_resources;
2720 "IO APIC resources couldn't be allocated.\n");
2724 for_each_ioapic(i) {
2725 insert_resource(&iomem_resource, r);
2730 int mp_find_ioapic(u32 gsi)
2734 if (nr_ioapics == 0)
2737 /* Find the IOAPIC that manages this GSI. */
2738 for_each_ioapic(i) {
2739 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2740 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2744 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2748 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2750 struct mp_ioapic_gsi *gsi_cfg;
2752 if (WARN_ON(ioapic < 0))
2755 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2756 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2759 return gsi - gsi_cfg->gsi_base;
2762 static int bad_ioapic_register(int idx)
2764 union IO_APIC_reg_00 reg_00;
2765 union IO_APIC_reg_01 reg_01;
2766 union IO_APIC_reg_02 reg_02;
2768 reg_00.raw = io_apic_read(idx, 0);
2769 reg_01.raw = io_apic_read(idx, 1);
2770 reg_02.raw = io_apic_read(idx, 2);
2772 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2773 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2774 mpc_ioapic_addr(idx));
2781 static int find_free_ioapic_entry(void)
2785 for (idx = 0; idx < MAX_IO_APICS; idx++)
2786 if (ioapics[idx].nr_registers == 0)
2789 return MAX_IO_APICS;
2793 * mp_register_ioapic - Register an IOAPIC device
2794 * @id: hardware IOAPIC ID
2795 * @address: physical address of IOAPIC register area
2796 * @gsi_base: base of GSI associated with the IOAPIC
2797 * @cfg: configuration information for the IOAPIC
2799 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2800 struct ioapic_domain_cfg *cfg)
2802 bool hotplug = !!ioapic_initialized;
2803 struct mp_ioapic_gsi *gsi_cfg;
2804 int idx, ioapic, entries;
2808 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2811 for_each_ioapic(ioapic)
2812 if (ioapics[ioapic].mp_config.apicaddr == address) {
2813 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2818 idx = find_free_ioapic_entry();
2819 if (idx >= MAX_IO_APICS) {
2820 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2825 ioapics[idx].mp_config.type = MP_IOAPIC;
2826 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2827 ioapics[idx].mp_config.apicaddr = address;
2829 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2830 if (bad_ioapic_register(idx)) {
2831 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2835 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2836 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2839 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2840 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2842 entries = io_apic_get_redir_entries(idx);
2843 gsi_end = gsi_base + entries - 1;
2844 for_each_ioapic(ioapic) {
2845 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2846 if ((gsi_base >= gsi_cfg->gsi_base &&
2847 gsi_base <= gsi_cfg->gsi_end) ||
2848 (gsi_end >= gsi_cfg->gsi_base &&
2849 gsi_end <= gsi_cfg->gsi_end)) {
2850 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2852 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2853 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2857 gsi_cfg = mp_ioapic_gsi_routing(idx);
2858 gsi_cfg->gsi_base = gsi_base;
2859 gsi_cfg->gsi_end = gsi_end;
2861 ioapics[idx].irqdomain = NULL;
2862 ioapics[idx].irqdomain_cfg = *cfg;
2865 * If mp_register_ioapic() is called during early boot stage when
2866 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2867 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2870 if (mp_irqdomain_create(idx)) {
2871 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2874 alloc_ioapic_saved_registers(idx);
2877 if (gsi_cfg->gsi_end >= gsi_top)
2878 gsi_top = gsi_cfg->gsi_end + 1;
2879 if (nr_ioapics <= idx)
2880 nr_ioapics = idx + 1;
2882 /* Set nr_registers to mark entry present */
2883 ioapics[idx].nr_registers = entries;
2885 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2886 idx, mpc_ioapic_id(idx),
2887 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2888 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2893 int mp_unregister_ioapic(u32 gsi_base)
2898 for_each_ioapic(ioapic)
2899 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2904 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2908 for_each_pin(ioapic, pin) {
2909 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2910 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2911 struct mp_chip_data *data;
2914 data = irq_get_chip_data(irq);
2915 if (data && data->count) {
2916 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2923 /* Mark entry not present */
2924 ioapics[ioapic].nr_registers = 0;
2925 ioapic_destroy_irqdomain(ioapic);
2926 free_ioapic_saved_registers(ioapic);
2927 if (ioapics[ioapic].iomem_res)
2928 release_resource(ioapics[ioapic].iomem_res);
2929 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2930 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2935 int mp_ioapic_registered(u32 gsi_base)
2939 for_each_ioapic(ioapic)
2940 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2946 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2947 struct irq_alloc_info *info)
2949 if (info && info->ioapic_valid) {
2950 data->trigger = info->ioapic_trigger;
2951 data->polarity = info->ioapic_polarity;
2952 } else if (acpi_get_override_irq(gsi, &data->trigger,
2953 &data->polarity) < 0) {
2954 /* PCI interrupts are always active low level triggered. */
2955 data->trigger = IOAPIC_LEVEL;
2956 data->polarity = IOAPIC_POL_LOW;
2960 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2961 struct IO_APIC_route_entry *entry)
2963 memset(entry, 0, sizeof(*entry));
2964 entry->delivery_mode = apic->irq_delivery_mode;
2965 entry->dest_mode = apic->irq_dest_mode;
2966 entry->dest = cfg->dest_apicid;
2967 entry->vector = cfg->vector;
2968 entry->trigger = data->trigger;
2969 entry->polarity = data->polarity;
2971 * Mask level triggered irqs. Edge triggered irqs are masked
2972 * by the irq core code in case they fire.
2974 if (data->trigger == IOAPIC_LEVEL)
2975 entry->mask = IOAPIC_MASKED;
2977 entry->mask = IOAPIC_UNMASKED;
2980 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2981 unsigned int nr_irqs, void *arg)
2983 int ret, ioapic, pin;
2984 struct irq_cfg *cfg;
2985 struct irq_data *irq_data;
2986 struct mp_chip_data *data;
2987 struct irq_alloc_info *info = arg;
2988 unsigned long flags;
2990 if (!info || nr_irqs > 1)
2992 irq_data = irq_domain_get_irq_data(domain, virq);
2996 ioapic = mp_irqdomain_ioapic_idx(domain);
2997 pin = info->ioapic_pin;
2998 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3001 data = kzalloc(sizeof(*data), GFP_KERNEL);
3005 info->ioapic_entry = &data->entry;
3006 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3012 INIT_LIST_HEAD(&data->irq_2_pin);
3013 irq_data->hwirq = info->ioapic_pin;
3014 irq_data->chip = (domain->parent == x86_vector_domain) ?
3015 &ioapic_chip : &ioapic_ir_chip;
3016 irq_data->chip_data = data;
3017 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3019 cfg = irqd_cfg(irq_data);
3020 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3022 local_irq_save(flags);
3023 if (info->ioapic_entry)
3024 mp_setup_entry(cfg, data, info->ioapic_entry);
3025 mp_register_handler(virq, data->trigger);
3026 if (virq < nr_legacy_irqs())
3027 legacy_pic->mask(virq);
3028 local_irq_restore(flags);
3030 apic_printk(APIC_VERBOSE, KERN_DEBUG
3031 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3032 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3033 virq, data->trigger, data->polarity, cfg->dest_apicid);
3038 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3039 unsigned int nr_irqs)
3041 struct irq_data *irq_data;
3042 struct mp_chip_data *data;
3044 BUG_ON(nr_irqs != 1);
3045 irq_data = irq_domain_get_irq_data(domain, virq);
3046 if (irq_data && irq_data->chip_data) {
3047 data = irq_data->chip_data;
3048 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3049 (int)irq_data->hwirq);
3050 WARN_ON(!list_empty(&data->irq_2_pin));
3051 kfree(irq_data->chip_data);
3053 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3056 int mp_irqdomain_activate(struct irq_domain *domain,
3057 struct irq_data *irq_data, bool reserve)
3059 unsigned long flags;
3061 raw_spin_lock_irqsave(&ioapic_lock, flags);
3062 ioapic_configure_entry(irq_data);
3063 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3067 void mp_irqdomain_deactivate(struct irq_domain *domain,
3068 struct irq_data *irq_data)
3070 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3071 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3072 (int)irq_data->hwirq);
3075 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3077 return (int)(long)domain->host_data;
3080 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3081 .alloc = mp_irqdomain_alloc,
3082 .free = mp_irqdomain_free,
3083 .activate = mp_irqdomain_activate,
3084 .deactivate = mp_irqdomain_deactivate,