2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/barrier.h>
45 #include <asm/mpspec.h>
46 #include <asm/i8259.h>
47 #include <asm/proto.h>
49 #include <asm/io_apic.h>
57 #include <asm/hypervisor.h>
58 #include <asm/cpu_device_id.h>
59 #include <asm/intel-family.h>
60 #include <asm/irq_regs.h>
62 unsigned int num_processors;
64 unsigned disabled_cpus;
66 /* Processor that is doing the boot up */
67 unsigned int boot_cpu_physical_apicid = -1U;
68 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
70 u8 boot_cpu_apic_version;
73 * The highest APIC ID seen during enumeration.
75 static unsigned int max_physical_apicid;
78 * Bitmask of physically existing CPUs:
80 physid_mask_t phys_cpu_present_map;
83 * Processor to be disabled specified by kernel parameter
84 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
85 * avoid undefined behaviour caused by sending INIT from AP to BSP.
87 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
90 * This variable controls which CPUs receive external NMIs. By default,
91 * external NMIs are delivered only to the BSP.
93 static int apic_extnmi = APIC_EXTNMI_BSP;
96 * Map cpu index to physical APIC ID
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
108 * On x86_32, the mapping between cpu and logical apicid may vary
109 * depending on apic in use. The following early percpu variable is
110 * used for the mapping. This is where the behaviors of x86_64 and 32
111 * actually diverge. Let's keep it ugly for now.
113 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase;
119 * Handle interrupt mode configuration register (IMCR).
120 * This register controls whether the interrupt signals
121 * that reach the BSP come from the master PIC or from the
122 * local APIC. Before entering Symmetric I/O Mode, either
123 * the BIOS or the operating system must switch out of
124 * PIC Mode by changing the IMCR.
126 static inline void imcr_pic_to_apic(void)
128 /* select IMCR register */
130 /* NMI and 8259 INTR go through APIC */
134 static inline void imcr_apic_to_pic(void)
136 /* select IMCR register */
138 /* NMI and 8259 INTR go directly to BSP */
144 * Knob to control our willingness to enable the local APIC.
148 static int force_enable_local_apic __initdata;
151 * APIC command line parameters
153 static int __init parse_lapic(char *arg)
155 if (IS_ENABLED(CONFIG_X86_32) && !arg)
156 force_enable_local_apic = 1;
157 else if (arg && !strncmp(arg, "notscdeadline", 13))
158 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
161 early_param("lapic", parse_lapic);
164 static int apic_calibrate_pmtmr __initdata;
165 static __init int setup_apicpmtimer(char *s)
167 apic_calibrate_pmtmr = 1;
171 __setup("apicpmtimer", setup_apicpmtimer);
174 unsigned long mp_lapic_addr;
176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
177 static int disable_apic_timer __initdata;
178 /* Local APIC timer works in C2 */
179 int local_apic_timer_c2_ok;
180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
183 * Debug level, exported for io_apic.c
189 /* Have we found an MP table */
190 int smp_found_config;
192 static struct resource lapic_resource = {
193 .name = "Local APIC",
194 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
197 unsigned int lapic_timer_frequency = 0;
199 static void apic_pm_activate(void);
201 static unsigned long apic_phys;
204 * Get the LAPIC version
206 static inline int lapic_get_version(void)
208 return GET_APIC_VERSION(apic_read(APIC_LVR));
212 * Check, if the APIC is integrated or a separate chip
214 static inline int lapic_is_integrated(void)
216 return APIC_INTEGRATED(lapic_get_version());
220 * Check, whether this is a modern or a first generation APIC
222 static int modern_apic(void)
224 /* AMD systems use old APIC versions, so check the CPU */
225 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
226 boot_cpu_data.x86 >= 0xf)
228 return lapic_get_version() >= 0x14;
232 * right after this call apic become NOOP driven
233 * so apic->write/read doesn't do anything
235 static void __init apic_disable(void)
237 pr_info("APIC: switched to apic NOOP\n");
241 void native_apic_wait_icr_idle(void)
243 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
247 u32 native_safe_apic_wait_icr_idle(void)
254 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
257 inc_irq_stat(icr_read_retry_count);
259 } while (timeout++ < 1000);
264 void native_apic_icr_write(u32 low, u32 id)
268 local_irq_save(flags);
269 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
270 apic_write(APIC_ICR, low);
271 local_irq_restore(flags);
274 u64 native_apic_icr_read(void)
278 icr2 = apic_read(APIC_ICR2);
279 icr1 = apic_read(APIC_ICR);
281 return icr1 | ((u64)icr2 << 32);
286 * get_physical_broadcast - Get number of physical broadcast IDs
288 int get_physical_broadcast(void)
290 return modern_apic() ? 0xff : 0xf;
295 * lapic_get_maxlvt - get the maximum number of local vector table entries
297 int lapic_get_maxlvt(void)
300 * - we always have APIC integrated on 64bit mode
301 * - 82489DXs do not report # of LVT entries
303 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
311 #define APIC_DIVISOR 16
312 #define TSC_DIVISOR 8
315 * This function sets up the local APIC timer, with a timeout of
316 * 'clocks' APIC bus clock. During calibration we actually call
317 * this function twice on the boot CPU, once with a bogus timeout
318 * value, second time for real. The other (noncalibrating) CPUs
319 * call this function only once, with the real, calibrated value.
321 * We do reads before writes even if unnecessary, to get around the
322 * P5 APIC double write bug.
324 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
326 unsigned int lvtt_value, tmp_value;
328 lvtt_value = LOCAL_TIMER_VECTOR;
330 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
331 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
332 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
334 if (!lapic_is_integrated())
335 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
338 lvtt_value |= APIC_LVT_MASKED;
340 apic_write(APIC_LVTT, lvtt_value);
342 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
344 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
345 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
346 * According to Intel, MFENCE can do the serialization here.
348 asm volatile("mfence" : : : "memory");
355 tmp_value = apic_read(APIC_TDCR);
356 apic_write(APIC_TDCR,
357 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
361 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
365 * Setup extended LVT, AMD specific
367 * Software should use the LVT offsets the BIOS provides. The offsets
368 * are determined by the subsystems using it like those for MCE
369 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
370 * are supported. Beginning with family 10h at least 4 offsets are
373 * Since the offsets must be consistent for all cores, we keep track
374 * of the LVT offsets in software and reserve the offset for the same
375 * vector also to be used on other cores. An offset is freed by
376 * setting the entry to APIC_EILVT_MASKED.
378 * If the BIOS is right, there should be no conflicts. Otherwise a
379 * "[Firmware Bug]: ..." error message is generated. However, if
380 * software does not properly determines the offsets, it is not
381 * necessarily a BIOS bug.
384 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
386 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
388 return (old & APIC_EILVT_MASKED)
389 || (new == APIC_EILVT_MASKED)
390 || ((new & ~APIC_EILVT_MASKED) == old);
393 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
395 unsigned int rsvd, vector;
397 if (offset >= APIC_EILVT_NR_MAX)
400 rsvd = atomic_read(&eilvt_offsets[offset]);
402 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
403 if (vector && !eilvt_entry_is_changeable(vector, new))
404 /* may not change if vectors are different */
406 } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
408 rsvd = new & ~APIC_EILVT_MASKED;
409 if (rsvd && rsvd != vector)
410 pr_info("LVT offset %d assigned for vector 0x%02x\n",
417 * If mask=1, the LVT entry does not generate interrupts while mask=0
418 * enables the vector. See also the BKDGs. Must be called with
419 * preemption disabled.
422 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
424 unsigned long reg = APIC_EILVTn(offset);
425 unsigned int new, old, reserved;
427 new = (mask << 16) | (msg_type << 8) | vector;
428 old = apic_read(reg);
429 reserved = reserve_eilvt_offset(offset, new);
431 if (reserved != new) {
432 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
433 "vector 0x%x, but the register is already in use for "
434 "vector 0x%x on another cpu\n",
435 smp_processor_id(), reg, offset, new, reserved);
439 if (!eilvt_entry_is_changeable(old, new)) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on this cpu\n",
443 smp_processor_id(), reg, offset, new, old);
447 apic_write(reg, new);
451 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
454 * Program the next event, relative to now
456 static int lapic_next_event(unsigned long delta,
457 struct clock_event_device *evt)
459 apic_write(APIC_TMICT, delta);
463 static int lapic_next_deadline(unsigned long delta,
464 struct clock_event_device *evt)
468 /* This MSR is special and need a special fence: */
472 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
476 static int lapic_timer_shutdown(struct clock_event_device *evt)
480 /* Lapic used as dummy for broadcast ? */
481 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
484 v = apic_read(APIC_LVTT);
485 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
486 apic_write(APIC_LVTT, v);
487 apic_write(APIC_TMICT, 0);
492 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
494 /* Lapic used as dummy for broadcast ? */
495 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
498 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
502 static int lapic_timer_set_periodic(struct clock_event_device *evt)
504 return lapic_timer_set_periodic_oneshot(evt, false);
507 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
509 return lapic_timer_set_periodic_oneshot(evt, true);
513 * Local APIC timer broadcast function
515 static void lapic_timer_broadcast(const struct cpumask *mask)
518 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
524 * The local apic timer can be used for any function which is CPU local.
526 static struct clock_event_device lapic_clockevent = {
528 .features = CLOCK_EVT_FEAT_PERIODIC |
529 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
530 | CLOCK_EVT_FEAT_DUMMY,
532 .set_state_shutdown = lapic_timer_shutdown,
533 .set_state_periodic = lapic_timer_set_periodic,
534 .set_state_oneshot = lapic_timer_set_oneshot,
535 .set_state_oneshot_stopped = lapic_timer_shutdown,
536 .set_next_event = lapic_next_event,
537 .broadcast = lapic_timer_broadcast,
541 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
543 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
544 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
546 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
547 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
549 static __init u32 hsx_deadline_rev(void)
551 switch (boot_cpu_data.x86_stepping) {
552 case 0x02: return 0x3a; /* EP */
553 case 0x04: return 0x0f; /* EX */
559 static __init u32 bdx_deadline_rev(void)
561 switch (boot_cpu_data.x86_stepping) {
562 case 0x02: return 0x00000011;
563 case 0x03: return 0x0700000e;
564 case 0x04: return 0x0f00000c;
565 case 0x05: return 0x0e000003;
571 static __init u32 skx_deadline_rev(void)
573 switch (boot_cpu_data.x86_stepping) {
574 case 0x03: return 0x01000136;
575 case 0x04: return 0x02000014;
578 if (boot_cpu_data.x86_stepping > 4)
584 static const struct x86_cpu_id deadline_match[] __initconst = {
585 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
587 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
588 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
606 static __init bool apic_validate_deadline_timer(void)
608 const struct x86_cpu_id *m;
611 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
613 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
616 m = x86_match_cpu(deadline_match);
621 * Function pointers will have the MSB set due to address layout,
622 * immediate revisions will not.
624 if ((long)m->driver_data < 0)
625 rev = ((u32 (*)(void))(m->driver_data))();
627 rev = (u32)m->driver_data;
629 if (boot_cpu_data.microcode >= rev)
632 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
633 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
634 "/*(DEBLOBBED)*/\n", rev);
639 * Setup the local APIC timer for this CPU. Copy the initialized values
640 * of the boot CPU and register the clock event in the framework.
642 static void setup_APIC_timer(void)
644 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
646 if (this_cpu_has(X86_FEATURE_ARAT)) {
647 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
648 /* Make LAPIC timer preferrable over percpu HPET */
649 lapic_clockevent.rating = 150;
652 memcpy(levt, &lapic_clockevent, sizeof(*levt));
653 levt->cpumask = cpumask_of(smp_processor_id());
655 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
656 levt->name = "lapic-deadline";
657 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
658 CLOCK_EVT_FEAT_DUMMY);
659 levt->set_next_event = lapic_next_deadline;
660 clockevents_config_and_register(levt,
661 tsc_khz * (1000 / TSC_DIVISOR),
664 clockevents_register_device(levt);
668 * Install the updated TSC frequency from recalibration at the TSC
669 * deadline clockevent devices.
671 static void __lapic_update_tsc_freq(void *info)
673 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
675 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
678 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
681 void lapic_update_tsc_freq(void)
684 * The clockevent device's ->mult and ->shift can both be
685 * changed. In order to avoid races, schedule the frequency
686 * update code on each CPU.
688 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
692 * In this functions we calibrate APIC bus clocks to the external timer.
694 * We want to do the calibration only once since we want to have local timer
695 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
698 * This was previously done by reading the PIT/HPET and waiting for a wrap
699 * around to find out, that a tick has elapsed. I have a box, where the PIT
700 * readout is broken, so it never gets out of the wait loop again. This was
701 * also reported by others.
703 * Monitoring the jiffies value is inaccurate and the clockevents
704 * infrastructure allows us to do a simple substitution of the interrupt
707 * The calibration routine also uses the pm_timer when possible, as the PIT
708 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
709 * back to normal later in the boot process).
712 #define LAPIC_CAL_LOOPS (HZ/10)
714 static __initdata int lapic_cal_loops = -1;
715 static __initdata long lapic_cal_t1, lapic_cal_t2;
716 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
717 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
718 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
721 * Temporary interrupt handler and polled calibration function.
723 static void __init lapic_cal_handler(struct clock_event_device *dev)
725 unsigned long long tsc = 0;
726 long tapic = apic_read(APIC_TMCCT);
727 unsigned long pm = acpi_pm_read_early();
729 if (boot_cpu_has(X86_FEATURE_TSC))
732 switch (lapic_cal_loops++) {
734 lapic_cal_t1 = tapic;
735 lapic_cal_tsc1 = tsc;
737 lapic_cal_j1 = jiffies;
740 case LAPIC_CAL_LOOPS:
741 lapic_cal_t2 = tapic;
742 lapic_cal_tsc2 = tsc;
743 if (pm < lapic_cal_pm1)
744 pm += ACPI_PM_OVRRUN;
746 lapic_cal_j2 = jiffies;
752 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
754 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
755 const long pm_thresh = pm_100ms / 100;
759 #ifndef CONFIG_X86_PM_TIMER
763 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
765 /* Check, if the PM timer is available */
769 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
771 if (deltapm > (pm_100ms - pm_thresh) &&
772 deltapm < (pm_100ms + pm_thresh)) {
773 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
777 res = (((u64)deltapm) * mult) >> 22;
778 do_div(res, 1000000);
779 pr_warning("APIC calibration not consistent "
780 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
782 /* Correct the lapic counter value */
783 res = (((u64)(*delta)) * pm_100ms);
784 do_div(res, deltapm);
785 pr_info("APIC delta adjusted to PM-Timer: "
786 "%lu (%ld)\n", (unsigned long)res, *delta);
789 /* Correct the tsc counter value */
790 if (boot_cpu_has(X86_FEATURE_TSC)) {
791 res = (((u64)(*deltatsc)) * pm_100ms);
792 do_div(res, deltapm);
793 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
794 "PM-Timer: %lu (%ld)\n",
795 (unsigned long)res, *deltatsc);
796 *deltatsc = (long)res;
802 static int __init calibrate_APIC_clock(void)
804 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
805 u64 tsc_perj = 0, tsc_start = 0;
806 unsigned long jif_start;
807 unsigned long deltaj;
808 long delta, deltatsc;
809 int pm_referenced = 0;
812 * check if lapic timer has already been calibrated by platform
813 * specific routine, such as tsc calibration code. if so, we just fill
814 * in the clockevent structure and return.
817 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
819 } else if (lapic_timer_frequency) {
820 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
821 lapic_timer_frequency);
822 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
823 TICK_NSEC, lapic_clockevent.shift);
824 lapic_clockevent.max_delta_ns =
825 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
826 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
827 lapic_clockevent.min_delta_ns =
828 clockevent_delta2ns(0xF, &lapic_clockevent);
829 lapic_clockevent.min_delta_ticks = 0xF;
830 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
834 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
835 "calibrating APIC timer ...\n");
838 * There are platforms w/o global clockevent devices. Instead of
839 * making the calibration conditional on that, use a polling based
840 * approach everywhere.
845 * Setup the APIC counter to maximum. There is no way the lapic
846 * can underflow in the 100ms detection time frame
848 __setup_APIC_LVTT(0xffffffff, 0, 0);
851 * Methods to terminate the calibration loop:
852 * 1) Global clockevent if available (jiffies)
853 * 2) TSC if available and frequency is known
855 jif_start = READ_ONCE(jiffies);
859 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
863 * Enable interrupts so the tick can fire, if a global
864 * clockevent device is available
868 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
869 /* Wait for a tick to elapse */
872 u64 tsc_now = rdtsc();
873 if ((tsc_now - tsc_start) >= tsc_perj) {
874 tsc_start += tsc_perj;
878 unsigned long jif_now = READ_ONCE(jiffies);
880 if (time_after(jif_now, jif_start)) {
888 /* Invoke the calibration routine */
890 lapic_cal_handler(NULL);
896 /* Build delta t1-t2 as apic timer counts down */
897 delta = lapic_cal_t1 - lapic_cal_t2;
898 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
900 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
902 /* we trust the PM based calibration if possible */
903 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
906 /* Calculate the scaled math multiplication factor */
907 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
908 lapic_clockevent.shift);
909 lapic_clockevent.max_delta_ns =
910 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
911 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
912 lapic_clockevent.min_delta_ns =
913 clockevent_delta2ns(0xF, &lapic_clockevent);
914 lapic_clockevent.min_delta_ticks = 0xF;
916 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
918 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
919 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
920 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
921 lapic_timer_frequency);
923 if (boot_cpu_has(X86_FEATURE_TSC)) {
924 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
926 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
927 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
930 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
932 lapic_timer_frequency / (1000000 / HZ),
933 lapic_timer_frequency % (1000000 / HZ));
936 * Do a sanity check on the APIC calibration result
938 if (lapic_timer_frequency < (1000000 / HZ)) {
940 pr_warning("APIC frequency too slow, disabling apic timer\n");
944 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
947 * PM timer calibration failed or not turned on so lets try APIC
948 * timer based calibration, if a global clockevent device is
951 if (!pm_referenced && global_clock_event) {
952 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
955 * Setup the apic timer manually
957 levt->event_handler = lapic_cal_handler;
958 lapic_timer_set_periodic(levt);
959 lapic_cal_loops = -1;
961 /* Let the interrupts run */
964 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
967 /* Stop the lapic timer */
969 lapic_timer_shutdown(levt);
972 deltaj = lapic_cal_j2 - lapic_cal_j1;
973 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
975 /* Check, if the jiffies result is consistent */
976 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
977 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
979 levt->features |= CLOCK_EVT_FEAT_DUMMY;
983 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
984 pr_warning("APIC timer disabled due to verification failure\n");
992 * Setup the boot APIC
994 * Calibrate and verify the result.
996 void __init setup_boot_APIC_clock(void)
999 * The local apic timer can be disabled via the kernel
1000 * commandline or from the CPU detection code. Register the lapic
1001 * timer as a dummy clock event source on SMP systems, so the
1002 * broadcast mechanism is used. On UP systems simply ignore it.
1004 if (disable_apic_timer) {
1005 pr_info("Disabling APIC timer\n");
1006 /* No broadcast on UP ! */
1007 if (num_possible_cpus() > 1) {
1008 lapic_clockevent.mult = 1;
1014 if (calibrate_APIC_clock()) {
1015 /* No broadcast on UP ! */
1016 if (num_possible_cpus() > 1)
1022 * If nmi_watchdog is set to IO_APIC, we need the
1023 * PIT/HPET going. Otherwise register lapic as a dummy
1026 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1028 /* Setup the lapic or request the broadcast */
1030 amd_e400_c1e_apic_setup();
1033 void setup_secondary_APIC_clock(void)
1036 amd_e400_c1e_apic_setup();
1040 * The guts of the apic timer interrupt
1042 static void local_apic_timer_interrupt(void)
1044 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1047 * Normally we should not be here till LAPIC has been initialized but
1048 * in some cases like kdump, its possible that there is a pending LAPIC
1049 * timer interrupt from previous kernel's context and is delivered in
1050 * new kernel the moment interrupts are enabled.
1052 * Interrupts are enabled early and LAPIC is setup much later, hence
1053 * its possible that when we get here evt->event_handler is NULL.
1054 * Check for event_handler being NULL and discard the interrupt as
1057 if (!evt->event_handler) {
1058 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1059 smp_processor_id());
1061 lapic_timer_shutdown(evt);
1066 * the NMI deadlock-detector uses this.
1068 inc_irq_stat(apic_timer_irqs);
1070 evt->event_handler(evt);
1074 * Local APIC timer interrupt. This is the most natural way for doing
1075 * local interrupts, but local timer interrupts can be emulated by
1076 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1078 * [ if a single-CPU system runs an SMP kernel then we call the local
1079 * interrupt as well. Thus we cannot inline the local irq ... ]
1081 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1083 struct pt_regs *old_regs = set_irq_regs(regs);
1086 * NOTE! We'd better ACK the irq immediately,
1087 * because timer handling can be slow.
1089 * update_process_times() expects us to have done irq_enter().
1090 * Besides, if we don't timer interrupts ignore the global
1091 * interrupt lock, which is the WrongThing (tm) to do.
1094 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1095 local_apic_timer_interrupt();
1096 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1099 set_irq_regs(old_regs);
1102 int setup_profiling_timer(unsigned int multiplier)
1108 * Local APIC start and shutdown
1112 * clear_local_APIC - shutdown the local APIC
1114 * This is called, when a CPU is disabled and before rebooting, so the state of
1115 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1116 * leftovers during boot.
1118 void clear_local_APIC(void)
1123 /* APIC hasn't been mapped yet */
1124 if (!x2apic_mode && !apic_phys)
1127 maxlvt = lapic_get_maxlvt();
1129 * Masking an LVT entry can trigger a local APIC error
1130 * if the vector is zero. Mask LVTERR first to prevent this.
1133 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1134 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1137 * Careful: we have to set masks only first to deassert
1138 * any level-triggered sources.
1140 v = apic_read(APIC_LVTT);
1141 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1142 v = apic_read(APIC_LVT0);
1143 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1144 v = apic_read(APIC_LVT1);
1145 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1147 v = apic_read(APIC_LVTPC);
1148 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1151 /* lets not touch this if we didn't frob it */
1152 #ifdef CONFIG_X86_THERMAL_VECTOR
1154 v = apic_read(APIC_LVTTHMR);
1155 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1158 #ifdef CONFIG_X86_MCE_INTEL
1160 v = apic_read(APIC_LVTCMCI);
1161 if (!(v & APIC_LVT_MASKED))
1162 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1167 * Clean APIC state for other OSs:
1169 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1170 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1171 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1173 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1175 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1177 /* Integrated APIC (!82489DX) ? */
1178 if (lapic_is_integrated()) {
1180 /* Clear ESR due to Pentium errata 3AP and 11AP */
1181 apic_write(APIC_ESR, 0);
1182 apic_read(APIC_ESR);
1187 * disable_local_APIC - clear and disable the local APIC
1189 void disable_local_APIC(void)
1193 /* APIC hasn't been mapped yet */
1194 if (!x2apic_mode && !apic_phys)
1200 * Disable APIC (implies clearing of registers
1203 value = apic_read(APIC_SPIV);
1204 value &= ~APIC_SPIV_APIC_ENABLED;
1205 apic_write(APIC_SPIV, value);
1207 #ifdef CONFIG_X86_32
1209 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1210 * restore the disabled state.
1212 if (enabled_via_apicbase) {
1215 rdmsr(MSR_IA32_APICBASE, l, h);
1216 l &= ~MSR_IA32_APICBASE_ENABLE;
1217 wrmsr(MSR_IA32_APICBASE, l, h);
1223 * If Linux enabled the LAPIC against the BIOS default disable it down before
1224 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1225 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1226 * for the case where Linux didn't enable the LAPIC.
1228 void lapic_shutdown(void)
1230 unsigned long flags;
1232 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1235 local_irq_save(flags);
1237 #ifdef CONFIG_X86_32
1238 if (!enabled_via_apicbase)
1242 disable_local_APIC();
1245 local_irq_restore(flags);
1249 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1251 void __init sync_Arb_IDs(void)
1254 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1257 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1263 apic_wait_icr_idle();
1265 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1266 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1267 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1270 enum apic_intr_mode_id apic_intr_mode;
1272 static int __init apic_intr_mode_select(void)
1274 /* Check kernel option */
1276 pr_info("APIC disabled via kernel command line\n");
1281 #ifdef CONFIG_X86_64
1282 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1283 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1285 pr_info("APIC disabled by BIOS\n");
1289 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1291 /* Neither 82489DX nor integrated APIC ? */
1292 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1297 /* If the BIOS pretends there is an integrated APIC ? */
1298 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1299 APIC_INTEGRATED(boot_cpu_apic_version)) {
1301 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1302 boot_cpu_physical_apicid);
1307 /* Check MP table or ACPI MADT configuration */
1308 if (!smp_found_config) {
1309 disable_ioapic_support();
1311 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1312 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1314 return APIC_VIRTUAL_WIRE;
1318 /* If SMP should be disabled, then really disable it! */
1319 if (!setup_max_cpus) {
1320 pr_info("APIC: SMP mode deactivated\n");
1321 return APIC_SYMMETRIC_IO_NO_ROUTING;
1324 if (read_apic_id() != boot_cpu_physical_apicid) {
1325 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1326 read_apic_id(), boot_cpu_physical_apicid);
1327 /* Or can we switch back to PIC here? */
1331 return APIC_SYMMETRIC_IO;
1335 * An initial setup of the virtual wire mode.
1337 void __init init_bsp_APIC(void)
1342 * Don't do the setup now if we have a SMP BIOS as the
1343 * through-I/O-APIC virtual wire mode might be active.
1345 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1349 * Do not trust the local APIC being empty at bootup.
1356 value = apic_read(APIC_SPIV);
1357 value &= ~APIC_VECTOR_MASK;
1358 value |= APIC_SPIV_APIC_ENABLED;
1360 #ifdef CONFIG_X86_32
1361 /* This bit is reserved on P4/Xeon and should be cleared */
1362 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1363 (boot_cpu_data.x86 == 15))
1364 value &= ~APIC_SPIV_FOCUS_DISABLED;
1367 value |= APIC_SPIV_FOCUS_DISABLED;
1368 value |= SPURIOUS_APIC_VECTOR;
1369 apic_write(APIC_SPIV, value);
1372 * Set up the virtual wire mode.
1374 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1375 value = APIC_DM_NMI;
1376 if (!lapic_is_integrated()) /* 82489DX */
1377 value |= APIC_LVT_LEVEL_TRIGGER;
1378 if (apic_extnmi == APIC_EXTNMI_NONE)
1379 value |= APIC_LVT_MASKED;
1380 apic_write(APIC_LVT1, value);
1383 /* Init the interrupt delivery mode for the BSP */
1384 void __init apic_intr_mode_init(void)
1386 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1388 apic_intr_mode = apic_intr_mode_select();
1390 switch (apic_intr_mode) {
1392 pr_info("APIC: Keep in PIC mode(8259)\n");
1394 case APIC_VIRTUAL_WIRE:
1395 pr_info("APIC: Switch to virtual wire mode setup\n");
1396 default_setup_apic_routing();
1398 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1399 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1401 default_setup_apic_routing();
1403 case APIC_SYMMETRIC_IO:
1404 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1405 default_setup_apic_routing();
1407 case APIC_SYMMETRIC_IO_NO_ROUTING:
1408 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1412 apic_bsp_setup(upmode);
1415 static void lapic_setup_esr(void)
1417 unsigned int oldvalue, value, maxlvt;
1419 if (!lapic_is_integrated()) {
1420 pr_info("No ESR for 82489DX.\n");
1424 if (apic->disable_esr) {
1426 * Something untraceable is creating bad interrupts on
1427 * secondary quads ... for the moment, just leave the
1428 * ESR disabled - we can't do anything useful with the
1429 * errors anyway - mbligh
1431 pr_info("Leaving ESR disabled.\n");
1435 maxlvt = lapic_get_maxlvt();
1436 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1437 apic_write(APIC_ESR, 0);
1438 oldvalue = apic_read(APIC_ESR);
1440 /* enables sending errors */
1441 value = ERROR_APIC_VECTOR;
1442 apic_write(APIC_LVTERR, value);
1445 * spec says clear errors after enabling vector.
1448 apic_write(APIC_ESR, 0);
1449 value = apic_read(APIC_ESR);
1450 if (value != oldvalue)
1451 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1452 "vector: 0x%08x after: 0x%08x\n",
1456 #define APIC_IR_REGS APIC_ISR_NR
1457 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1458 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1461 unsigned long map[APIC_IR_MAPSIZE];
1462 u32 regs[APIC_IR_REGS];
1465 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1470 for (i = 0; i < APIC_IR_REGS; i++)
1471 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1474 for (i = 0; i < APIC_IR_REGS; i++)
1475 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1478 * If the ISR map is not empty. ACK the APIC and run another round
1479 * to verify whether a pending IRR has been unblocked and turned
1482 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1484 * There can be multiple ISR bits set when a high priority
1485 * interrupt preempted a lower priority one. Issue an ACK
1488 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1493 return !bitmap_empty(irr->map, APIC_IR_BITS);
1497 * After a crash, we no longer service the interrupts and a pending
1498 * interrupt from previous kernel might still have ISR bit set.
1500 * Most probably by now the CPU has serviced that pending interrupt and it
1501 * might not have done the ack_APIC_irq() because it thought, interrupt
1502 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1503 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1504 * a vector might get locked. It was noticed for timer irq (vector
1505 * 0x31). Issue an extra EOI to clear ISR.
1507 * If there are pending IRR bits they turn into ISR bits after a higher
1508 * priority ISR bit has been acked.
1510 static void apic_pending_intr_clear(void)
1512 union apic_ir irr, isr;
1515 /* 512 loops are way oversized and give the APIC a chance to obey. */
1516 for (i = 0; i < 512; i++) {
1517 if (!apic_check_and_ack(&irr, &isr))
1520 /* Dump the IRR/ISR content if that failed */
1521 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1525 * setup_local_APIC - setup the local APIC
1527 * Used to setup local APIC while initializing BSP or bringing up APs.
1528 * Always called with preemption disabled.
1530 static void setup_local_APIC(void)
1532 int cpu = smp_processor_id();
1537 disable_ioapic_support();
1542 * If this comes from kexec/kcrash the APIC might be enabled in
1543 * SPIV. Soft disable it before doing further initialization.
1545 value = apic_read(APIC_SPIV);
1546 value &= ~APIC_SPIV_APIC_ENABLED;
1547 apic_write(APIC_SPIV, value);
1549 #ifdef CONFIG_X86_32
1550 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1551 if (lapic_is_integrated() && apic->disable_esr) {
1552 apic_write(APIC_ESR, 0);
1553 apic_write(APIC_ESR, 0);
1554 apic_write(APIC_ESR, 0);
1555 apic_write(APIC_ESR, 0);
1558 perf_events_lapic_init();
1561 * Double-check whether this APIC is really registered.
1562 * This is meaningless in clustered apic mode, so we skip it.
1564 BUG_ON(!apic->apic_id_registered());
1567 * Intel recommends to set DFR, LDR and TPR before enabling
1568 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1569 * document number 292116). So here it goes...
1571 apic->init_apic_ldr();
1573 #ifdef CONFIG_X86_32
1574 if (apic->dest_logical) {
1575 int logical_apicid, ldr_apicid;
1578 * APIC LDR is initialized. If logical_apicid mapping was
1579 * initialized during get_smp_config(), make sure it matches
1582 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1583 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1584 if (logical_apicid != BAD_APICID)
1585 WARN_ON(logical_apicid != ldr_apicid);
1586 /* Always use the value from LDR. */
1587 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1592 * Set Task Priority to 'accept all'. We never change this
1595 value = apic_read(APIC_TASKPRI);
1596 value &= ~APIC_TPRI_MASK;
1597 apic_write(APIC_TASKPRI, value);
1599 /* Clear eventually stale ISR/IRR bits */
1600 apic_pending_intr_clear();
1603 * Now that we are all set up, enable the APIC
1605 value = apic_read(APIC_SPIV);
1606 value &= ~APIC_VECTOR_MASK;
1610 value |= APIC_SPIV_APIC_ENABLED;
1612 #ifdef CONFIG_X86_32
1614 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1615 * certain networking cards. If high frequency interrupts are
1616 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1617 * entry is masked/unmasked at a high rate as well then sooner or
1618 * later IOAPIC line gets 'stuck', no more interrupts are received
1619 * from the device. If focus CPU is disabled then the hang goes
1622 * [ This bug can be reproduced easily with a level-triggered
1623 * PCI Ne2000 networking cards and PII/PIII processors, dual
1627 * Actually disabling the focus CPU check just makes the hang less
1628 * frequent as it makes the interrupt distributon model be more
1629 * like LRU than MRU (the short-term load is more even across CPUs).
1633 * - enable focus processor (bit==0)
1634 * - 64bit mode always use processor focus
1635 * so no need to set it
1637 value &= ~APIC_SPIV_FOCUS_DISABLED;
1641 * Set spurious IRQ vector
1643 value |= SPURIOUS_APIC_VECTOR;
1644 apic_write(APIC_SPIV, value);
1647 * Set up LVT0, LVT1:
1649 * set up through-local-APIC on the boot CPU's LINT0. This is not
1650 * strictly necessary in pure symmetric-IO mode, but sometimes
1651 * we delegate interrupts to the 8259A.
1654 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1656 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1657 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1658 value = APIC_DM_EXTINT;
1659 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1661 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1662 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1664 apic_write(APIC_LVT0, value);
1667 * Only the BSP sees the LINT1 NMI signal by default. This can be
1668 * modified by apic_extnmi= boot option.
1670 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1671 apic_extnmi == APIC_EXTNMI_ALL)
1672 value = APIC_DM_NMI;
1674 value = APIC_DM_NMI | APIC_LVT_MASKED;
1677 if (!lapic_is_integrated())
1678 value |= APIC_LVT_LEVEL_TRIGGER;
1679 apic_write(APIC_LVT1, value);
1681 #ifdef CONFIG_X86_MCE_INTEL
1682 /* Recheck CMCI information after local APIC is up on CPU #0 */
1688 static void end_local_APIC_setup(void)
1692 #ifdef CONFIG_X86_32
1695 /* Disable the local apic timer */
1696 value = apic_read(APIC_LVTT);
1697 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1698 apic_write(APIC_LVTT, value);
1706 * APIC setup function for application processors. Called from smpboot.c
1708 void apic_ap_setup(void)
1711 end_local_APIC_setup();
1714 #ifdef CONFIG_X86_X2APIC
1722 static int x2apic_state;
1724 static void __x2apic_disable(void)
1728 if (!boot_cpu_has(X86_FEATURE_APIC))
1731 rdmsrl(MSR_IA32_APICBASE, msr);
1732 if (!(msr & X2APIC_ENABLE))
1734 /* Disable xapic and x2apic first and then reenable xapic mode */
1735 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1736 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1737 printk_once(KERN_INFO "x2apic disabled\n");
1740 static void __x2apic_enable(void)
1744 rdmsrl(MSR_IA32_APICBASE, msr);
1745 if (msr & X2APIC_ENABLE)
1747 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1748 printk_once(KERN_INFO "x2apic enabled\n");
1751 static int __init setup_nox2apic(char *str)
1753 if (x2apic_enabled()) {
1754 int apicid = native_apic_msr_read(APIC_ID);
1756 if (apicid >= 255) {
1757 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1761 pr_warning("x2apic already enabled.\n");
1764 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1765 x2apic_state = X2APIC_DISABLED;
1769 early_param("nox2apic", setup_nox2apic);
1771 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1772 void x2apic_setup(void)
1775 * If x2apic is not in ON state, disable it if already enabled
1778 if (x2apic_state != X2APIC_ON) {
1785 static __init void x2apic_disable(void)
1787 u32 x2apic_id, state = x2apic_state;
1790 x2apic_state = X2APIC_DISABLED;
1792 if (state != X2APIC_ON)
1795 x2apic_id = read_apic_id();
1796 if (x2apic_id >= 255)
1797 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1800 register_lapic_address(mp_lapic_addr);
1803 static __init void x2apic_enable(void)
1805 if (x2apic_state != X2APIC_OFF)
1809 x2apic_state = X2APIC_ON;
1813 static __init void try_to_enable_x2apic(int remap_mode)
1815 if (x2apic_state == X2APIC_DISABLED)
1818 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1820 * Using X2APIC without IR is not architecturally supported
1821 * on bare metal but may be supported in guests.
1823 if (!x86_init.hyper.x2apic_available()) {
1824 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1830 * Without IR, all CPUs can be addressed by IOAPIC/MSI only
1831 * in physical mode, and CPUs with an APIC ID that cannnot
1832 * be addressed must not be brought online.
1834 x2apic_set_max_apicid(255);
1840 void __init check_x2apic(void)
1842 if (x2apic_enabled()) {
1843 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1845 x2apic_state = X2APIC_ON;
1846 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1847 x2apic_state = X2APIC_DISABLED;
1850 #else /* CONFIG_X86_X2APIC */
1851 static int __init validate_x2apic(void)
1853 if (!apic_is_x2apic_enabled())
1856 * Checkme: Can we simply turn off x2apic here instead of panic?
1858 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1860 early_initcall(validate_x2apic);
1862 static inline void try_to_enable_x2apic(int remap_mode) { }
1863 static inline void __x2apic_enable(void) { }
1864 #endif /* !CONFIG_X86_X2APIC */
1866 void __init enable_IR_x2apic(void)
1868 unsigned long flags;
1871 if (skip_ioapic_setup) {
1872 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1876 ir_stat = irq_remapping_prepare();
1877 if (ir_stat < 0 && !x2apic_supported())
1880 ret = save_ioapic_entries();
1882 pr_info("Saving IO-APIC state failed: %d\n", ret);
1886 local_irq_save(flags);
1887 legacy_pic->mask_all();
1888 mask_ioapic_entries();
1890 /* If irq_remapping_prepare() succeeded, try to enable it */
1892 ir_stat = irq_remapping_enable();
1893 /* ir_stat contains the remap mode or an error code */
1894 try_to_enable_x2apic(ir_stat);
1897 restore_ioapic_entries();
1898 legacy_pic->restore_mask();
1899 local_irq_restore(flags);
1902 #ifdef CONFIG_X86_64
1904 * Detect and enable local APICs on non-SMP boards.
1905 * Original code written by Keir Fraser.
1906 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1907 * not correctly set up (usually the APIC timer won't work etc.)
1909 static int __init detect_init_APIC(void)
1911 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1912 pr_info("No local APIC present\n");
1916 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1921 static int __init apic_verify(void)
1926 * The APIC feature bit should now be enabled
1929 features = cpuid_edx(1);
1930 if (!(features & (1 << X86_FEATURE_APIC))) {
1931 pr_warning("Could not enable APIC!\n");
1934 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1935 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1937 /* The BIOS may have set up the APIC at some other address */
1938 if (boot_cpu_data.x86 >= 6) {
1939 rdmsr(MSR_IA32_APICBASE, l, h);
1940 if (l & MSR_IA32_APICBASE_ENABLE)
1941 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1944 pr_info("Found and enabled local APIC!\n");
1948 int __init apic_force_enable(unsigned long addr)
1956 * Some BIOSes disable the local APIC in the APIC_BASE
1957 * MSR. This can only be done in software for Intel P6 or later
1958 * and AMD K7 (Model > 1) or later.
1960 if (boot_cpu_data.x86 >= 6) {
1961 rdmsr(MSR_IA32_APICBASE, l, h);
1962 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1963 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1964 l &= ~MSR_IA32_APICBASE_BASE;
1965 l |= MSR_IA32_APICBASE_ENABLE | addr;
1966 wrmsr(MSR_IA32_APICBASE, l, h);
1967 enabled_via_apicbase = 1;
1970 return apic_verify();
1974 * Detect and initialize APIC
1976 static int __init detect_init_APIC(void)
1978 /* Disabled by kernel option? */
1982 switch (boot_cpu_data.x86_vendor) {
1983 case X86_VENDOR_AMD:
1984 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1985 (boot_cpu_data.x86 >= 15))
1988 case X86_VENDOR_INTEL:
1989 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1990 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1997 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1999 * Over-ride BIOS and try to enable the local APIC only if
2000 * "lapic" specified.
2002 if (!force_enable_local_apic) {
2003 pr_info("Local APIC disabled by BIOS -- "
2004 "you can enable it with \"lapic\"\n");
2007 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2019 pr_info("No local APIC present or hardware disabled\n");
2025 * init_apic_mappings - initialize APIC mappings
2027 void __init init_apic_mappings(void)
2029 unsigned int new_apicid;
2031 if (apic_validate_deadline_timer())
2032 pr_info("TSC deadline timer available\n");
2035 boot_cpu_physical_apicid = read_apic_id();
2039 /* If no local APIC can be found return early */
2040 if (!smp_found_config && detect_init_APIC()) {
2041 /* lets NOP'ify apic operations */
2042 pr_info("APIC: disable apic facility\n");
2045 apic_phys = mp_lapic_addr;
2048 * If the system has ACPI MADT tables or MP info, the LAPIC
2049 * address is already registered.
2051 if (!acpi_lapic && !smp_found_config)
2052 register_lapic_address(apic_phys);
2056 * Fetch the APIC ID of the BSP in case we have a
2057 * default configuration (or the MP table is broken).
2059 new_apicid = read_apic_id();
2060 if (boot_cpu_physical_apicid != new_apicid) {
2061 boot_cpu_physical_apicid = new_apicid;
2063 * yeah -- we lie about apic_version
2064 * in case if apic was disabled via boot option
2065 * but it's not a problem for SMP compiled kernel
2066 * since apic_intr_mode_select is prepared for such
2067 * a case and disable smp mode
2069 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2073 void __init register_lapic_address(unsigned long address)
2075 mp_lapic_addr = address;
2078 set_fixmap_nocache(FIX_APIC_BASE, address);
2079 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2080 APIC_BASE, address);
2082 if (boot_cpu_physical_apicid == -1U) {
2083 boot_cpu_physical_apicid = read_apic_id();
2084 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2089 * Local APIC interrupts
2093 * This interrupt should _never_ happen with our APIC/SMP architecture
2095 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2097 u8 vector = ~regs->orig_ax;
2101 trace_spurious_apic_entry(vector);
2103 inc_irq_stat(irq_spurious_count);
2106 * If this is a spurious interrupt then do not acknowledge
2108 if (vector == SPURIOUS_APIC_VECTOR) {
2110 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2111 smp_processor_id());
2116 * If it is a vectored one, verify it's set in the ISR. If set,
2119 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2120 if (v & (1 << (vector & 0x1f))) {
2121 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2122 vector, smp_processor_id());
2125 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2126 vector, smp_processor_id());
2129 trace_spurious_apic_exit(vector);
2134 * This interrupt should never happen with our APIC/SMP architecture
2136 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2138 static const char * const error_interrupt_reason[] = {
2139 "Send CS error", /* APIC Error Bit 0 */
2140 "Receive CS error", /* APIC Error Bit 1 */
2141 "Send accept error", /* APIC Error Bit 2 */
2142 "Receive accept error", /* APIC Error Bit 3 */
2143 "Redirectable IPI", /* APIC Error Bit 4 */
2144 "Send illegal vector", /* APIC Error Bit 5 */
2145 "Received illegal vector", /* APIC Error Bit 6 */
2146 "Illegal register address", /* APIC Error Bit 7 */
2151 trace_error_apic_entry(ERROR_APIC_VECTOR);
2153 /* First tickle the hardware, only then report what went on. -- REW */
2154 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2155 apic_write(APIC_ESR, 0);
2156 v = apic_read(APIC_ESR);
2158 atomic_inc(&irq_err_count);
2160 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2161 smp_processor_id(), v);
2166 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2171 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2173 trace_error_apic_exit(ERROR_APIC_VECTOR);
2178 * connect_bsp_APIC - attach the APIC to the interrupt system
2180 static void __init connect_bsp_APIC(void)
2182 #ifdef CONFIG_X86_32
2185 * Do not trust the local APIC being empty at bootup.
2189 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2190 * local APIC to INT and NMI lines.
2192 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2193 "enabling APIC mode.\n");
2200 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2201 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2203 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2206 void disconnect_bsp_APIC(int virt_wire_setup)
2210 #ifdef CONFIG_X86_32
2213 * Put the board back into PIC mode (has an effect only on
2214 * certain older boards). Note that APIC interrupts, including
2215 * IPIs, won't work beyond this point! The only exception are
2218 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2219 "entering PIC mode.\n");
2225 /* Go back to Virtual Wire compatibility mode */
2227 /* For the spurious interrupt use vector F, and enable it */
2228 value = apic_read(APIC_SPIV);
2229 value &= ~APIC_VECTOR_MASK;
2230 value |= APIC_SPIV_APIC_ENABLED;
2232 apic_write(APIC_SPIV, value);
2234 if (!virt_wire_setup) {
2236 * For LVT0 make it edge triggered, active high,
2237 * external and enabled
2239 value = apic_read(APIC_LVT0);
2240 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2241 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2242 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2243 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2244 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2245 apic_write(APIC_LVT0, value);
2248 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2252 * For LVT1 make it edge triggered, active high,
2255 value = apic_read(APIC_LVT1);
2256 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2257 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2258 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2259 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2260 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2261 apic_write(APIC_LVT1, value);
2265 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2266 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2267 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2268 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2270 * NOTE: Reserve 0 for BSP.
2272 static int nr_logical_cpuids = 1;
2275 * Used to store mapping between logical CPU IDs and APIC IDs.
2277 static int cpuid_to_apicid[] = {
2278 [0 ... NR_CPUS - 1] = -1,
2281 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
2283 return phys_id == cpuid_to_apicid[cpu];
2288 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2289 * @id: APIC ID to check
2291 bool apic_id_is_primary_thread(unsigned int apicid)
2295 if (smp_num_siblings == 1)
2297 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2298 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2299 return !(apicid & mask);
2304 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2305 * and cpuid_to_apicid[] synchronized.
2307 static int allocate_logical_cpuid(int apicid)
2312 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2313 * check if the kernel has allocated a cpuid for it.
2315 for (i = 0; i < nr_logical_cpuids; i++) {
2316 if (cpuid_to_apicid[i] == apicid)
2320 /* Allocate a new cpuid. */
2321 if (nr_logical_cpuids >= nr_cpu_ids) {
2322 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2323 "Processor %d/0x%x and the rest are ignored.\n",
2324 nr_cpu_ids, nr_logical_cpuids, apicid);
2328 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2329 return nr_logical_cpuids++;
2332 int generic_processor_info(int apicid, int version)
2334 int cpu, max = nr_cpu_ids;
2335 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2336 phys_cpu_present_map);
2339 * boot_cpu_physical_apicid is designed to have the apicid
2340 * returned by read_apic_id(), i.e, the apicid of the
2341 * currently booting-up processor. However, on some platforms,
2342 * it is temporarily modified by the apicid reported as BSP
2343 * through MP table. Concretely:
2345 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2346 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2348 * This function is executed with the modified
2349 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2350 * parameter doesn't work to disable APs on kdump 2nd kernel.
2352 * Since fixing handling of boot_cpu_physical_apicid requires
2353 * another discussion and tests on each platform, we leave it
2354 * for now and here we use read_apic_id() directly in this
2355 * function, generic_processor_info().
2357 if (disabled_cpu_apicid != BAD_APICID &&
2358 disabled_cpu_apicid != read_apic_id() &&
2359 disabled_cpu_apicid == apicid) {
2360 int thiscpu = num_processors + disabled_cpus;
2362 pr_warning("APIC: Disabling requested cpu."
2363 " Processor %d/0x%x ignored.\n",
2371 * If boot cpu has not been detected yet, then only allow upto
2372 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2374 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2375 apicid != boot_cpu_physical_apicid) {
2376 int thiscpu = max + disabled_cpus - 1;
2379 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2380 " reached. Keeping one slot for boot cpu."
2381 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2387 if (num_processors >= nr_cpu_ids) {
2388 int thiscpu = max + disabled_cpus;
2390 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2391 "reached. Processor %d/0x%x ignored.\n",
2392 max, thiscpu, apicid);
2398 if (apicid == boot_cpu_physical_apicid) {
2400 * x86_bios_cpu_apicid is required to have processors listed
2401 * in same order as logical cpu numbers. Hence the first
2402 * entry is BSP, and so on.
2403 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2408 /* Logical cpuid 0 is reserved for BSP. */
2409 cpuid_to_apicid[0] = apicid;
2411 cpu = allocate_logical_cpuid(apicid);
2421 if (version == 0x0) {
2422 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2427 if (version != boot_cpu_apic_version) {
2428 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2429 boot_cpu_apic_version, cpu, version);
2432 if (apicid > max_physical_apicid)
2433 max_physical_apicid = apicid;
2435 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2436 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2437 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2439 #ifdef CONFIG_X86_32
2440 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2441 apic->x86_32_early_logical_apicid(cpu);
2443 set_cpu_possible(cpu, true);
2444 physid_set(apicid, phys_cpu_present_map);
2445 set_cpu_present(cpu, true);
2451 int hard_smp_processor_id(void)
2453 return read_apic_id();
2457 * Override the generic EOI implementation with an optimized version.
2458 * Only called during early boot when only one CPU is active and with
2459 * interrupts disabled, so we know this does not race with actual APIC driver
2462 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2466 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2467 /* Should happen once for each apic */
2468 WARN_ON((*drv)->eoi_write == eoi_write);
2469 (*drv)->native_eoi_write = (*drv)->eoi_write;
2470 (*drv)->eoi_write = eoi_write;
2474 static void __init apic_bsp_up_setup(void)
2476 #ifdef CONFIG_X86_64
2477 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2480 * Hack: In case of kdump, after a crash, kernel might be booting
2481 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2482 * might be zero if read from MP tables. Get it from LAPIC.
2484 # ifdef CONFIG_CRASH_DUMP
2485 boot_cpu_physical_apicid = read_apic_id();
2488 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2492 * apic_bsp_setup - Setup function for local apic and io-apic
2493 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2496 * apic_id of BSP APIC
2498 void __init apic_bsp_setup(bool upmode)
2502 apic_bsp_up_setup();
2506 end_local_APIC_setup();
2507 irq_remap_enable_fault_handling();
2509 lapic_update_legacy_vectors();
2512 #ifdef CONFIG_UP_LATE_INIT
2513 void __init up_late_init(void)
2515 if (apic_intr_mode == APIC_PIC)
2518 /* Setup local timer */
2519 x86_init.timers.setup_percpu_clockev();
2530 * 'active' is true if the local APIC was enabled by us and
2531 * not the BIOS; this signifies that we are also responsible
2532 * for disabling it before entering apm/acpi suspend
2535 /* r/w apic fields */
2536 unsigned int apic_id;
2537 unsigned int apic_taskpri;
2538 unsigned int apic_ldr;
2539 unsigned int apic_dfr;
2540 unsigned int apic_spiv;
2541 unsigned int apic_lvtt;
2542 unsigned int apic_lvtpc;
2543 unsigned int apic_lvt0;
2544 unsigned int apic_lvt1;
2545 unsigned int apic_lvterr;
2546 unsigned int apic_tmict;
2547 unsigned int apic_tdcr;
2548 unsigned int apic_thmr;
2549 unsigned int apic_cmci;
2552 static int lapic_suspend(void)
2554 unsigned long flags;
2557 if (!apic_pm_state.active)
2560 maxlvt = lapic_get_maxlvt();
2562 apic_pm_state.apic_id = apic_read(APIC_ID);
2563 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2564 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2565 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2566 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2567 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2569 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2570 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2571 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2572 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2573 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2574 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2575 #ifdef CONFIG_X86_THERMAL_VECTOR
2577 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2579 #ifdef CONFIG_X86_MCE_INTEL
2581 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2584 local_irq_save(flags);
2585 disable_local_APIC();
2587 irq_remapping_disable();
2589 local_irq_restore(flags);
2593 static void lapic_resume(void)
2596 unsigned long flags;
2599 if (!apic_pm_state.active)
2602 local_irq_save(flags);
2605 * IO-APIC and PIC have their own resume routines.
2606 * We just mask them here to make sure the interrupt
2607 * subsystem is completely quiet while we enable x2apic
2608 * and interrupt-remapping.
2610 mask_ioapic_entries();
2611 legacy_pic->mask_all();
2617 * Make sure the APICBASE points to the right address
2619 * FIXME! This will be wrong if we ever support suspend on
2620 * SMP! We'll need to do this as part of the CPU restore!
2622 if (boot_cpu_data.x86 >= 6) {
2623 rdmsr(MSR_IA32_APICBASE, l, h);
2624 l &= ~MSR_IA32_APICBASE_BASE;
2625 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2626 wrmsr(MSR_IA32_APICBASE, l, h);
2630 maxlvt = lapic_get_maxlvt();
2631 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2632 apic_write(APIC_ID, apic_pm_state.apic_id);
2633 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2634 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2635 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2636 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2637 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2638 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2639 #ifdef CONFIG_X86_THERMAL_VECTOR
2641 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2643 #ifdef CONFIG_X86_MCE_INTEL
2645 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2648 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2649 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2650 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2651 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2652 apic_write(APIC_ESR, 0);
2653 apic_read(APIC_ESR);
2654 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2655 apic_write(APIC_ESR, 0);
2656 apic_read(APIC_ESR);
2658 irq_remapping_reenable(x2apic_mode);
2660 local_irq_restore(flags);
2664 * This device has no shutdown method - fully functioning local APICs
2665 * are needed on every CPU up until machine_halt/restart/poweroff.
2668 static struct syscore_ops lapic_syscore_ops = {
2669 .resume = lapic_resume,
2670 .suspend = lapic_suspend,
2673 static void apic_pm_activate(void)
2675 apic_pm_state.active = 1;
2678 static int __init init_lapic_sysfs(void)
2680 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2681 if (boot_cpu_has(X86_FEATURE_APIC))
2682 register_syscore_ops(&lapic_syscore_ops);
2687 /* local apic needs to resume before other devices access its registers. */
2688 core_initcall(init_lapic_sysfs);
2690 #else /* CONFIG_PM */
2692 static void apic_pm_activate(void) { }
2694 #endif /* CONFIG_PM */
2696 #ifdef CONFIG_X86_64
2698 static int multi_checked;
2701 static int set_multi(const struct dmi_system_id *d)
2705 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2710 static const struct dmi_system_id multi_dmi_table[] = {
2712 .callback = set_multi,
2713 .ident = "IBM System Summit2",
2715 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2716 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2722 static void dmi_check_multi(void)
2727 dmi_check_system(multi_dmi_table);
2732 * apic_is_clustered_box() -- Check if we can expect good TSC
2734 * Thus far, the major user of this is IBM's Summit2 series:
2735 * Clustered boxes may have unsynced TSC problems if they are
2737 * Use DMI to check them
2739 int apic_is_clustered_box(void)
2747 * APIC command line parameters
2749 static int __init setup_disableapic(char *arg)
2752 setup_clear_cpu_cap(X86_FEATURE_APIC);
2755 early_param("disableapic", setup_disableapic);
2757 /* same as disableapic, for compatibility */
2758 static int __init setup_nolapic(char *arg)
2760 return setup_disableapic(arg);
2762 early_param("nolapic", setup_nolapic);
2764 static int __init parse_lapic_timer_c2_ok(char *arg)
2766 local_apic_timer_c2_ok = 1;
2769 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2771 static int __init parse_disable_apic_timer(char *arg)
2773 disable_apic_timer = 1;
2776 early_param("noapictimer", parse_disable_apic_timer);
2778 static int __init parse_nolapic_timer(char *arg)
2780 disable_apic_timer = 1;
2783 early_param("nolapic_timer", parse_nolapic_timer);
2785 static int __init apic_set_verbosity(char *arg)
2788 #ifdef CONFIG_X86_64
2789 skip_ioapic_setup = 0;
2795 if (strcmp("debug", arg) == 0)
2796 apic_verbosity = APIC_DEBUG;
2797 else if (strcmp("verbose", arg) == 0)
2798 apic_verbosity = APIC_VERBOSE;
2799 #ifdef CONFIG_X86_64
2801 pr_warning("APIC Verbosity level %s not recognised"
2802 " use apic=verbose or apic=debug\n", arg);
2809 early_param("apic", apic_set_verbosity);
2811 static int __init lapic_insert_resource(void)
2816 /* Put local APIC into the resource map. */
2817 lapic_resource.start = apic_phys;
2818 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2819 insert_resource(&iomem_resource, &lapic_resource);
2825 * need call insert after e820__reserve_resources()
2826 * that is using request_resource
2828 late_initcall(lapic_insert_resource);
2830 static int __init apic_set_disabled_cpu_apicid(char *arg)
2832 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2837 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2839 static int __init apic_set_extnmi(char *arg)
2844 if (!strncmp("all", arg, 3))
2845 apic_extnmi = APIC_EXTNMI_ALL;
2846 else if (!strncmp("none", arg, 4))
2847 apic_extnmi = APIC_EXTNMI_NONE;
2848 else if (!strncmp("bsp", arg, 3))
2849 apic_extnmi = APIC_EXTNMI_BSP;
2851 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2857 early_param("apic_extnmi", apic_set_extnmi);