2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
37 #include <linux/irq.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <asm/pgalloc.h>
44 #include <linux/atomic.h>
45 #include <asm/barrier.h>
46 #include <asm/mpspec.h>
47 #include <asm/i8259.h>
48 #include <asm/proto.h>
50 #include <asm/io_apic.h>
58 #include <asm/hypervisor.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/intel-family.h>
61 #include <asm/irq_regs.h>
63 unsigned int num_processors;
65 unsigned disabled_cpus;
67 /* Processor that is doing the boot up */
68 unsigned int boot_cpu_physical_apicid = -1U;
69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
71 u8 boot_cpu_apic_version;
74 * The highest APIC ID seen during enumeration.
76 static unsigned int max_physical_apicid;
79 * Bitmask of physically existing CPUs:
81 physid_mask_t phys_cpu_present_map;
84 * Processor to be disabled specified by kernel parameter
85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
86 * avoid undefined behaviour caused by sending INIT from AP to BSP.
88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
91 * This variable controls which CPUs receive external NMIs. By default,
92 * external NMIs are delivered only to the BSP.
94 static int apic_extnmi = APIC_EXTNMI_BSP;
97 * Map cpu index to physical APIC ID
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
109 * On x86_32, the mapping between cpu and logical apicid may vary
110 * depending on apic in use. The following early percpu variable is
111 * used for the mapping. This is where the behaviors of x86_64 and 32
112 * actually diverge. Let's keep it ugly for now.
114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
116 /* Local APIC was disabled by the BIOS and enabled by the kernel */
117 static int enabled_via_apicbase;
120 * Handle interrupt mode configuration register (IMCR).
121 * This register controls whether the interrupt signals
122 * that reach the BSP come from the master PIC or from the
123 * local APIC. Before entering Symmetric I/O Mode, either
124 * the BIOS or the operating system must switch out of
125 * PIC Mode by changing the IMCR.
127 static inline void imcr_pic_to_apic(void)
129 /* select IMCR register */
131 /* NMI and 8259 INTR go through APIC */
135 static inline void imcr_apic_to_pic(void)
137 /* select IMCR register */
139 /* NMI and 8259 INTR go directly to BSP */
145 * Knob to control our willingness to enable the local APIC.
149 static int force_enable_local_apic __initdata;
152 * APIC command line parameters
154 static int __init parse_lapic(char *arg)
156 if (IS_ENABLED(CONFIG_X86_32) && !arg)
157 force_enable_local_apic = 1;
158 else if (arg && !strncmp(arg, "notscdeadline", 13))
159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
162 early_param("lapic", parse_lapic);
165 static int apic_calibrate_pmtmr __initdata;
166 static __init int setup_apicpmtimer(char *s)
168 apic_calibrate_pmtmr = 1;
172 __setup("apicpmtimer", setup_apicpmtimer);
175 unsigned long mp_lapic_addr;
177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
178 static int disable_apic_timer __initdata;
179 /* Local APIC timer works in C2 */
180 int local_apic_timer_c2_ok;
181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
184 * Debug level, exported for io_apic.c
190 /* Have we found an MP table */
191 int smp_found_config;
193 static struct resource lapic_resource = {
194 .name = "Local APIC",
195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
198 unsigned int lapic_timer_frequency = 0;
200 static void apic_pm_activate(void);
202 static unsigned long apic_phys;
205 * Get the LAPIC version
207 static inline int lapic_get_version(void)
209 return GET_APIC_VERSION(apic_read(APIC_LVR));
213 * Check, if the APIC is integrated or a separate chip
215 static inline int lapic_is_integrated(void)
220 return APIC_INTEGRATED(lapic_get_version());
225 * Check, whether this is a modern or a first generation APIC
227 static int modern_apic(void)
229 /* AMD systems use old APIC versions, so check the CPU */
230 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
231 boot_cpu_data.x86 >= 0xf)
233 return lapic_get_version() >= 0x14;
237 * right after this call apic become NOOP driven
238 * so apic->write/read doesn't do anything
240 static void __init apic_disable(void)
242 pr_info("APIC: switched to apic NOOP\n");
246 void native_apic_wait_icr_idle(void)
248 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
252 u32 native_safe_apic_wait_icr_idle(void)
259 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
262 inc_irq_stat(icr_read_retry_count);
264 } while (timeout++ < 1000);
269 void native_apic_icr_write(u32 low, u32 id)
273 local_irq_save(flags);
274 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
275 apic_write(APIC_ICR, low);
276 local_irq_restore(flags);
279 u64 native_apic_icr_read(void)
283 icr2 = apic_read(APIC_ICR2);
284 icr1 = apic_read(APIC_ICR);
286 return icr1 | ((u64)icr2 << 32);
291 * get_physical_broadcast - Get number of physical broadcast IDs
293 int get_physical_broadcast(void)
295 return modern_apic() ? 0xff : 0xf;
300 * lapic_get_maxlvt - get the maximum number of local vector table entries
302 int lapic_get_maxlvt(void)
306 v = apic_read(APIC_LVR);
308 * - we always have APIC integrated on 64bit mode
309 * - 82489DXs do not report # of LVT entries
311 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
319 #define APIC_DIVISOR 16
320 #define TSC_DIVISOR 8
323 * This function sets up the local APIC timer, with a timeout of
324 * 'clocks' APIC bus clock. During calibration we actually call
325 * this function twice on the boot CPU, once with a bogus timeout
326 * value, second time for real. The other (noncalibrating) CPUs
327 * call this function only once, with the real, calibrated value.
329 * We do reads before writes even if unnecessary, to get around the
330 * P5 APIC double write bug.
332 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
334 unsigned int lvtt_value, tmp_value;
336 lvtt_value = LOCAL_TIMER_VECTOR;
338 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
339 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
340 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
342 if (!lapic_is_integrated())
343 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
346 lvtt_value |= APIC_LVT_MASKED;
348 apic_write(APIC_LVTT, lvtt_value);
350 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
352 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
353 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
354 * According to Intel, MFENCE can do the serialization here.
356 asm volatile("mfence" : : : "memory");
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
373 * Setup extended LVT, AMD specific
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 unsigned int rsvd, vector;
405 if (offset >= APIC_EILVT_NR_MAX)
408 rsvd = atomic_read(&eilvt_offsets[offset]);
410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
411 if (vector && !eilvt_entry_is_changeable(vector, new))
412 /* may not change if vectors are different */
414 } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
416 rsvd = new & ~APIC_EILVT_MASKED;
417 if (rsvd && rsvd != vector)
418 pr_info("LVT offset %d assigned for vector 0x%02x\n",
425 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 * enables the vector. See also the BKDGs. Must be called with
427 * preemption disabled.
430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 unsigned long reg = APIC_EILVTn(offset);
433 unsigned int new, old, reserved;
435 new = (mask << 16) | (msg_type << 8) | vector;
436 old = apic_read(reg);
437 reserved = reserve_eilvt_offset(offset, new);
439 if (reserved != new) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on another cpu\n",
443 smp_processor_id(), reg, offset, new, reserved);
447 if (!eilvt_entry_is_changeable(old, new)) {
448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
449 "vector 0x%x, but the register is already in use for "
450 "vector 0x%x on this cpu\n",
451 smp_processor_id(), reg, offset, new, old);
455 apic_write(reg, new);
459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
462 * Program the next event, relative to now
464 static int lapic_next_event(unsigned long delta,
465 struct clock_event_device *evt)
467 apic_write(APIC_TMICT, delta);
471 static int lapic_next_deadline(unsigned long delta,
472 struct clock_event_device *evt)
476 /* This MSR is special and need a special fence: */
480 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
484 static int lapic_timer_shutdown(struct clock_event_device *evt)
488 /* Lapic used as dummy for broadcast ? */
489 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
492 v = apic_read(APIC_LVTT);
493 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
494 apic_write(APIC_LVTT, v);
495 apic_write(APIC_TMICT, 0);
500 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
502 /* Lapic used as dummy for broadcast ? */
503 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
506 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
510 static int lapic_timer_set_periodic(struct clock_event_device *evt)
512 return lapic_timer_set_periodic_oneshot(evt, false);
515 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
517 return lapic_timer_set_periodic_oneshot(evt, true);
521 * Local APIC timer broadcast function
523 static void lapic_timer_broadcast(const struct cpumask *mask)
526 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
532 * The local apic timer can be used for any function which is CPU local.
534 static struct clock_event_device lapic_clockevent = {
536 .features = CLOCK_EVT_FEAT_PERIODIC |
537 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
538 | CLOCK_EVT_FEAT_DUMMY,
540 .set_state_shutdown = lapic_timer_shutdown,
541 .set_state_periodic = lapic_timer_set_periodic,
542 .set_state_oneshot = lapic_timer_set_oneshot,
543 .set_state_oneshot_stopped = lapic_timer_shutdown,
544 .set_next_event = lapic_next_event,
545 .broadcast = lapic_timer_broadcast,
549 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
551 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
552 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
554 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
555 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
557 static __init u32 hsx_deadline_rev(void)
559 switch (boot_cpu_data.x86_stepping) {
560 case 0x02: return 0x3a; /* EP */
561 case 0x04: return 0x0f; /* EX */
567 static __init u32 bdx_deadline_rev(void)
569 switch (boot_cpu_data.x86_stepping) {
570 case 0x02: return 0x00000011;
571 case 0x03: return 0x0700000e;
572 case 0x04: return 0x0f00000c;
573 case 0x05: return 0x0e000003;
579 static __init u32 skx_deadline_rev(void)
581 switch (boot_cpu_data.x86_stepping) {
582 case 0x03: return 0x01000136;
583 case 0x04: return 0x02000014;
586 if (boot_cpu_data.x86_stepping > 4)
592 static const struct x86_cpu_id deadline_match[] __initconst = {
593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
595 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
596 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
602 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
605 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
608 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
609 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
614 static __init bool apic_validate_deadline_timer(void)
616 const struct x86_cpu_id *m;
619 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
621 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
624 m = x86_match_cpu(deadline_match);
629 * Function pointers will have the MSB set due to address layout,
630 * immediate revisions will not.
632 if ((long)m->driver_data < 0)
633 rev = ((u32 (*)(void))(m->driver_data))();
635 rev = (u32)m->driver_data;
637 if (boot_cpu_data.microcode >= rev)
640 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
641 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
642 "/*(DEBLOBBED)*/\n", rev);
647 * Setup the local APIC timer for this CPU. Copy the initialized values
648 * of the boot CPU and register the clock event in the framework.
650 static void setup_APIC_timer(void)
652 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
654 if (this_cpu_has(X86_FEATURE_ARAT)) {
655 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
656 /* Make LAPIC timer preferrable over percpu HPET */
657 lapic_clockevent.rating = 150;
660 memcpy(levt, &lapic_clockevent, sizeof(*levt));
661 levt->cpumask = cpumask_of(smp_processor_id());
663 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
664 levt->name = "lapic-deadline";
665 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
666 CLOCK_EVT_FEAT_DUMMY);
667 levt->set_next_event = lapic_next_deadline;
668 clockevents_config_and_register(levt,
669 tsc_khz * (1000 / TSC_DIVISOR),
672 clockevents_register_device(levt);
676 * Install the updated TSC frequency from recalibration at the TSC
677 * deadline clockevent devices.
679 static void __lapic_update_tsc_freq(void *info)
681 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
683 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
686 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
689 void lapic_update_tsc_freq(void)
692 * The clockevent device's ->mult and ->shift can both be
693 * changed. In order to avoid races, schedule the frequency
694 * update code on each CPU.
696 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
700 * In this functions we calibrate APIC bus clocks to the external timer.
702 * We want to do the calibration only once since we want to have local timer
703 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
706 * This was previously done by reading the PIT/HPET and waiting for a wrap
707 * around to find out, that a tick has elapsed. I have a box, where the PIT
708 * readout is broken, so it never gets out of the wait loop again. This was
709 * also reported by others.
711 * Monitoring the jiffies value is inaccurate and the clockevents
712 * infrastructure allows us to do a simple substitution of the interrupt
715 * The calibration routine also uses the pm_timer when possible, as the PIT
716 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
717 * back to normal later in the boot process).
720 #define LAPIC_CAL_LOOPS (HZ/10)
722 static __initdata int lapic_cal_loops = -1;
723 static __initdata long lapic_cal_t1, lapic_cal_t2;
724 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
725 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
726 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
729 * Temporary interrupt handler and polled calibration function.
731 static void __init lapic_cal_handler(struct clock_event_device *dev)
733 unsigned long long tsc = 0;
734 long tapic = apic_read(APIC_TMCCT);
735 unsigned long pm = acpi_pm_read_early();
737 if (boot_cpu_has(X86_FEATURE_TSC))
740 switch (lapic_cal_loops++) {
742 lapic_cal_t1 = tapic;
743 lapic_cal_tsc1 = tsc;
745 lapic_cal_j1 = jiffies;
748 case LAPIC_CAL_LOOPS:
749 lapic_cal_t2 = tapic;
750 lapic_cal_tsc2 = tsc;
751 if (pm < lapic_cal_pm1)
752 pm += ACPI_PM_OVRRUN;
754 lapic_cal_j2 = jiffies;
760 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
762 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
763 const long pm_thresh = pm_100ms / 100;
767 #ifndef CONFIG_X86_PM_TIMER
771 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
773 /* Check, if the PM timer is available */
777 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
779 if (deltapm > (pm_100ms - pm_thresh) &&
780 deltapm < (pm_100ms + pm_thresh)) {
781 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
785 res = (((u64)deltapm) * mult) >> 22;
786 do_div(res, 1000000);
787 pr_warning("APIC calibration not consistent "
788 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
790 /* Correct the lapic counter value */
791 res = (((u64)(*delta)) * pm_100ms);
792 do_div(res, deltapm);
793 pr_info("APIC delta adjusted to PM-Timer: "
794 "%lu (%ld)\n", (unsigned long)res, *delta);
797 /* Correct the tsc counter value */
798 if (boot_cpu_has(X86_FEATURE_TSC)) {
799 res = (((u64)(*deltatsc)) * pm_100ms);
800 do_div(res, deltapm);
801 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
802 "PM-Timer: %lu (%ld)\n",
803 (unsigned long)res, *deltatsc);
804 *deltatsc = (long)res;
810 static int __init calibrate_APIC_clock(void)
812 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
813 u64 tsc_perj = 0, tsc_start = 0;
814 unsigned long jif_start;
815 unsigned long deltaj;
816 long delta, deltatsc;
817 int pm_referenced = 0;
820 * check if lapic timer has already been calibrated by platform
821 * specific routine, such as tsc calibration code. if so, we just fill
822 * in the clockevent structure and return.
825 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
827 } else if (lapic_timer_frequency) {
828 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
829 lapic_timer_frequency);
830 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
831 TICK_NSEC, lapic_clockevent.shift);
832 lapic_clockevent.max_delta_ns =
833 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
834 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
835 lapic_clockevent.min_delta_ns =
836 clockevent_delta2ns(0xF, &lapic_clockevent);
837 lapic_clockevent.min_delta_ticks = 0xF;
838 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
842 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
843 "calibrating APIC timer ...\n");
846 * There are platforms w/o global clockevent devices. Instead of
847 * making the calibration conditional on that, use a polling based
848 * approach everywhere.
853 * Setup the APIC counter to maximum. There is no way the lapic
854 * can underflow in the 100ms detection time frame
856 __setup_APIC_LVTT(0xffffffff, 0, 0);
859 * Methods to terminate the calibration loop:
860 * 1) Global clockevent if available (jiffies)
861 * 2) TSC if available and frequency is known
863 jif_start = READ_ONCE(jiffies);
867 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
871 * Enable interrupts so the tick can fire, if a global
872 * clockevent device is available
876 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
877 /* Wait for a tick to elapse */
880 u64 tsc_now = rdtsc();
881 if ((tsc_now - tsc_start) >= tsc_perj) {
882 tsc_start += tsc_perj;
886 unsigned long jif_now = READ_ONCE(jiffies);
888 if (time_after(jif_now, jif_start)) {
896 /* Invoke the calibration routine */
898 lapic_cal_handler(NULL);
904 /* Build delta t1-t2 as apic timer counts down */
905 delta = lapic_cal_t1 - lapic_cal_t2;
906 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
908 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
910 /* we trust the PM based calibration if possible */
911 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
914 /* Calculate the scaled math multiplication factor */
915 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
916 lapic_clockevent.shift);
917 lapic_clockevent.max_delta_ns =
918 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
919 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
920 lapic_clockevent.min_delta_ns =
921 clockevent_delta2ns(0xF, &lapic_clockevent);
922 lapic_clockevent.min_delta_ticks = 0xF;
924 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
926 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
927 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
928 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
929 lapic_timer_frequency);
931 if (boot_cpu_has(X86_FEATURE_TSC)) {
932 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
934 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
935 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
938 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
940 lapic_timer_frequency / (1000000 / HZ),
941 lapic_timer_frequency % (1000000 / HZ));
944 * Do a sanity check on the APIC calibration result
946 if (lapic_timer_frequency < (1000000 / HZ)) {
948 pr_warning("APIC frequency too slow, disabling apic timer\n");
952 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
955 * PM timer calibration failed or not turned on so lets try APIC
956 * timer based calibration, if a global clockevent device is
959 if (!pm_referenced && global_clock_event) {
960 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
963 * Setup the apic timer manually
965 levt->event_handler = lapic_cal_handler;
966 lapic_timer_set_periodic(levt);
967 lapic_cal_loops = -1;
969 /* Let the interrupts run */
972 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
975 /* Stop the lapic timer */
977 lapic_timer_shutdown(levt);
980 deltaj = lapic_cal_j2 - lapic_cal_j1;
981 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
983 /* Check, if the jiffies result is consistent */
984 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
985 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
987 levt->features |= CLOCK_EVT_FEAT_DUMMY;
991 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
992 pr_warning("APIC timer disabled due to verification failure\n");
1000 * Setup the boot APIC
1002 * Calibrate and verify the result.
1004 void __init setup_boot_APIC_clock(void)
1007 * The local apic timer can be disabled via the kernel
1008 * commandline or from the CPU detection code. Register the lapic
1009 * timer as a dummy clock event source on SMP systems, so the
1010 * broadcast mechanism is used. On UP systems simply ignore it.
1012 if (disable_apic_timer) {
1013 pr_info("Disabling APIC timer\n");
1014 /* No broadcast on UP ! */
1015 if (num_possible_cpus() > 1) {
1016 lapic_clockevent.mult = 1;
1022 if (calibrate_APIC_clock()) {
1023 /* No broadcast on UP ! */
1024 if (num_possible_cpus() > 1)
1030 * If nmi_watchdog is set to IO_APIC, we need the
1031 * PIT/HPET going. Otherwise register lapic as a dummy
1034 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1036 /* Setup the lapic or request the broadcast */
1038 amd_e400_c1e_apic_setup();
1041 void setup_secondary_APIC_clock(void)
1044 amd_e400_c1e_apic_setup();
1048 * The guts of the apic timer interrupt
1050 static void local_apic_timer_interrupt(void)
1052 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1055 * Normally we should not be here till LAPIC has been initialized but
1056 * in some cases like kdump, its possible that there is a pending LAPIC
1057 * timer interrupt from previous kernel's context and is delivered in
1058 * new kernel the moment interrupts are enabled.
1060 * Interrupts are enabled early and LAPIC is setup much later, hence
1061 * its possible that when we get here evt->event_handler is NULL.
1062 * Check for event_handler being NULL and discard the interrupt as
1065 if (!evt->event_handler) {
1066 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1067 smp_processor_id());
1069 lapic_timer_shutdown(evt);
1074 * the NMI deadlock-detector uses this.
1076 inc_irq_stat(apic_timer_irqs);
1078 evt->event_handler(evt);
1082 * Local APIC timer interrupt. This is the most natural way for doing
1083 * local interrupts, but local timer interrupts can be emulated by
1084 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1086 * [ if a single-CPU system runs an SMP kernel then we call the local
1087 * interrupt as well. Thus we cannot inline the local irq ... ]
1089 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1091 struct pt_regs *old_regs = set_irq_regs(regs);
1094 * NOTE! We'd better ACK the irq immediately,
1095 * because timer handling can be slow.
1097 * update_process_times() expects us to have done irq_enter().
1098 * Besides, if we don't timer interrupts ignore the global
1099 * interrupt lock, which is the WrongThing (tm) to do.
1102 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1103 local_apic_timer_interrupt();
1104 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1107 set_irq_regs(old_regs);
1110 int setup_profiling_timer(unsigned int multiplier)
1116 * Local APIC start and shutdown
1120 * clear_local_APIC - shutdown the local APIC
1122 * This is called, when a CPU is disabled and before rebooting, so the state of
1123 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1124 * leftovers during boot.
1126 void clear_local_APIC(void)
1131 /* APIC hasn't been mapped yet */
1132 if (!x2apic_mode && !apic_phys)
1135 maxlvt = lapic_get_maxlvt();
1137 * Masking an LVT entry can trigger a local APIC error
1138 * if the vector is zero. Mask LVTERR first to prevent this.
1141 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1142 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1145 * Careful: we have to set masks only first to deassert
1146 * any level-triggered sources.
1148 v = apic_read(APIC_LVTT);
1149 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1150 v = apic_read(APIC_LVT0);
1151 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1152 v = apic_read(APIC_LVT1);
1153 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1155 v = apic_read(APIC_LVTPC);
1156 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1159 /* lets not touch this if we didn't frob it */
1160 #ifdef CONFIG_X86_THERMAL_VECTOR
1162 v = apic_read(APIC_LVTTHMR);
1163 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1166 #ifdef CONFIG_X86_MCE_INTEL
1168 v = apic_read(APIC_LVTCMCI);
1169 if (!(v & APIC_LVT_MASKED))
1170 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1175 * Clean APIC state for other OSs:
1177 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1178 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1179 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1181 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1183 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1185 /* Integrated APIC (!82489DX) ? */
1186 if (lapic_is_integrated()) {
1188 /* Clear ESR due to Pentium errata 3AP and 11AP */
1189 apic_write(APIC_ESR, 0);
1190 apic_read(APIC_ESR);
1195 * disable_local_APIC - clear and disable the local APIC
1197 void disable_local_APIC(void)
1201 /* APIC hasn't been mapped yet */
1202 if (!x2apic_mode && !apic_phys)
1208 * Disable APIC (implies clearing of registers
1211 value = apic_read(APIC_SPIV);
1212 value &= ~APIC_SPIV_APIC_ENABLED;
1213 apic_write(APIC_SPIV, value);
1215 #ifdef CONFIG_X86_32
1217 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1218 * restore the disabled state.
1220 if (enabled_via_apicbase) {
1223 rdmsr(MSR_IA32_APICBASE, l, h);
1224 l &= ~MSR_IA32_APICBASE_ENABLE;
1225 wrmsr(MSR_IA32_APICBASE, l, h);
1231 * If Linux enabled the LAPIC against the BIOS default disable it down before
1232 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1233 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1234 * for the case where Linux didn't enable the LAPIC.
1236 void lapic_shutdown(void)
1238 unsigned long flags;
1240 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1243 local_irq_save(flags);
1245 #ifdef CONFIG_X86_32
1246 if (!enabled_via_apicbase)
1250 disable_local_APIC();
1253 local_irq_restore(flags);
1257 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1259 void __init sync_Arb_IDs(void)
1262 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1265 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1271 apic_wait_icr_idle();
1273 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1274 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1275 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1279 * An initial setup of the virtual wire mode.
1281 void __init init_bsp_APIC(void)
1286 * Don't do the setup now if we have a SMP BIOS as the
1287 * through-I/O-APIC virtual wire mode might be active.
1289 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1293 * Do not trust the local APIC being empty at bootup.
1300 value = apic_read(APIC_SPIV);
1301 value &= ~APIC_VECTOR_MASK;
1302 value |= APIC_SPIV_APIC_ENABLED;
1304 #ifdef CONFIG_X86_32
1305 /* This bit is reserved on P4/Xeon and should be cleared */
1306 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1307 (boot_cpu_data.x86 == 15))
1308 value &= ~APIC_SPIV_FOCUS_DISABLED;
1311 value |= APIC_SPIV_FOCUS_DISABLED;
1312 value |= SPURIOUS_APIC_VECTOR;
1313 apic_write(APIC_SPIV, value);
1316 * Set up the virtual wire mode.
1318 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1319 value = APIC_DM_NMI;
1320 if (!lapic_is_integrated()) /* 82489DX */
1321 value |= APIC_LVT_LEVEL_TRIGGER;
1322 if (apic_extnmi == APIC_EXTNMI_NONE)
1323 value |= APIC_LVT_MASKED;
1324 apic_write(APIC_LVT1, value);
1327 static void lapic_setup_esr(void)
1329 unsigned int oldvalue, value, maxlvt;
1331 if (!lapic_is_integrated()) {
1332 pr_info("No ESR for 82489DX.\n");
1336 if (apic->disable_esr) {
1338 * Something untraceable is creating bad interrupts on
1339 * secondary quads ... for the moment, just leave the
1340 * ESR disabled - we can't do anything useful with the
1341 * errors anyway - mbligh
1343 pr_info("Leaving ESR disabled.\n");
1347 maxlvt = lapic_get_maxlvt();
1348 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1349 apic_write(APIC_ESR, 0);
1350 oldvalue = apic_read(APIC_ESR);
1352 /* enables sending errors */
1353 value = ERROR_APIC_VECTOR;
1354 apic_write(APIC_LVTERR, value);
1357 * spec says clear errors after enabling vector.
1360 apic_write(APIC_ESR, 0);
1361 value = apic_read(APIC_ESR);
1362 if (value != oldvalue)
1363 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1364 "vector: 0x%08x after: 0x%08x\n",
1368 static void apic_pending_intr_clear(void)
1370 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1371 unsigned long long tsc = 0, ntsc;
1372 unsigned int value, queued;
1373 int i, j, acked = 0;
1375 if (boot_cpu_has(X86_FEATURE_TSC))
1378 * After a crash, we no longer service the interrupts and a pending
1379 * interrupt from previous kernel might still have ISR bit set.
1381 * Most probably by now CPU has serviced that pending interrupt and
1382 * it might not have done the ack_APIC_irq() because it thought,
1383 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1384 * does not clear the ISR bit and cpu thinks it has already serivced
1385 * the interrupt. Hence a vector might get locked. It was noticed
1386 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1390 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1391 queued |= apic_read(APIC_IRR + i*0x10);
1393 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1394 value = apic_read(APIC_ISR + i*0x10);
1395 for (j = 31; j >= 0; j--) {
1396 if (value & (1<<j)) {
1403 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1408 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1410 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1414 } while (queued && max_loops > 0);
1415 WARN_ON(max_loops <= 0);
1419 * setup_local_APIC - setup the local APIC
1421 * Used to setup local APIC while initializing BSP or bringing up APs.
1422 * Always called with preemption disabled.
1424 void setup_local_APIC(void)
1426 int cpu = smp_processor_id();
1431 disable_ioapic_support();
1436 * If this comes from kexec/kcrash the APIC might be enabled in
1437 * SPIV. Soft disable it before doing further initialization.
1439 value = apic_read(APIC_SPIV);
1440 value &= ~APIC_SPIV_APIC_ENABLED;
1441 apic_write(APIC_SPIV, value);
1443 #ifdef CONFIG_X86_32
1444 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1445 if (lapic_is_integrated() && apic->disable_esr) {
1446 apic_write(APIC_ESR, 0);
1447 apic_write(APIC_ESR, 0);
1448 apic_write(APIC_ESR, 0);
1449 apic_write(APIC_ESR, 0);
1452 perf_events_lapic_init();
1455 * Double-check whether this APIC is really registered.
1456 * This is meaningless in clustered apic mode, so we skip it.
1458 BUG_ON(!apic->apic_id_registered());
1461 * Intel recommends to set DFR, LDR and TPR before enabling
1462 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1463 * document number 292116). So here it goes...
1465 apic->init_apic_ldr();
1467 #ifdef CONFIG_X86_32
1468 if (apic->dest_logical) {
1469 int logical_apicid, ldr_apicid;
1472 * APIC LDR is initialized. If logical_apicid mapping was
1473 * initialized during get_smp_config(), make sure it matches
1476 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1477 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1478 if (logical_apicid != BAD_APICID)
1479 WARN_ON(logical_apicid != ldr_apicid);
1480 /* Always use the value from LDR. */
1481 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1486 * Set Task Priority to 'accept all'. We never change this
1489 value = apic_read(APIC_TASKPRI);
1490 value &= ~APIC_TPRI_MASK;
1491 apic_write(APIC_TASKPRI, value);
1493 apic_pending_intr_clear();
1496 * Now that we are all set up, enable the APIC
1498 value = apic_read(APIC_SPIV);
1499 value &= ~APIC_VECTOR_MASK;
1503 value |= APIC_SPIV_APIC_ENABLED;
1505 #ifdef CONFIG_X86_32
1507 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1508 * certain networking cards. If high frequency interrupts are
1509 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1510 * entry is masked/unmasked at a high rate as well then sooner or
1511 * later IOAPIC line gets 'stuck', no more interrupts are received
1512 * from the device. If focus CPU is disabled then the hang goes
1515 * [ This bug can be reproduced easily with a level-triggered
1516 * PCI Ne2000 networking cards and PII/PIII processors, dual
1520 * Actually disabling the focus CPU check just makes the hang less
1521 * frequent as it makes the interrupt distributon model be more
1522 * like LRU than MRU (the short-term load is more even across CPUs).
1526 * - enable focus processor (bit==0)
1527 * - 64bit mode always use processor focus
1528 * so no need to set it
1530 value &= ~APIC_SPIV_FOCUS_DISABLED;
1534 * Set spurious IRQ vector
1536 value |= SPURIOUS_APIC_VECTOR;
1537 apic_write(APIC_SPIV, value);
1540 * Set up LVT0, LVT1:
1542 * set up through-local-APIC on the BP's LINT0. This is not
1543 * strictly necessary in pure symmetric-IO mode, but sometimes
1544 * we delegate interrupts to the 8259A.
1547 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1549 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1550 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1551 value = APIC_DM_EXTINT;
1552 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1554 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1555 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1557 apic_write(APIC_LVT0, value);
1560 * Only the BSP sees the LINT1 NMI signal by default. This can be
1561 * modified by apic_extnmi= boot option.
1563 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1564 apic_extnmi == APIC_EXTNMI_ALL)
1565 value = APIC_DM_NMI;
1567 value = APIC_DM_NMI | APIC_LVT_MASKED;
1568 if (!lapic_is_integrated()) /* 82489DX */
1569 value |= APIC_LVT_LEVEL_TRIGGER;
1570 apic_write(APIC_LVT1, value);
1572 #ifdef CONFIG_X86_MCE_INTEL
1573 /* Recheck CMCI information after local APIC is up on CPU #0 */
1579 static void end_local_APIC_setup(void)
1583 #ifdef CONFIG_X86_32
1586 /* Disable the local apic timer */
1587 value = apic_read(APIC_LVTT);
1588 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1589 apic_write(APIC_LVTT, value);
1597 * APIC setup function for application processors. Called from smpboot.c
1599 void apic_ap_setup(void)
1602 end_local_APIC_setup();
1605 #ifdef CONFIG_X86_X2APIC
1613 static int x2apic_state;
1615 static void __x2apic_disable(void)
1619 if (!boot_cpu_has(X86_FEATURE_APIC))
1622 rdmsrl(MSR_IA32_APICBASE, msr);
1623 if (!(msr & X2APIC_ENABLE))
1625 /* Disable xapic and x2apic first and then reenable xapic mode */
1626 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1627 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1628 printk_once(KERN_INFO "x2apic disabled\n");
1631 static void __x2apic_enable(void)
1635 rdmsrl(MSR_IA32_APICBASE, msr);
1636 if (msr & X2APIC_ENABLE)
1638 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1639 printk_once(KERN_INFO "x2apic enabled\n");
1642 static int __init setup_nox2apic(char *str)
1644 if (x2apic_enabled()) {
1645 int apicid = native_apic_msr_read(APIC_ID);
1647 if (apicid >= 255) {
1648 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1652 pr_warning("x2apic already enabled.\n");
1655 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1656 x2apic_state = X2APIC_DISABLED;
1660 early_param("nox2apic", setup_nox2apic);
1662 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1663 void x2apic_setup(void)
1666 * If x2apic is not in ON state, disable it if already enabled
1669 if (x2apic_state != X2APIC_ON) {
1676 static __init void x2apic_disable(void)
1678 u32 x2apic_id, state = x2apic_state;
1681 x2apic_state = X2APIC_DISABLED;
1683 if (state != X2APIC_ON)
1686 x2apic_id = read_apic_id();
1687 if (x2apic_id >= 255)
1688 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1691 register_lapic_address(mp_lapic_addr);
1694 static __init void x2apic_enable(void)
1696 if (x2apic_state != X2APIC_OFF)
1700 x2apic_state = X2APIC_ON;
1704 static __init void try_to_enable_x2apic(int remap_mode)
1706 if (x2apic_state == X2APIC_DISABLED)
1709 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1710 /* IR is required if there is APIC ID > 255 even when running
1713 if (max_physical_apicid > 255 ||
1714 !x86_init.hyper.x2apic_available()) {
1715 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1721 * without IR all CPUs can be addressed by IOAPIC/MSI
1722 * only in physical mode
1729 void __init check_x2apic(void)
1731 if (x2apic_enabled()) {
1732 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1734 x2apic_state = X2APIC_ON;
1735 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1736 x2apic_state = X2APIC_DISABLED;
1739 #else /* CONFIG_X86_X2APIC */
1740 static int __init validate_x2apic(void)
1742 if (!apic_is_x2apic_enabled())
1745 * Checkme: Can we simply turn off x2apic here instead of panic?
1747 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1749 early_initcall(validate_x2apic);
1751 static inline void try_to_enable_x2apic(int remap_mode) { }
1752 static inline void __x2apic_enable(void) { }
1753 #endif /* !CONFIG_X86_X2APIC */
1755 void __init enable_IR_x2apic(void)
1757 unsigned long flags;
1760 if (skip_ioapic_setup) {
1761 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1765 ir_stat = irq_remapping_prepare();
1766 if (ir_stat < 0 && !x2apic_supported())
1769 ret = save_ioapic_entries();
1771 pr_info("Saving IO-APIC state failed: %d\n", ret);
1775 local_irq_save(flags);
1776 legacy_pic->mask_all();
1777 mask_ioapic_entries();
1779 /* If irq_remapping_prepare() succeeded, try to enable it */
1781 ir_stat = irq_remapping_enable();
1782 /* ir_stat contains the remap mode or an error code */
1783 try_to_enable_x2apic(ir_stat);
1786 restore_ioapic_entries();
1787 legacy_pic->restore_mask();
1788 local_irq_restore(flags);
1791 #ifdef CONFIG_X86_64
1793 * Detect and enable local APICs on non-SMP boards.
1794 * Original code written by Keir Fraser.
1795 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1796 * not correctly set up (usually the APIC timer won't work etc.)
1798 static int __init detect_init_APIC(void)
1800 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1801 pr_info("No local APIC present\n");
1805 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1810 static int __init apic_verify(void)
1815 * The APIC feature bit should now be enabled
1818 features = cpuid_edx(1);
1819 if (!(features & (1 << X86_FEATURE_APIC))) {
1820 pr_warning("Could not enable APIC!\n");
1823 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1824 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1826 /* The BIOS may have set up the APIC at some other address */
1827 if (boot_cpu_data.x86 >= 6) {
1828 rdmsr(MSR_IA32_APICBASE, l, h);
1829 if (l & MSR_IA32_APICBASE_ENABLE)
1830 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1833 pr_info("Found and enabled local APIC!\n");
1837 int __init apic_force_enable(unsigned long addr)
1845 * Some BIOSes disable the local APIC in the APIC_BASE
1846 * MSR. This can only be done in software for Intel P6 or later
1847 * and AMD K7 (Model > 1) or later.
1849 if (boot_cpu_data.x86 >= 6) {
1850 rdmsr(MSR_IA32_APICBASE, l, h);
1851 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1852 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1853 l &= ~MSR_IA32_APICBASE_BASE;
1854 l |= MSR_IA32_APICBASE_ENABLE | addr;
1855 wrmsr(MSR_IA32_APICBASE, l, h);
1856 enabled_via_apicbase = 1;
1859 return apic_verify();
1863 * Detect and initialize APIC
1865 static int __init detect_init_APIC(void)
1867 /* Disabled by kernel option? */
1871 switch (boot_cpu_data.x86_vendor) {
1872 case X86_VENDOR_AMD:
1873 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1874 (boot_cpu_data.x86 >= 15))
1877 case X86_VENDOR_INTEL:
1878 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1879 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1886 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1888 * Over-ride BIOS and try to enable the local APIC only if
1889 * "lapic" specified.
1891 if (!force_enable_local_apic) {
1892 pr_info("Local APIC disabled by BIOS -- "
1893 "you can enable it with \"lapic\"\n");
1896 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1908 pr_info("No local APIC present or hardware disabled\n");
1914 * init_apic_mappings - initialize APIC mappings
1916 void __init init_apic_mappings(void)
1918 unsigned int new_apicid;
1920 if (apic_validate_deadline_timer())
1921 pr_info("TSC deadline timer available\n");
1924 boot_cpu_physical_apicid = read_apic_id();
1928 /* If no local APIC can be found return early */
1929 if (!smp_found_config && detect_init_APIC()) {
1930 /* lets NOP'ify apic operations */
1931 pr_info("APIC: disable apic facility\n");
1934 apic_phys = mp_lapic_addr;
1937 * If the system has ACPI MADT tables or MP info, the LAPIC
1938 * address is already registered.
1940 if (!acpi_lapic && !smp_found_config)
1941 register_lapic_address(apic_phys);
1945 * Fetch the APIC ID of the BSP in case we have a
1946 * default configuration (or the MP table is broken).
1948 new_apicid = read_apic_id();
1949 if (boot_cpu_physical_apicid != new_apicid) {
1950 boot_cpu_physical_apicid = new_apicid;
1952 * yeah -- we lie about apic_version
1953 * in case if apic was disabled via boot option
1954 * but it's not a problem for SMP compiled kernel
1955 * since smp_sanity_check is prepared for such a case
1956 * and disable smp mode
1958 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1962 void __init register_lapic_address(unsigned long address)
1964 mp_lapic_addr = address;
1967 set_fixmap_nocache(FIX_APIC_BASE, address);
1968 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1969 APIC_BASE, address);
1971 if (boot_cpu_physical_apicid == -1U) {
1972 boot_cpu_physical_apicid = read_apic_id();
1973 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1978 * Local APIC interrupts
1982 * This interrupt should _never_ happen with our APIC/SMP architecture
1984 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1986 u8 vector = ~regs->orig_ax;
1990 trace_spurious_apic_entry(vector);
1993 * Check if this really is a spurious interrupt and ACK it
1994 * if it is a vectored one. Just in case...
1995 * Spurious interrupts should not be ACKed.
1997 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1998 if (v & (1 << (vector & 0x1f)))
2001 inc_irq_stat(irq_spurious_count);
2003 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
2004 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
2005 "should never happen.\n", vector, smp_processor_id());
2007 trace_spurious_apic_exit(vector);
2012 * This interrupt should never happen with our APIC/SMP architecture
2014 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2016 static const char * const error_interrupt_reason[] = {
2017 "Send CS error", /* APIC Error Bit 0 */
2018 "Receive CS error", /* APIC Error Bit 1 */
2019 "Send accept error", /* APIC Error Bit 2 */
2020 "Receive accept error", /* APIC Error Bit 3 */
2021 "Redirectable IPI", /* APIC Error Bit 4 */
2022 "Send illegal vector", /* APIC Error Bit 5 */
2023 "Received illegal vector", /* APIC Error Bit 6 */
2024 "Illegal register address", /* APIC Error Bit 7 */
2029 trace_error_apic_entry(ERROR_APIC_VECTOR);
2031 /* First tickle the hardware, only then report what went on. -- REW */
2032 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2033 apic_write(APIC_ESR, 0);
2034 v = apic_read(APIC_ESR);
2036 atomic_inc(&irq_err_count);
2038 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2039 smp_processor_id(), v);
2044 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2049 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2051 trace_error_apic_exit(ERROR_APIC_VECTOR);
2056 * connect_bsp_APIC - attach the APIC to the interrupt system
2058 static void __init connect_bsp_APIC(void)
2060 #ifdef CONFIG_X86_32
2063 * Do not trust the local APIC being empty at bootup.
2067 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2068 * local APIC to INT and NMI lines.
2070 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2071 "enabling APIC mode.\n");
2078 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2079 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2081 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2084 void disconnect_bsp_APIC(int virt_wire_setup)
2088 #ifdef CONFIG_X86_32
2091 * Put the board back into PIC mode (has an effect only on
2092 * certain older boards). Note that APIC interrupts, including
2093 * IPIs, won't work beyond this point! The only exception are
2096 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2097 "entering PIC mode.\n");
2103 /* Go back to Virtual Wire compatibility mode */
2105 /* For the spurious interrupt use vector F, and enable it */
2106 value = apic_read(APIC_SPIV);
2107 value &= ~APIC_VECTOR_MASK;
2108 value |= APIC_SPIV_APIC_ENABLED;
2110 apic_write(APIC_SPIV, value);
2112 if (!virt_wire_setup) {
2114 * For LVT0 make it edge triggered, active high,
2115 * external and enabled
2117 value = apic_read(APIC_LVT0);
2118 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2119 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2120 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2121 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2122 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2123 apic_write(APIC_LVT0, value);
2126 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2130 * For LVT1 make it edge triggered, active high,
2133 value = apic_read(APIC_LVT1);
2134 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2135 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2136 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2137 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2138 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2139 apic_write(APIC_LVT1, value);
2143 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2144 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2145 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2146 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2148 * NOTE: Reserve 0 for BSP.
2150 static int nr_logical_cpuids = 1;
2153 * Used to store mapping between logical CPU IDs and APIC IDs.
2155 static int cpuid_to_apicid[] = {
2156 [0 ... NR_CPUS - 1] = -1,
2161 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2162 * @id: APIC ID to check
2164 bool apic_id_is_primary_thread(unsigned int apicid)
2168 if (smp_num_siblings == 1)
2170 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2171 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2172 return !(apicid & mask);
2177 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2178 * and cpuid_to_apicid[] synchronized.
2180 static int allocate_logical_cpuid(int apicid)
2185 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2186 * check if the kernel has allocated a cpuid for it.
2188 for (i = 0; i < nr_logical_cpuids; i++) {
2189 if (cpuid_to_apicid[i] == apicid)
2193 /* Allocate a new cpuid. */
2194 if (nr_logical_cpuids >= nr_cpu_ids) {
2195 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2196 "Processor %d/0x%x and the rest are ignored.\n",
2197 nr_cpu_ids, nr_logical_cpuids, apicid);
2201 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2202 return nr_logical_cpuids++;
2205 int generic_processor_info(int apicid, int version)
2207 int cpu, max = nr_cpu_ids;
2208 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2209 phys_cpu_present_map);
2212 * boot_cpu_physical_apicid is designed to have the apicid
2213 * returned by read_apic_id(), i.e, the apicid of the
2214 * currently booting-up processor. However, on some platforms,
2215 * it is temporarily modified by the apicid reported as BSP
2216 * through MP table. Concretely:
2218 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2219 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2221 * This function is executed with the modified
2222 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2223 * parameter doesn't work to disable APs on kdump 2nd kernel.
2225 * Since fixing handling of boot_cpu_physical_apicid requires
2226 * another discussion and tests on each platform, we leave it
2227 * for now and here we use read_apic_id() directly in this
2228 * function, generic_processor_info().
2230 if (disabled_cpu_apicid != BAD_APICID &&
2231 disabled_cpu_apicid != read_apic_id() &&
2232 disabled_cpu_apicid == apicid) {
2233 int thiscpu = num_processors + disabled_cpus;
2235 pr_warning("APIC: Disabling requested cpu."
2236 " Processor %d/0x%x ignored.\n",
2244 * If boot cpu has not been detected yet, then only allow upto
2245 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2247 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2248 apicid != boot_cpu_physical_apicid) {
2249 int thiscpu = max + disabled_cpus - 1;
2252 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2253 " reached. Keeping one slot for boot cpu."
2254 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2260 if (num_processors >= nr_cpu_ids) {
2261 int thiscpu = max + disabled_cpus;
2263 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2264 "reached. Processor %d/0x%x ignored.\n",
2265 max, thiscpu, apicid);
2271 if (apicid == boot_cpu_physical_apicid) {
2273 * x86_bios_cpu_apicid is required to have processors listed
2274 * in same order as logical cpu numbers. Hence the first
2275 * entry is BSP, and so on.
2276 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2281 /* Logical cpuid 0 is reserved for BSP. */
2282 cpuid_to_apicid[0] = apicid;
2284 cpu = allocate_logical_cpuid(apicid);
2294 if (version == 0x0) {
2295 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2300 if (version != boot_cpu_apic_version) {
2301 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2302 boot_cpu_apic_version, cpu, version);
2305 if (apicid > max_physical_apicid)
2306 max_physical_apicid = apicid;
2308 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2309 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2310 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2312 #ifdef CONFIG_X86_32
2313 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2314 apic->x86_32_early_logical_apicid(cpu);
2316 set_cpu_possible(cpu, true);
2317 physid_set(apicid, phys_cpu_present_map);
2318 set_cpu_present(cpu, true);
2324 int hard_smp_processor_id(void)
2326 return read_apic_id();
2329 void default_init_apic_ldr(void)
2333 apic_write(APIC_DFR, APIC_DFR_VALUE);
2334 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2335 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2336 apic_write(APIC_LDR, val);
2339 int default_cpu_mask_to_apicid(const struct cpumask *mask,
2340 struct irq_data *irqdata,
2341 unsigned int *apicid)
2343 unsigned int cpu = cpumask_first(mask);
2345 if (cpu >= nr_cpu_ids)
2347 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2348 irq_data_update_effective_affinity(irqdata, cpumask_of(cpu));
2352 int flat_cpu_mask_to_apicid(const struct cpumask *mask,
2353 struct irq_data *irqdata,
2354 unsigned int *apicid)
2357 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
2358 unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS;
2362 *apicid = (unsigned int)cpu_mask;
2363 cpumask_bits(effmsk)[0] = cpu_mask;
2368 * Override the generic EOI implementation with an optimized version.
2369 * Only called during early boot when only one CPU is active and with
2370 * interrupts disabled, so we know this does not race with actual APIC driver
2373 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2377 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2378 /* Should happen once for each apic */
2379 WARN_ON((*drv)->eoi_write == eoi_write);
2380 (*drv)->native_eoi_write = (*drv)->eoi_write;
2381 (*drv)->eoi_write = eoi_write;
2385 static void __init apic_bsp_up_setup(void)
2387 #ifdef CONFIG_X86_64
2388 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2391 * Hack: In case of kdump, after a crash, kernel might be booting
2392 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2393 * might be zero if read from MP tables. Get it from LAPIC.
2395 # ifdef CONFIG_CRASH_DUMP
2396 boot_cpu_physical_apicid = read_apic_id();
2399 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2403 * apic_bsp_setup - Setup function for local apic and io-apic
2404 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2407 * apic_id of BSP APIC
2409 int __init apic_bsp_setup(bool upmode)
2415 apic_bsp_up_setup();
2419 id = apic_read(APIC_LDR);
2421 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2424 end_local_APIC_setup();
2425 irq_remap_enable_fault_handling();
2427 /* Setup local timer */
2428 x86_init.timers.setup_percpu_clockev();
2433 * This initializes the IO-APIC and APIC hardware if this is
2436 int __init APIC_init_uniprocessor(void)
2439 pr_info("Apic disabled\n");
2442 #ifdef CONFIG_X86_64
2443 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2445 pr_info("Apic disabled by BIOS\n");
2449 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2453 * Complain if the BIOS pretends there is one.
2455 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2456 APIC_INTEGRATED(boot_cpu_apic_version)) {
2457 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2458 boot_cpu_physical_apicid);
2463 if (!smp_found_config)
2464 disable_ioapic_support();
2466 default_setup_apic_routing();
2467 apic_bsp_setup(true);
2471 #ifdef CONFIG_UP_LATE_INIT
2472 void __init up_late_init(void)
2474 APIC_init_uniprocessor();
2485 * 'active' is true if the local APIC was enabled by us and
2486 * not the BIOS; this signifies that we are also responsible
2487 * for disabling it before entering apm/acpi suspend
2490 /* r/w apic fields */
2491 unsigned int apic_id;
2492 unsigned int apic_taskpri;
2493 unsigned int apic_ldr;
2494 unsigned int apic_dfr;
2495 unsigned int apic_spiv;
2496 unsigned int apic_lvtt;
2497 unsigned int apic_lvtpc;
2498 unsigned int apic_lvt0;
2499 unsigned int apic_lvt1;
2500 unsigned int apic_lvterr;
2501 unsigned int apic_tmict;
2502 unsigned int apic_tdcr;
2503 unsigned int apic_thmr;
2504 unsigned int apic_cmci;
2507 static int lapic_suspend(void)
2509 unsigned long flags;
2512 if (!apic_pm_state.active)
2515 maxlvt = lapic_get_maxlvt();
2517 apic_pm_state.apic_id = apic_read(APIC_ID);
2518 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2519 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2520 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2521 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2522 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2524 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2525 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2526 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2527 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2528 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2529 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2530 #ifdef CONFIG_X86_THERMAL_VECTOR
2532 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2534 #ifdef CONFIG_X86_MCE_INTEL
2536 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2539 local_irq_save(flags);
2540 disable_local_APIC();
2542 irq_remapping_disable();
2544 local_irq_restore(flags);
2548 static void lapic_resume(void)
2551 unsigned long flags;
2554 if (!apic_pm_state.active)
2557 local_irq_save(flags);
2560 * IO-APIC and PIC have their own resume routines.
2561 * We just mask them here to make sure the interrupt
2562 * subsystem is completely quiet while we enable x2apic
2563 * and interrupt-remapping.
2565 mask_ioapic_entries();
2566 legacy_pic->mask_all();
2572 * Make sure the APICBASE points to the right address
2574 * FIXME! This will be wrong if we ever support suspend on
2575 * SMP! We'll need to do this as part of the CPU restore!
2577 if (boot_cpu_data.x86 >= 6) {
2578 rdmsr(MSR_IA32_APICBASE, l, h);
2579 l &= ~MSR_IA32_APICBASE_BASE;
2580 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2581 wrmsr(MSR_IA32_APICBASE, l, h);
2585 maxlvt = lapic_get_maxlvt();
2586 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2587 apic_write(APIC_ID, apic_pm_state.apic_id);
2588 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2589 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2590 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2591 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2592 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2593 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2594 #ifdef CONFIG_X86_THERMAL_VECTOR
2596 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2598 #ifdef CONFIG_X86_MCE_INTEL
2600 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2603 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2604 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2605 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2606 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2607 apic_write(APIC_ESR, 0);
2608 apic_read(APIC_ESR);
2609 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2610 apic_write(APIC_ESR, 0);
2611 apic_read(APIC_ESR);
2613 irq_remapping_reenable(x2apic_mode);
2615 local_irq_restore(flags);
2619 * This device has no shutdown method - fully functioning local APICs
2620 * are needed on every CPU up until machine_halt/restart/poweroff.
2623 static struct syscore_ops lapic_syscore_ops = {
2624 .resume = lapic_resume,
2625 .suspend = lapic_suspend,
2628 static void apic_pm_activate(void)
2630 apic_pm_state.active = 1;
2633 static int __init init_lapic_sysfs(void)
2635 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2636 if (boot_cpu_has(X86_FEATURE_APIC))
2637 register_syscore_ops(&lapic_syscore_ops);
2642 /* local apic needs to resume before other devices access its registers. */
2643 core_initcall(init_lapic_sysfs);
2645 #else /* CONFIG_PM */
2647 static void apic_pm_activate(void) { }
2649 #endif /* CONFIG_PM */
2651 #ifdef CONFIG_X86_64
2653 static int multi_checked;
2656 static int set_multi(const struct dmi_system_id *d)
2660 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2665 static const struct dmi_system_id multi_dmi_table[] = {
2667 .callback = set_multi,
2668 .ident = "IBM System Summit2",
2670 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2671 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2677 static void dmi_check_multi(void)
2682 dmi_check_system(multi_dmi_table);
2687 * apic_is_clustered_box() -- Check if we can expect good TSC
2689 * Thus far, the major user of this is IBM's Summit2 series:
2690 * Clustered boxes may have unsynced TSC problems if they are
2692 * Use DMI to check them
2694 int apic_is_clustered_box(void)
2702 * APIC command line parameters
2704 static int __init setup_disableapic(char *arg)
2707 setup_clear_cpu_cap(X86_FEATURE_APIC);
2710 early_param("disableapic", setup_disableapic);
2712 /* same as disableapic, for compatibility */
2713 static int __init setup_nolapic(char *arg)
2715 return setup_disableapic(arg);
2717 early_param("nolapic", setup_nolapic);
2719 static int __init parse_lapic_timer_c2_ok(char *arg)
2721 local_apic_timer_c2_ok = 1;
2724 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2726 static int __init parse_disable_apic_timer(char *arg)
2728 disable_apic_timer = 1;
2731 early_param("noapictimer", parse_disable_apic_timer);
2733 static int __init parse_nolapic_timer(char *arg)
2735 disable_apic_timer = 1;
2738 early_param("nolapic_timer", parse_nolapic_timer);
2740 static int __init apic_set_verbosity(char *arg)
2743 #ifdef CONFIG_X86_64
2744 skip_ioapic_setup = 0;
2750 if (strcmp("debug", arg) == 0)
2751 apic_verbosity = APIC_DEBUG;
2752 else if (strcmp("verbose", arg) == 0)
2753 apic_verbosity = APIC_VERBOSE;
2755 pr_warning("APIC Verbosity level %s not recognised"
2756 " use apic=verbose or apic=debug\n", arg);
2762 early_param("apic", apic_set_verbosity);
2764 static int __init lapic_insert_resource(void)
2769 /* Put local APIC into the resource map. */
2770 lapic_resource.start = apic_phys;
2771 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2772 insert_resource(&iomem_resource, &lapic_resource);
2778 * need call insert after e820__reserve_resources()
2779 * that is using request_resource
2781 late_initcall(lapic_insert_resource);
2783 static int __init apic_set_disabled_cpu_apicid(char *arg)
2785 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2790 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2792 static int __init apic_set_extnmi(char *arg)
2797 if (!strncmp("all", arg, 3))
2798 apic_extnmi = APIC_EXTNMI_ALL;
2799 else if (!strncmp("none", arg, 4))
2800 apic_extnmi = APIC_EXTNMI_NONE;
2801 else if (!strncmp("bsp", arg, 3))
2802 apic_extnmi = APIC_EXTNMI_BSP;
2804 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2810 early_param("apic_extnmi", apic_set_extnmi);