2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
37 #include <linux/irq.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <asm/pgalloc.h>
44 #include <linux/atomic.h>
45 #include <asm/barrier.h>
46 #include <asm/mpspec.h>
47 #include <asm/i8259.h>
48 #include <asm/proto.h>
50 #include <asm/io_apic.h>
59 #include <asm/hypervisor.h>
60 #include <asm/irq_regs.h>
62 unsigned int num_processors;
64 unsigned disabled_cpus;
66 /* Processor that is doing the boot up */
67 unsigned int boot_cpu_physical_apicid = -1U;
68 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
70 u8 boot_cpu_apic_version;
73 * The highest APIC ID seen during enumeration.
75 static unsigned int max_physical_apicid;
78 * Bitmask of physically existing CPUs:
80 physid_mask_t phys_cpu_present_map;
83 * Processor to be disabled specified by kernel parameter
84 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
85 * avoid undefined behaviour caused by sending INIT from AP to BSP.
87 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
90 * This variable controls which CPUs receive external NMIs. By default,
91 * external NMIs are delivered only to the BSP.
93 static int apic_extnmi = APIC_EXTNMI_BSP;
96 * Map cpu index to physical APIC ID
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
108 * On x86_32, the mapping between cpu and logical apicid may vary
109 * depending on apic in use. The following early percpu variable is
110 * used for the mapping. This is where the behaviors of x86_64 and 32
111 * actually diverge. Let's keep it ugly for now.
113 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase;
119 * Handle interrupt mode configuration register (IMCR).
120 * This register controls whether the interrupt signals
121 * that reach the BSP come from the master PIC or from the
122 * local APIC. Before entering Symmetric I/O Mode, either
123 * the BIOS or the operating system must switch out of
124 * PIC Mode by changing the IMCR.
126 static inline void imcr_pic_to_apic(void)
128 /* select IMCR register */
130 /* NMI and 8259 INTR go through APIC */
134 static inline void imcr_apic_to_pic(void)
136 /* select IMCR register */
138 /* NMI and 8259 INTR go directly to BSP */
144 * Knob to control our willingness to enable the local APIC.
148 static int force_enable_local_apic __initdata;
151 * APIC command line parameters
153 static int __init parse_lapic(char *arg)
155 if (IS_ENABLED(CONFIG_X86_32) && !arg)
156 force_enable_local_apic = 1;
157 else if (arg && !strncmp(arg, "notscdeadline", 13))
158 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
161 early_param("lapic", parse_lapic);
164 static int apic_calibrate_pmtmr __initdata;
165 static __init int setup_apicpmtimer(char *s)
167 apic_calibrate_pmtmr = 1;
171 __setup("apicpmtimer", setup_apicpmtimer);
174 unsigned long mp_lapic_addr;
176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
177 static int disable_apic_timer __initdata;
178 /* Local APIC timer works in C2 */
179 int local_apic_timer_c2_ok;
180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
182 int first_system_vector = FIRST_SYSTEM_VECTOR;
185 * Debug level, exported for io_apic.c
191 /* Have we found an MP table */
192 int smp_found_config;
194 static struct resource lapic_resource = {
195 .name = "Local APIC",
196 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
199 unsigned int lapic_timer_frequency = 0;
201 static void apic_pm_activate(void);
203 static unsigned long apic_phys;
206 * Get the LAPIC version
208 static inline int lapic_get_version(void)
210 return GET_APIC_VERSION(apic_read(APIC_LVR));
214 * Check, if the APIC is integrated or a separate chip
216 static inline int lapic_is_integrated(void)
221 return APIC_INTEGRATED(lapic_get_version());
226 * Check, whether this is a modern or a first generation APIC
228 static int modern_apic(void)
230 /* AMD systems use old APIC versions, so check the CPU */
231 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
232 boot_cpu_data.x86 >= 0xf)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 static void __init apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
253 u32 native_safe_apic_wait_icr_idle(void)
260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
263 inc_irq_stat(icr_read_retry_count);
265 } while (timeout++ < 1000);
270 void native_apic_icr_write(u32 low, u32 id)
274 local_irq_save(flags);
275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
276 apic_write(APIC_ICR, low);
277 local_irq_restore(flags);
280 u64 native_apic_icr_read(void)
284 icr2 = apic_read(APIC_ICR2);
285 icr1 = apic_read(APIC_ICR);
287 return icr1 | ((u64)icr2 << 32);
292 * get_physical_broadcast - Get number of physical broadcast IDs
294 int get_physical_broadcast(void)
296 return modern_apic() ? 0xff : 0xf;
301 * lapic_get_maxlvt - get the maximum number of local vector table entries
303 int lapic_get_maxlvt(void)
307 v = apic_read(APIC_LVR);
309 * - we always have APIC integrated on 64bit mode
310 * - 82489DXs do not report # of LVT entries
312 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
320 #define APIC_DIVISOR 16
321 #define TSC_DIVISOR 8
324 * This function sets up the local APIC timer, with a timeout of
325 * 'clocks' APIC bus clock. During calibration we actually call
326 * this function twice on the boot CPU, once with a bogus timeout
327 * value, second time for real. The other (noncalibrating) CPUs
328 * call this function only once, with the real, calibrated value.
330 * We do reads before writes even if unnecessary, to get around the
331 * P5 APIC double write bug.
333 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
335 unsigned int lvtt_value, tmp_value;
337 lvtt_value = LOCAL_TIMER_VECTOR;
339 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
340 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
341 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
343 if (!lapic_is_integrated())
344 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
347 lvtt_value |= APIC_LVT_MASKED;
349 apic_write(APIC_LVTT, lvtt_value);
351 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
353 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
354 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
355 * According to Intel, MFENCE can do the serialization here.
357 asm volatile("mfence" : : : "memory");
359 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
366 tmp_value = apic_read(APIC_TDCR);
367 apic_write(APIC_TDCR,
368 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
372 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
376 * Setup extended LVT, AMD specific
378 * Software should use the LVT offsets the BIOS provides. The offsets
379 * are determined by the subsystems using it like those for MCE
380 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
381 * are supported. Beginning with family 10h at least 4 offsets are
384 * Since the offsets must be consistent for all cores, we keep track
385 * of the LVT offsets in software and reserve the offset for the same
386 * vector also to be used on other cores. An offset is freed by
387 * setting the entry to APIC_EILVT_MASKED.
389 * If the BIOS is right, there should be no conflicts. Otherwise a
390 * "[Firmware Bug]: ..." error message is generated. However, if
391 * software does not properly determines the offsets, it is not
392 * necessarily a BIOS bug.
395 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
397 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
399 return (old & APIC_EILVT_MASKED)
400 || (new == APIC_EILVT_MASKED)
401 || ((new & ~APIC_EILVT_MASKED) == old);
404 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
406 unsigned int rsvd, vector;
408 if (offset >= APIC_EILVT_NR_MAX)
411 rsvd = atomic_read(&eilvt_offsets[offset]);
413 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
414 if (vector && !eilvt_entry_is_changeable(vector, new))
415 /* may not change if vectors are different */
417 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
418 } while (rsvd != new);
420 rsvd &= ~APIC_EILVT_MASKED;
421 if (rsvd && rsvd != vector)
422 pr_info("LVT offset %d assigned for vector 0x%02x\n",
429 * If mask=1, the LVT entry does not generate interrupts while mask=0
430 * enables the vector. See also the BKDGs. Must be called with
431 * preemption disabled.
434 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
436 unsigned long reg = APIC_EILVTn(offset);
437 unsigned int new, old, reserved;
439 new = (mask << 16) | (msg_type << 8) | vector;
440 old = apic_read(reg);
441 reserved = reserve_eilvt_offset(offset, new);
443 if (reserved != new) {
444 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
445 "vector 0x%x, but the register is already in use for "
446 "vector 0x%x on another cpu\n",
447 smp_processor_id(), reg, offset, new, reserved);
451 if (!eilvt_entry_is_changeable(old, new)) {
452 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
453 "vector 0x%x, but the register is already in use for "
454 "vector 0x%x on this cpu\n",
455 smp_processor_id(), reg, offset, new, old);
459 apic_write(reg, new);
463 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
466 * Program the next event, relative to now
468 static int lapic_next_event(unsigned long delta,
469 struct clock_event_device *evt)
471 apic_write(APIC_TMICT, delta);
475 static int lapic_next_deadline(unsigned long delta,
476 struct clock_event_device *evt)
480 /* This MSR is special and need a special fence: */
484 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
488 static int lapic_timer_shutdown(struct clock_event_device *evt)
492 /* Lapic used as dummy for broadcast ? */
493 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
496 v = apic_read(APIC_LVTT);
497 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
498 apic_write(APIC_LVTT, v);
499 apic_write(APIC_TMICT, 0);
504 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
506 /* Lapic used as dummy for broadcast ? */
507 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
510 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
514 static int lapic_timer_set_periodic(struct clock_event_device *evt)
516 return lapic_timer_set_periodic_oneshot(evt, false);
519 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
521 return lapic_timer_set_periodic_oneshot(evt, true);
525 * Local APIC timer broadcast function
527 static void lapic_timer_broadcast(const struct cpumask *mask)
530 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
536 * The local apic timer can be used for any function which is CPU local.
538 static struct clock_event_device lapic_clockevent = {
540 .features = CLOCK_EVT_FEAT_PERIODIC |
541 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
542 | CLOCK_EVT_FEAT_DUMMY,
544 .set_state_shutdown = lapic_timer_shutdown,
545 .set_state_periodic = lapic_timer_set_periodic,
546 .set_state_oneshot = lapic_timer_set_oneshot,
547 .set_next_event = lapic_next_event,
548 .broadcast = lapic_timer_broadcast,
552 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
555 * Setup the local APIC timer for this CPU. Copy the initialized values
556 * of the boot CPU and register the clock event in the framework.
558 static void setup_APIC_timer(void)
560 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
562 if (this_cpu_has(X86_FEATURE_ARAT)) {
563 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
564 /* Make LAPIC timer preferrable over percpu HPET */
565 lapic_clockevent.rating = 150;
568 memcpy(levt, &lapic_clockevent, sizeof(*levt));
569 levt->cpumask = cpumask_of(smp_processor_id());
571 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
572 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
573 CLOCK_EVT_FEAT_DUMMY);
574 levt->set_next_event = lapic_next_deadline;
575 clockevents_config_and_register(levt,
576 tsc_khz * (1000 / TSC_DIVISOR),
579 clockevents_register_device(levt);
583 * Install the updated TSC frequency from recalibration at the TSC
584 * deadline clockevent devices.
586 static void __lapic_update_tsc_freq(void *info)
588 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
590 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
593 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
596 void lapic_update_tsc_freq(void)
599 * The clockevent device's ->mult and ->shift can both be
600 * changed. In order to avoid races, schedule the frequency
601 * update code on each CPU.
603 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
607 * In this functions we calibrate APIC bus clocks to the external timer.
609 * We want to do the calibration only once since we want to have local timer
610 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
613 * This was previously done by reading the PIT/HPET and waiting for a wrap
614 * around to find out, that a tick has elapsed. I have a box, where the PIT
615 * readout is broken, so it never gets out of the wait loop again. This was
616 * also reported by others.
618 * Monitoring the jiffies value is inaccurate and the clockevents
619 * infrastructure allows us to do a simple substitution of the interrupt
622 * The calibration routine also uses the pm_timer when possible, as the PIT
623 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
624 * back to normal later in the boot process).
627 #define LAPIC_CAL_LOOPS (HZ/10)
629 static __initdata int lapic_cal_loops = -1;
630 static __initdata long lapic_cal_t1, lapic_cal_t2;
631 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
632 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
633 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
636 * Temporary interrupt handler and polled calibration function.
638 static void __init lapic_cal_handler(struct clock_event_device *dev)
640 unsigned long long tsc = 0;
641 long tapic = apic_read(APIC_TMCCT);
642 unsigned long pm = acpi_pm_read_early();
644 if (boot_cpu_has(X86_FEATURE_TSC))
647 switch (lapic_cal_loops++) {
649 lapic_cal_t1 = tapic;
650 lapic_cal_tsc1 = tsc;
652 lapic_cal_j1 = jiffies;
655 case LAPIC_CAL_LOOPS:
656 lapic_cal_t2 = tapic;
657 lapic_cal_tsc2 = tsc;
658 if (pm < lapic_cal_pm1)
659 pm += ACPI_PM_OVRRUN;
661 lapic_cal_j2 = jiffies;
667 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
669 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
670 const long pm_thresh = pm_100ms / 100;
674 #ifndef CONFIG_X86_PM_TIMER
678 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
680 /* Check, if the PM timer is available */
684 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
686 if (deltapm > (pm_100ms - pm_thresh) &&
687 deltapm < (pm_100ms + pm_thresh)) {
688 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
692 res = (((u64)deltapm) * mult) >> 22;
693 do_div(res, 1000000);
694 pr_warning("APIC calibration not consistent "
695 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
697 /* Correct the lapic counter value */
698 res = (((u64)(*delta)) * pm_100ms);
699 do_div(res, deltapm);
700 pr_info("APIC delta adjusted to PM-Timer: "
701 "%lu (%ld)\n", (unsigned long)res, *delta);
704 /* Correct the tsc counter value */
705 if (boot_cpu_has(X86_FEATURE_TSC)) {
706 res = (((u64)(*deltatsc)) * pm_100ms);
707 do_div(res, deltapm);
708 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
709 "PM-Timer: %lu (%ld)\n",
710 (unsigned long)res, *deltatsc);
711 *deltatsc = (long)res;
717 static int __init calibrate_APIC_clock(void)
719 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
720 u64 tsc_perj = 0, tsc_start = 0;
721 unsigned long jif_start;
722 unsigned long deltaj;
723 long delta, deltatsc;
724 int pm_referenced = 0;
727 * check if lapic timer has already been calibrated by platform
728 * specific routine, such as tsc calibration code. if so, we just fill
729 * in the clockevent structure and return.
732 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
734 } else if (lapic_timer_frequency) {
735 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
736 lapic_timer_frequency);
737 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
738 TICK_NSEC, lapic_clockevent.shift);
739 lapic_clockevent.max_delta_ns =
740 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
741 lapic_clockevent.min_delta_ns =
742 clockevent_delta2ns(0xF, &lapic_clockevent);
743 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
747 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
748 "calibrating APIC timer ...\n");
751 * There are platforms w/o global clockevent devices. Instead of
752 * making the calibration conditional on that, use a polling based
753 * approach everywhere.
758 * Setup the APIC counter to maximum. There is no way the lapic
759 * can underflow in the 100ms detection time frame
761 __setup_APIC_LVTT(0xffffffff, 0, 0);
764 * Methods to terminate the calibration loop:
765 * 1) Global clockevent if available (jiffies)
766 * 2) TSC if available and frequency is known
768 jif_start = READ_ONCE(jiffies);
772 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
776 * Enable interrupts so the tick can fire, if a global
777 * clockevent device is available
781 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
782 /* Wait for a tick to elapse */
785 u64 tsc_now = rdtsc();
786 if ((tsc_now - tsc_start) >= tsc_perj) {
787 tsc_start += tsc_perj;
791 unsigned long jif_now = READ_ONCE(jiffies);
793 if (time_after(jif_now, jif_start)) {
801 /* Invoke the calibration routine */
803 lapic_cal_handler(NULL);
809 /* Build delta t1-t2 as apic timer counts down */
810 delta = lapic_cal_t1 - lapic_cal_t2;
811 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
813 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
815 /* we trust the PM based calibration if possible */
816 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
819 /* Calculate the scaled math multiplication factor */
820 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
821 lapic_clockevent.shift);
822 lapic_clockevent.max_delta_ns =
823 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
824 lapic_clockevent.min_delta_ns =
825 clockevent_delta2ns(0xF, &lapic_clockevent);
827 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
829 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
830 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
831 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
832 lapic_timer_frequency);
834 if (boot_cpu_has(X86_FEATURE_TSC)) {
835 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
837 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
838 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
841 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
843 lapic_timer_frequency / (1000000 / HZ),
844 lapic_timer_frequency % (1000000 / HZ));
847 * Do a sanity check on the APIC calibration result
849 if (lapic_timer_frequency < (1000000 / HZ)) {
851 pr_warning("APIC frequency too slow, disabling apic timer\n");
855 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
858 * PM timer calibration failed or not turned on so lets try APIC
859 * timer based calibration, if a global clockevent device is
862 if (!pm_referenced && global_clock_event) {
863 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
866 * Setup the apic timer manually
868 levt->event_handler = lapic_cal_handler;
869 lapic_timer_set_periodic(levt);
870 lapic_cal_loops = -1;
872 /* Let the interrupts run */
875 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
878 /* Stop the lapic timer */
880 lapic_timer_shutdown(levt);
883 deltaj = lapic_cal_j2 - lapic_cal_j1;
884 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
886 /* Check, if the jiffies result is consistent */
887 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
888 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
890 levt->features |= CLOCK_EVT_FEAT_DUMMY;
894 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
895 pr_warning("APIC timer disabled due to verification failure\n");
903 * Setup the boot APIC
905 * Calibrate and verify the result.
907 void __init setup_boot_APIC_clock(void)
910 * The local apic timer can be disabled via the kernel
911 * commandline or from the CPU detection code. Register the lapic
912 * timer as a dummy clock event source on SMP systems, so the
913 * broadcast mechanism is used. On UP systems simply ignore it.
915 if (disable_apic_timer) {
916 pr_info("Disabling APIC timer\n");
917 /* No broadcast on UP ! */
918 if (num_possible_cpus() > 1) {
919 lapic_clockevent.mult = 1;
925 if (calibrate_APIC_clock()) {
926 /* No broadcast on UP ! */
927 if (num_possible_cpus() > 1)
933 * If nmi_watchdog is set to IO_APIC, we need the
934 * PIT/HPET going. Otherwise register lapic as a dummy
937 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
939 /* Setup the lapic or request the broadcast */
943 void setup_secondary_APIC_clock(void)
949 * The guts of the apic timer interrupt
951 static void local_apic_timer_interrupt(void)
953 int cpu = smp_processor_id();
954 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
957 * Normally we should not be here till LAPIC has been initialized but
958 * in some cases like kdump, its possible that there is a pending LAPIC
959 * timer interrupt from previous kernel's context and is delivered in
960 * new kernel the moment interrupts are enabled.
962 * Interrupts are enabled early and LAPIC is setup much later, hence
963 * its possible that when we get here evt->event_handler is NULL.
964 * Check for event_handler being NULL and discard the interrupt as
967 if (!evt->event_handler) {
968 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
970 lapic_timer_shutdown(evt);
975 * the NMI deadlock-detector uses this.
977 inc_irq_stat(apic_timer_irqs);
979 evt->event_handler(evt);
983 * Local APIC timer interrupt. This is the most natural way for doing
984 * local interrupts, but local timer interrupts can be emulated by
985 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
987 * [ if a single-CPU system runs an SMP kernel then we call the local
988 * interrupt as well. Thus we cannot inline the local irq ... ]
990 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
992 struct pt_regs *old_regs = set_irq_regs(regs);
995 * NOTE! We'd better ACK the irq immediately,
996 * because timer handling can be slow.
998 * update_process_times() expects us to have done irq_enter().
999 * Besides, if we don't timer interrupts ignore the global
1000 * interrupt lock, which is the WrongThing (tm) to do.
1003 local_apic_timer_interrupt();
1006 set_irq_regs(old_regs);
1009 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
1011 struct pt_regs *old_regs = set_irq_regs(regs);
1014 * NOTE! We'd better ACK the irq immediately,
1015 * because timer handling can be slow.
1017 * update_process_times() expects us to have done irq_enter().
1018 * Besides, if we don't timer interrupts ignore the global
1019 * interrupt lock, which is the WrongThing (tm) to do.
1022 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1023 local_apic_timer_interrupt();
1024 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1027 set_irq_regs(old_regs);
1030 int setup_profiling_timer(unsigned int multiplier)
1036 * Local APIC start and shutdown
1040 * clear_local_APIC - shutdown the local APIC
1042 * This is called, when a CPU is disabled and before rebooting, so the state of
1043 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1044 * leftovers during boot.
1046 void clear_local_APIC(void)
1051 /* APIC hasn't been mapped yet */
1052 if (!x2apic_mode && !apic_phys)
1055 maxlvt = lapic_get_maxlvt();
1057 * Masking an LVT entry can trigger a local APIC error
1058 * if the vector is zero. Mask LVTERR first to prevent this.
1061 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1062 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1065 * Careful: we have to set masks only first to deassert
1066 * any level-triggered sources.
1068 v = apic_read(APIC_LVTT);
1069 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1070 v = apic_read(APIC_LVT0);
1071 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1072 v = apic_read(APIC_LVT1);
1073 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1075 v = apic_read(APIC_LVTPC);
1076 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1079 /* lets not touch this if we didn't frob it */
1080 #ifdef CONFIG_X86_THERMAL_VECTOR
1082 v = apic_read(APIC_LVTTHMR);
1083 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1086 #ifdef CONFIG_X86_MCE_INTEL
1088 v = apic_read(APIC_LVTCMCI);
1089 if (!(v & APIC_LVT_MASKED))
1090 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1095 * Clean APIC state for other OSs:
1097 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1098 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1099 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1101 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1103 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1105 /* Integrated APIC (!82489DX) ? */
1106 if (lapic_is_integrated()) {
1108 /* Clear ESR due to Pentium errata 3AP and 11AP */
1109 apic_write(APIC_ESR, 0);
1110 apic_read(APIC_ESR);
1115 * disable_local_APIC - clear and disable the local APIC
1117 void disable_local_APIC(void)
1121 /* APIC hasn't been mapped yet */
1122 if (!x2apic_mode && !apic_phys)
1128 * Disable APIC (implies clearing of registers
1131 value = apic_read(APIC_SPIV);
1132 value &= ~APIC_SPIV_APIC_ENABLED;
1133 apic_write(APIC_SPIV, value);
1135 #ifdef CONFIG_X86_32
1137 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1138 * restore the disabled state.
1140 if (enabled_via_apicbase) {
1143 rdmsr(MSR_IA32_APICBASE, l, h);
1144 l &= ~MSR_IA32_APICBASE_ENABLE;
1145 wrmsr(MSR_IA32_APICBASE, l, h);
1151 * If Linux enabled the LAPIC against the BIOS default disable it down before
1152 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1153 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1154 * for the case where Linux didn't enable the LAPIC.
1156 void lapic_shutdown(void)
1158 unsigned long flags;
1160 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1163 local_irq_save(flags);
1165 #ifdef CONFIG_X86_32
1166 if (!enabled_via_apicbase)
1170 disable_local_APIC();
1173 local_irq_restore(flags);
1177 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1179 void __init sync_Arb_IDs(void)
1182 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1185 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1191 apic_wait_icr_idle();
1193 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1194 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1195 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1199 * An initial setup of the virtual wire mode.
1201 void __init init_bsp_APIC(void)
1206 * Don't do the setup now if we have a SMP BIOS as the
1207 * through-I/O-APIC virtual wire mode might be active.
1209 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1213 * Do not trust the local APIC being empty at bootup.
1220 value = apic_read(APIC_SPIV);
1221 value &= ~APIC_VECTOR_MASK;
1222 value |= APIC_SPIV_APIC_ENABLED;
1224 #ifdef CONFIG_X86_32
1225 /* This bit is reserved on P4/Xeon and should be cleared */
1226 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1227 (boot_cpu_data.x86 == 15))
1228 value &= ~APIC_SPIV_FOCUS_DISABLED;
1231 value |= APIC_SPIV_FOCUS_DISABLED;
1232 value |= SPURIOUS_APIC_VECTOR;
1233 apic_write(APIC_SPIV, value);
1236 * Set up the virtual wire mode.
1238 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1239 value = APIC_DM_NMI;
1240 if (!lapic_is_integrated()) /* 82489DX */
1241 value |= APIC_LVT_LEVEL_TRIGGER;
1242 if (apic_extnmi == APIC_EXTNMI_NONE)
1243 value |= APIC_LVT_MASKED;
1244 apic_write(APIC_LVT1, value);
1247 static void lapic_setup_esr(void)
1249 unsigned int oldvalue, value, maxlvt;
1251 if (!lapic_is_integrated()) {
1252 pr_info("No ESR for 82489DX.\n");
1256 if (apic->disable_esr) {
1258 * Something untraceable is creating bad interrupts on
1259 * secondary quads ... for the moment, just leave the
1260 * ESR disabled - we can't do anything useful with the
1261 * errors anyway - mbligh
1263 pr_info("Leaving ESR disabled.\n");
1267 maxlvt = lapic_get_maxlvt();
1268 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1269 apic_write(APIC_ESR, 0);
1270 oldvalue = apic_read(APIC_ESR);
1272 /* enables sending errors */
1273 value = ERROR_APIC_VECTOR;
1274 apic_write(APIC_LVTERR, value);
1277 * spec says clear errors after enabling vector.
1280 apic_write(APIC_ESR, 0);
1281 value = apic_read(APIC_ESR);
1282 if (value != oldvalue)
1283 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1284 "vector: 0x%08x after: 0x%08x\n",
1288 static void apic_pending_intr_clear(void)
1290 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1291 unsigned long long tsc = 0, ntsc;
1292 unsigned int value, queued;
1293 int i, j, acked = 0;
1295 if (boot_cpu_has(X86_FEATURE_TSC))
1298 * After a crash, we no longer service the interrupts and a pending
1299 * interrupt from previous kernel might still have ISR bit set.
1301 * Most probably by now CPU has serviced that pending interrupt and
1302 * it might not have done the ack_APIC_irq() because it thought,
1303 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1304 * does not clear the ISR bit and cpu thinks it has already serivced
1305 * the interrupt. Hence a vector might get locked. It was noticed
1306 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1310 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1311 queued |= apic_read(APIC_IRR + i*0x10);
1313 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1314 value = apic_read(APIC_ISR + i*0x10);
1315 for (j = 31; j >= 0; j--) {
1316 if (value & (1<<j)) {
1323 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1328 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1330 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1334 } while (queued && max_loops > 0);
1335 WARN_ON(max_loops <= 0);
1339 * setup_local_APIC - setup the local APIC
1341 * Used to setup local APIC while initializing BSP or bringin up APs.
1342 * Always called with preemption disabled.
1344 void setup_local_APIC(void)
1346 int cpu = smp_processor_id();
1351 disable_ioapic_support();
1356 * If this comes from kexec/kcrash the APIC might be enabled in
1357 * SPIV. Soft disable it before doing further initialization.
1359 value = apic_read(APIC_SPIV);
1360 value &= ~APIC_SPIV_APIC_ENABLED;
1361 apic_write(APIC_SPIV, value);
1363 #ifdef CONFIG_X86_32
1364 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1365 if (lapic_is_integrated() && apic->disable_esr) {
1366 apic_write(APIC_ESR, 0);
1367 apic_write(APIC_ESR, 0);
1368 apic_write(APIC_ESR, 0);
1369 apic_write(APIC_ESR, 0);
1372 perf_events_lapic_init();
1375 * Double-check whether this APIC is really registered.
1376 * This is meaningless in clustered apic mode, so we skip it.
1378 BUG_ON(!apic->apic_id_registered());
1381 * Intel recommends to set DFR, LDR and TPR before enabling
1382 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1383 * document number 292116). So here it goes...
1385 apic->init_apic_ldr();
1387 #ifdef CONFIG_X86_32
1388 if (apic->dest_logical) {
1389 int logical_apicid, ldr_apicid;
1392 * APIC LDR is initialized. If logical_apicid mapping was
1393 * initialized during get_smp_config(), make sure it matches
1396 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1397 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1398 if (logical_apicid != BAD_APICID)
1399 WARN_ON(logical_apicid != ldr_apicid);
1400 /* Always use the value from LDR. */
1401 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1406 * Set Task Priority to 'accept all'. We never change this
1409 value = apic_read(APIC_TASKPRI);
1410 value &= ~APIC_TPRI_MASK;
1411 apic_write(APIC_TASKPRI, value);
1413 apic_pending_intr_clear();
1416 * Now that we are all set up, enable the APIC
1418 value = apic_read(APIC_SPIV);
1419 value &= ~APIC_VECTOR_MASK;
1423 value |= APIC_SPIV_APIC_ENABLED;
1425 #ifdef CONFIG_X86_32
1427 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1428 * certain networking cards. If high frequency interrupts are
1429 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1430 * entry is masked/unmasked at a high rate as well then sooner or
1431 * later IOAPIC line gets 'stuck', no more interrupts are received
1432 * from the device. If focus CPU is disabled then the hang goes
1435 * [ This bug can be reproduced easily with a level-triggered
1436 * PCI Ne2000 networking cards and PII/PIII processors, dual
1440 * Actually disabling the focus CPU check just makes the hang less
1441 * frequent as it makes the interrupt distributon model be more
1442 * like LRU than MRU (the short-term load is more even across CPUs).
1446 * - enable focus processor (bit==0)
1447 * - 64bit mode always use processor focus
1448 * so no need to set it
1450 value &= ~APIC_SPIV_FOCUS_DISABLED;
1454 * Set spurious IRQ vector
1456 value |= SPURIOUS_APIC_VECTOR;
1457 apic_write(APIC_SPIV, value);
1460 * Set up LVT0, LVT1:
1462 * set up through-local-APIC on the BP's LINT0. This is not
1463 * strictly necessary in pure symmetric-IO mode, but sometimes
1464 * we delegate interrupts to the 8259A.
1467 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1469 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1470 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1471 value = APIC_DM_EXTINT;
1472 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1474 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1475 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1477 apic_write(APIC_LVT0, value);
1480 * Only the BSP sees the LINT1 NMI signal by default. This can be
1481 * modified by apic_extnmi= boot option.
1483 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1484 apic_extnmi == APIC_EXTNMI_ALL)
1485 value = APIC_DM_NMI;
1487 value = APIC_DM_NMI | APIC_LVT_MASKED;
1488 if (!lapic_is_integrated()) /* 82489DX */
1489 value |= APIC_LVT_LEVEL_TRIGGER;
1490 apic_write(APIC_LVT1, value);
1492 #ifdef CONFIG_X86_MCE_INTEL
1493 /* Recheck CMCI information after local APIC is up on CPU #0 */
1499 static void end_local_APIC_setup(void)
1503 #ifdef CONFIG_X86_32
1506 /* Disable the local apic timer */
1507 value = apic_read(APIC_LVTT);
1508 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1509 apic_write(APIC_LVTT, value);
1517 * APIC setup function for application processors. Called from smpboot.c
1519 void apic_ap_setup(void)
1522 end_local_APIC_setup();
1525 #ifdef CONFIG_X86_X2APIC
1533 static int x2apic_state;
1535 static void __x2apic_disable(void)
1539 if (!boot_cpu_has(X86_FEATURE_APIC))
1542 rdmsrl(MSR_IA32_APICBASE, msr);
1543 if (!(msr & X2APIC_ENABLE))
1545 /* Disable xapic and x2apic first and then reenable xapic mode */
1546 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1547 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1548 printk_once(KERN_INFO "x2apic disabled\n");
1551 static void __x2apic_enable(void)
1555 rdmsrl(MSR_IA32_APICBASE, msr);
1556 if (msr & X2APIC_ENABLE)
1558 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1559 printk_once(KERN_INFO "x2apic enabled\n");
1562 static int __init setup_nox2apic(char *str)
1564 if (x2apic_enabled()) {
1565 int apicid = native_apic_msr_read(APIC_ID);
1567 if (apicid >= 255) {
1568 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1572 pr_warning("x2apic already enabled.\n");
1575 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1576 x2apic_state = X2APIC_DISABLED;
1580 early_param("nox2apic", setup_nox2apic);
1582 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1583 void x2apic_setup(void)
1586 * If x2apic is not in ON state, disable it if already enabled
1589 if (x2apic_state != X2APIC_ON) {
1596 static __init void x2apic_disable(void)
1598 u32 x2apic_id, state = x2apic_state;
1601 x2apic_state = X2APIC_DISABLED;
1603 if (state != X2APIC_ON)
1606 x2apic_id = read_apic_id();
1607 if (x2apic_id >= 255)
1608 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1611 register_lapic_address(mp_lapic_addr);
1614 static __init void x2apic_enable(void)
1616 if (x2apic_state != X2APIC_OFF)
1620 x2apic_state = X2APIC_ON;
1624 static __init void try_to_enable_x2apic(int remap_mode)
1626 if (x2apic_state == X2APIC_DISABLED)
1629 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1630 /* IR is required if there is APIC ID > 255 even when running
1633 if (max_physical_apicid > 255 ||
1634 !hypervisor_x2apic_available()) {
1635 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1641 * without IR all CPUs can be addressed by IOAPIC/MSI
1642 * only in physical mode
1649 void __init check_x2apic(void)
1651 if (x2apic_enabled()) {
1652 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1654 x2apic_state = X2APIC_ON;
1655 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1656 x2apic_state = X2APIC_DISABLED;
1659 #else /* CONFIG_X86_X2APIC */
1660 static int __init validate_x2apic(void)
1662 if (!apic_is_x2apic_enabled())
1665 * Checkme: Can we simply turn off x2apic here instead of panic?
1667 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1669 early_initcall(validate_x2apic);
1671 static inline void try_to_enable_x2apic(int remap_mode) { }
1672 static inline void __x2apic_enable(void) { }
1673 #endif /* !CONFIG_X86_X2APIC */
1675 static int __init try_to_enable_IR(void)
1677 #ifdef CONFIG_X86_IO_APIC
1678 if (!x2apic_enabled() && skip_ioapic_setup) {
1679 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1683 return irq_remapping_enable();
1686 void __init enable_IR_x2apic(void)
1688 unsigned long flags;
1691 if (skip_ioapic_setup)
1694 ir_stat = irq_remapping_prepare();
1695 if (ir_stat < 0 && !x2apic_supported())
1698 ret = save_ioapic_entries();
1700 pr_info("Saving IO-APIC state failed: %d\n", ret);
1704 local_irq_save(flags);
1705 legacy_pic->mask_all();
1706 mask_ioapic_entries();
1708 /* If irq_remapping_prepare() succeeded, try to enable it */
1710 ir_stat = try_to_enable_IR();
1711 /* ir_stat contains the remap mode or an error code */
1712 try_to_enable_x2apic(ir_stat);
1715 restore_ioapic_entries();
1716 legacy_pic->restore_mask();
1717 local_irq_restore(flags);
1720 #ifdef CONFIG_X86_64
1722 * Detect and enable local APICs on non-SMP boards.
1723 * Original code written by Keir Fraser.
1724 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1725 * not correctly set up (usually the APIC timer won't work etc.)
1727 static int __init detect_init_APIC(void)
1729 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1730 pr_info("No local APIC present\n");
1734 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1739 static int __init apic_verify(void)
1744 * The APIC feature bit should now be enabled
1747 features = cpuid_edx(1);
1748 if (!(features & (1 << X86_FEATURE_APIC))) {
1749 pr_warning("Could not enable APIC!\n");
1752 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1753 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1755 /* The BIOS may have set up the APIC at some other address */
1756 if (boot_cpu_data.x86 >= 6) {
1757 rdmsr(MSR_IA32_APICBASE, l, h);
1758 if (l & MSR_IA32_APICBASE_ENABLE)
1759 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1762 pr_info("Found and enabled local APIC!\n");
1766 int __init apic_force_enable(unsigned long addr)
1774 * Some BIOSes disable the local APIC in the APIC_BASE
1775 * MSR. This can only be done in software for Intel P6 or later
1776 * and AMD K7 (Model > 1) or later.
1778 if (boot_cpu_data.x86 >= 6) {
1779 rdmsr(MSR_IA32_APICBASE, l, h);
1780 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1781 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1782 l &= ~MSR_IA32_APICBASE_BASE;
1783 l |= MSR_IA32_APICBASE_ENABLE | addr;
1784 wrmsr(MSR_IA32_APICBASE, l, h);
1785 enabled_via_apicbase = 1;
1788 return apic_verify();
1792 * Detect and initialize APIC
1794 static int __init detect_init_APIC(void)
1796 /* Disabled by kernel option? */
1800 switch (boot_cpu_data.x86_vendor) {
1801 case X86_VENDOR_AMD:
1802 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1803 (boot_cpu_data.x86 >= 15))
1806 case X86_VENDOR_INTEL:
1807 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1808 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1815 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1817 * Over-ride BIOS and try to enable the local APIC only if
1818 * "lapic" specified.
1820 if (!force_enable_local_apic) {
1821 pr_info("Local APIC disabled by BIOS -- "
1822 "you can enable it with \"lapic\"\n");
1825 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1837 pr_info("No local APIC present or hardware disabled\n");
1843 * init_apic_mappings - initialize APIC mappings
1845 void __init init_apic_mappings(void)
1847 unsigned int new_apicid;
1850 boot_cpu_physical_apicid = read_apic_id();
1854 /* If no local APIC can be found return early */
1855 if (!smp_found_config && detect_init_APIC()) {
1856 /* lets NOP'ify apic operations */
1857 pr_info("APIC: disable apic facility\n");
1860 apic_phys = mp_lapic_addr;
1863 * acpi lapic path already maps that address in
1864 * acpi_register_lapic_address()
1866 if (!acpi_lapic && !smp_found_config)
1867 register_lapic_address(apic_phys);
1871 * Fetch the APIC ID of the BSP in case we have a
1872 * default configuration (or the MP table is broken).
1874 new_apicid = read_apic_id();
1875 if (boot_cpu_physical_apicid != new_apicid) {
1876 boot_cpu_physical_apicid = new_apicid;
1878 * yeah -- we lie about apic_version
1879 * in case if apic was disabled via boot option
1880 * but it's not a problem for SMP compiled kernel
1881 * since smp_sanity_check is prepared for such a case
1882 * and disable smp mode
1884 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1888 void __init register_lapic_address(unsigned long address)
1890 mp_lapic_addr = address;
1893 set_fixmap_nocache(FIX_APIC_BASE, address);
1894 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1895 APIC_BASE, address);
1897 if (boot_cpu_physical_apicid == -1U) {
1898 boot_cpu_physical_apicid = read_apic_id();
1899 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1904 * Local APIC interrupts
1908 * This interrupt should _never_ happen with our APIC/SMP architecture
1910 static void __smp_spurious_interrupt(u8 vector)
1915 * Check if this really is a spurious interrupt and ACK it
1916 * if it is a vectored one. Just in case...
1917 * Spurious interrupts should not be ACKed.
1919 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1920 if (v & (1 << (vector & 0x1f)))
1923 inc_irq_stat(irq_spurious_count);
1925 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1926 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1927 "should never happen.\n", vector, smp_processor_id());
1930 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1933 __smp_spurious_interrupt(~regs->orig_ax);
1937 __visible void __irq_entry smp_trace_spurious_interrupt(struct pt_regs *regs)
1939 u8 vector = ~regs->orig_ax;
1942 trace_spurious_apic_entry(vector);
1943 __smp_spurious_interrupt(vector);
1944 trace_spurious_apic_exit(vector);
1949 * This interrupt should never happen with our APIC/SMP architecture
1951 static void __smp_error_interrupt(struct pt_regs *regs)
1955 static const char * const error_interrupt_reason[] = {
1956 "Send CS error", /* APIC Error Bit 0 */
1957 "Receive CS error", /* APIC Error Bit 1 */
1958 "Send accept error", /* APIC Error Bit 2 */
1959 "Receive accept error", /* APIC Error Bit 3 */
1960 "Redirectable IPI", /* APIC Error Bit 4 */
1961 "Send illegal vector", /* APIC Error Bit 5 */
1962 "Received illegal vector", /* APIC Error Bit 6 */
1963 "Illegal register address", /* APIC Error Bit 7 */
1966 /* First tickle the hardware, only then report what went on. -- REW */
1967 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1968 apic_write(APIC_ESR, 0);
1969 v = apic_read(APIC_ESR);
1971 atomic_inc(&irq_err_count);
1973 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1974 smp_processor_id(), v);
1979 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1984 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1988 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
1991 __smp_error_interrupt(regs);
1995 __visible void __irq_entry smp_trace_error_interrupt(struct pt_regs *regs)
1998 trace_error_apic_entry(ERROR_APIC_VECTOR);
1999 __smp_error_interrupt(regs);
2000 trace_error_apic_exit(ERROR_APIC_VECTOR);
2005 * connect_bsp_APIC - attach the APIC to the interrupt system
2007 static void __init connect_bsp_APIC(void)
2009 #ifdef CONFIG_X86_32
2012 * Do not trust the local APIC being empty at bootup.
2016 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2017 * local APIC to INT and NMI lines.
2019 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2020 "enabling APIC mode.\n");
2027 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2028 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2030 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2033 void disconnect_bsp_APIC(int virt_wire_setup)
2037 #ifdef CONFIG_X86_32
2040 * Put the board back into PIC mode (has an effect only on
2041 * certain older boards). Note that APIC interrupts, including
2042 * IPIs, won't work beyond this point! The only exception are
2045 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2046 "entering PIC mode.\n");
2052 /* Go back to Virtual Wire compatibility mode */
2054 /* For the spurious interrupt use vector F, and enable it */
2055 value = apic_read(APIC_SPIV);
2056 value &= ~APIC_VECTOR_MASK;
2057 value |= APIC_SPIV_APIC_ENABLED;
2059 apic_write(APIC_SPIV, value);
2061 if (!virt_wire_setup) {
2063 * For LVT0 make it edge triggered, active high,
2064 * external and enabled
2066 value = apic_read(APIC_LVT0);
2067 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2068 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2069 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2070 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2071 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2072 apic_write(APIC_LVT0, value);
2075 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2079 * For LVT1 make it edge triggered, active high,
2082 value = apic_read(APIC_LVT1);
2083 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2084 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2085 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2086 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2087 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2088 apic_write(APIC_LVT1, value);
2092 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2093 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2094 * All allocated CPU ID should be in [0, nr_logical_cpuidi), so the maximum of
2095 * nr_logical_cpuids is nr_cpu_ids.
2097 * NOTE: Reserve 0 for BSP.
2099 static int nr_logical_cpuids = 1;
2102 * Used to store mapping between logical CPU IDs and APIC IDs.
2104 static int cpuid_to_apicid[] = {
2105 [0 ... NR_CPUS - 1] = -1,
2110 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2111 * @id: APIC ID to check
2113 bool apic_id_is_primary_thread(unsigned int apicid)
2117 if (smp_num_siblings == 1)
2119 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2120 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2121 return !(apicid & mask);
2126 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2127 * and cpuid_to_apicid[] synchronized.
2129 static int allocate_logical_cpuid(int apicid)
2134 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2135 * check if the kernel has allocated a cpuid for it.
2137 for (i = 0; i < nr_logical_cpuids; i++) {
2138 if (cpuid_to_apicid[i] == apicid)
2142 /* Allocate a new cpuid. */
2143 if (nr_logical_cpuids >= nr_cpu_ids) {
2144 WARN_ONCE(1, "Only %d processors supported."
2145 "Processor %d/0x%x and the rest are ignored.\n",
2146 nr_cpu_ids - 1, nr_logical_cpuids, apicid);
2150 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2151 return nr_logical_cpuids++;
2154 int generic_processor_info(int apicid, int version)
2156 int cpu, max = nr_cpu_ids;
2157 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2158 phys_cpu_present_map);
2161 * boot_cpu_physical_apicid is designed to have the apicid
2162 * returned by read_apic_id(), i.e, the apicid of the
2163 * currently booting-up processor. However, on some platforms,
2164 * it is temporarily modified by the apicid reported as BSP
2165 * through MP table. Concretely:
2167 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2168 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2170 * This function is executed with the modified
2171 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2172 * parameter doesn't work to disable APs on kdump 2nd kernel.
2174 * Since fixing handling of boot_cpu_physical_apicid requires
2175 * another discussion and tests on each platform, we leave it
2176 * for now and here we use read_apic_id() directly in this
2177 * function, generic_processor_info().
2179 if (disabled_cpu_apicid != BAD_APICID &&
2180 disabled_cpu_apicid != read_apic_id() &&
2181 disabled_cpu_apicid == apicid) {
2182 int thiscpu = num_processors + disabled_cpus;
2184 pr_warning("APIC: Disabling requested cpu."
2185 " Processor %d/0x%x ignored.\n",
2193 * If boot cpu has not been detected yet, then only allow upto
2194 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2196 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2197 apicid != boot_cpu_physical_apicid) {
2198 int thiscpu = max + disabled_cpus - 1;
2201 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2202 " reached. Keeping one slot for boot cpu."
2203 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2209 if (num_processors >= nr_cpu_ids) {
2210 int thiscpu = max + disabled_cpus;
2212 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2213 "reached. Processor %d/0x%x ignored.\n",
2214 max, thiscpu, apicid);
2220 if (apicid == boot_cpu_physical_apicid) {
2222 * x86_bios_cpu_apicid is required to have processors listed
2223 * in same order as logical cpu numbers. Hence the first
2224 * entry is BSP, and so on.
2225 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2230 /* Logical cpuid 0 is reserved for BSP. */
2231 cpuid_to_apicid[0] = apicid;
2233 cpu = allocate_logical_cpuid(apicid);
2243 if (version == 0x0) {
2244 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2249 if (version != boot_cpu_apic_version) {
2250 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2251 boot_cpu_apic_version, cpu, version);
2254 if (apicid > max_physical_apicid)
2255 max_physical_apicid = apicid;
2257 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2258 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2259 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2261 #ifdef CONFIG_X86_32
2262 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2263 apic->x86_32_early_logical_apicid(cpu);
2265 set_cpu_possible(cpu, true);
2266 physid_set(apicid, phys_cpu_present_map);
2267 set_cpu_present(cpu, true);
2273 int hard_smp_processor_id(void)
2275 return read_apic_id();
2278 void default_init_apic_ldr(void)
2282 apic_write(APIC_DFR, APIC_DFR_VALUE);
2283 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2284 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2285 apic_write(APIC_LDR, val);
2288 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2289 const struct cpumask *andmask,
2290 unsigned int *apicid)
2294 for_each_cpu_and(cpu, cpumask, andmask) {
2295 if (cpumask_test_cpu(cpu, cpu_online_mask))
2299 if (likely(cpu < nr_cpu_ids)) {
2300 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2308 * Override the generic EOI implementation with an optimized version.
2309 * Only called during early boot when only one CPU is active and with
2310 * interrupts disabled, so we know this does not race with actual APIC driver
2313 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2317 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2318 /* Should happen once for each apic */
2319 WARN_ON((*drv)->eoi_write == eoi_write);
2320 (*drv)->eoi_write = eoi_write;
2324 static void __init apic_bsp_up_setup(void)
2326 #ifdef CONFIG_X86_64
2327 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2330 * Hack: In case of kdump, after a crash, kernel might be booting
2331 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2332 * might be zero if read from MP tables. Get it from LAPIC.
2334 # ifdef CONFIG_CRASH_DUMP
2335 boot_cpu_physical_apicid = read_apic_id();
2338 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2342 * apic_bsp_setup - Setup function for local apic and io-apic
2343 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2346 * apic_id of BSP APIC
2348 int __init apic_bsp_setup(bool upmode)
2354 apic_bsp_up_setup();
2358 id = apic_read(APIC_LDR);
2360 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2363 end_local_APIC_setup();
2364 irq_remap_enable_fault_handling();
2366 /* Setup local timer */
2367 x86_init.timers.setup_percpu_clockev();
2372 * This initializes the IO-APIC and APIC hardware if this is
2375 int __init APIC_init_uniprocessor(void)
2378 pr_info("Apic disabled\n");
2381 #ifdef CONFIG_X86_64
2382 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2384 pr_info("Apic disabled by BIOS\n");
2388 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2392 * Complain if the BIOS pretends there is one.
2394 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2395 APIC_INTEGRATED(boot_cpu_apic_version)) {
2396 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2397 boot_cpu_physical_apicid);
2402 if (!smp_found_config)
2403 disable_ioapic_support();
2405 default_setup_apic_routing();
2406 apic_bsp_setup(true);
2410 #ifdef CONFIG_UP_LATE_INIT
2411 void __init up_late_init(void)
2413 APIC_init_uniprocessor();
2424 * 'active' is true if the local APIC was enabled by us and
2425 * not the BIOS; this signifies that we are also responsible
2426 * for disabling it before entering apm/acpi suspend
2429 /* r/w apic fields */
2430 unsigned int apic_id;
2431 unsigned int apic_taskpri;
2432 unsigned int apic_ldr;
2433 unsigned int apic_dfr;
2434 unsigned int apic_spiv;
2435 unsigned int apic_lvtt;
2436 unsigned int apic_lvtpc;
2437 unsigned int apic_lvt0;
2438 unsigned int apic_lvt1;
2439 unsigned int apic_lvterr;
2440 unsigned int apic_tmict;
2441 unsigned int apic_tdcr;
2442 unsigned int apic_thmr;
2443 unsigned int apic_cmci;
2446 static int lapic_suspend(void)
2448 unsigned long flags;
2451 if (!apic_pm_state.active)
2454 maxlvt = lapic_get_maxlvt();
2456 apic_pm_state.apic_id = apic_read(APIC_ID);
2457 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2458 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2459 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2460 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2461 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2463 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2464 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2465 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2466 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2467 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2468 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2469 #ifdef CONFIG_X86_THERMAL_VECTOR
2471 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2473 #ifdef CONFIG_X86_MCE_INTEL
2475 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2478 local_irq_save(flags);
2479 disable_local_APIC();
2481 irq_remapping_disable();
2483 local_irq_restore(flags);
2487 static void lapic_resume(void)
2490 unsigned long flags;
2493 if (!apic_pm_state.active)
2496 local_irq_save(flags);
2499 * IO-APIC and PIC have their own resume routines.
2500 * We just mask them here to make sure the interrupt
2501 * subsystem is completely quiet while we enable x2apic
2502 * and interrupt-remapping.
2504 mask_ioapic_entries();
2505 legacy_pic->mask_all();
2511 * Make sure the APICBASE points to the right address
2513 * FIXME! This will be wrong if we ever support suspend on
2514 * SMP! We'll need to do this as part of the CPU restore!
2516 if (boot_cpu_data.x86 >= 6) {
2517 rdmsr(MSR_IA32_APICBASE, l, h);
2518 l &= ~MSR_IA32_APICBASE_BASE;
2519 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2520 wrmsr(MSR_IA32_APICBASE, l, h);
2524 maxlvt = lapic_get_maxlvt();
2525 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2526 apic_write(APIC_ID, apic_pm_state.apic_id);
2527 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2528 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2529 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2530 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2531 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2532 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2533 #ifdef CONFIG_X86_THERMAL_VECTOR
2535 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2537 #ifdef CONFIG_X86_MCE_INTEL
2539 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2542 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2543 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2544 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2545 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2546 apic_write(APIC_ESR, 0);
2547 apic_read(APIC_ESR);
2548 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2549 apic_write(APIC_ESR, 0);
2550 apic_read(APIC_ESR);
2552 irq_remapping_reenable(x2apic_mode);
2554 local_irq_restore(flags);
2558 * This device has no shutdown method - fully functioning local APICs
2559 * are needed on every CPU up until machine_halt/restart/poweroff.
2562 static struct syscore_ops lapic_syscore_ops = {
2563 .resume = lapic_resume,
2564 .suspend = lapic_suspend,
2567 static void apic_pm_activate(void)
2569 apic_pm_state.active = 1;
2572 static int __init init_lapic_sysfs(void)
2574 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2575 if (boot_cpu_has(X86_FEATURE_APIC))
2576 register_syscore_ops(&lapic_syscore_ops);
2581 /* local apic needs to resume before other devices access its registers. */
2582 core_initcall(init_lapic_sysfs);
2584 #else /* CONFIG_PM */
2586 static void apic_pm_activate(void) { }
2588 #endif /* CONFIG_PM */
2590 #ifdef CONFIG_X86_64
2592 static int multi_checked;
2595 static int set_multi(const struct dmi_system_id *d)
2599 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2604 static const struct dmi_system_id multi_dmi_table[] = {
2606 .callback = set_multi,
2607 .ident = "IBM System Summit2",
2609 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2610 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2616 static void dmi_check_multi(void)
2621 dmi_check_system(multi_dmi_table);
2626 * apic_is_clustered_box() -- Check if we can expect good TSC
2628 * Thus far, the major user of this is IBM's Summit2 series:
2629 * Clustered boxes may have unsynced TSC problems if they are
2631 * Use DMI to check them
2633 int apic_is_clustered_box(void)
2641 * APIC command line parameters
2643 static int __init setup_disableapic(char *arg)
2646 setup_clear_cpu_cap(X86_FEATURE_APIC);
2649 early_param("disableapic", setup_disableapic);
2651 /* same as disableapic, for compatibility */
2652 static int __init setup_nolapic(char *arg)
2654 return setup_disableapic(arg);
2656 early_param("nolapic", setup_nolapic);
2658 static int __init parse_lapic_timer_c2_ok(char *arg)
2660 local_apic_timer_c2_ok = 1;
2663 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2665 static int __init parse_disable_apic_timer(char *arg)
2667 disable_apic_timer = 1;
2670 early_param("noapictimer", parse_disable_apic_timer);
2672 static int __init parse_nolapic_timer(char *arg)
2674 disable_apic_timer = 1;
2677 early_param("nolapic_timer", parse_nolapic_timer);
2679 static int __init apic_set_verbosity(char *arg)
2682 #ifdef CONFIG_X86_64
2683 skip_ioapic_setup = 0;
2689 if (strcmp("debug", arg) == 0)
2690 apic_verbosity = APIC_DEBUG;
2691 else if (strcmp("verbose", arg) == 0)
2692 apic_verbosity = APIC_VERBOSE;
2694 pr_warning("APIC Verbosity level %s not recognised"
2695 " use apic=verbose or apic=debug\n", arg);
2701 early_param("apic", apic_set_verbosity);
2703 static int __init lapic_insert_resource(void)
2708 /* Put local APIC into the resource map. */
2709 lapic_resource.start = apic_phys;
2710 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2711 insert_resource(&iomem_resource, &lapic_resource);
2717 * need call insert after e820_reserve_resources()
2718 * that is using request_resource
2720 late_initcall(lapic_insert_resource);
2722 static int __init apic_set_disabled_cpu_apicid(char *arg)
2724 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2729 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2731 static int __init apic_set_extnmi(char *arg)
2736 if (!strncmp("all", arg, 3))
2737 apic_extnmi = APIC_EXTNMI_ALL;
2738 else if (!strncmp("none", arg, 4))
2739 apic_extnmi = APIC_EXTNMI_NONE;
2740 else if (!strncmp("bsp", arg, 3))
2741 apic_extnmi = APIC_EXTNMI_BSP;
2743 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2749 early_param("apic_extnmi", apic_set_extnmi);