arch/x86/kernel/amd_nb.c

   1 /*
   2  * Shared support code for AMD K8 northbridges and derivates.
   3  * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/types.h>
   9 #include <linux/slab.h>
  10 #include <linux/init.h>
  11 #include <linux/errno.h>
  12 #include <linux/export.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/pci_ids.h>
  15 #include <asm/amd_nb.h>
  16
  17 #define PCI_DEVICE_ID_AMD_17H_ROOT      0x1450
  18 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
  19 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
  20 #define PCI_DEVICE_ID_AMD_17H_DF_F4     0x1464
  21 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
  22 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
  23 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
  24 #define PCI_DEVICE_ID_AMD_19H_DF_F4     0x1654
  25
  26 /* Protect the PCI config register pairs used for SMN and DF indirect access. */
  27 static DEFINE_MUTEX(smn_mutex);
  28
  29 static u32 *flush_words;
  30
  31 static const struct pci_device_id amd_root_ids[] = {
  32         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
  33         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
  34         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
  35         {}
  36 };
  37
  38
  39 #define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704
  40
  41 const struct pci_device_id amd_nb_misc_ids[] = {
  42         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
  43         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
  44         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
  45         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
  46         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
  47         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
  48         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
  49         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
  50         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
  51         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
  52         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
  53         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
  54         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
  55         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
  56         {}
  57 };
  58 EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
  59
  60 static const struct pci_device_id amd_nb_link_ids[] = {
  61         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
  62         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
  63         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
  64         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
  67         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
  68         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
  69         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
  70         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
  71         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
  72         {}
  73 };
  74
  75 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
  76         { 0x00, 0x18, 0x20 },
  77         { 0xff, 0x00, 0x20 },
  78         { 0xfe, 0x00, 0x20 },
  79         { }
  80 };
  81
  82 static struct amd_northbridge_info amd_northbridges;
  83
  84 u16 amd_nb_num(void)
  85 {
  86         return amd_northbridges.num;
  87 }
  88 EXPORT_SYMBOL_GPL(amd_nb_num);
  89
  90 bool amd_nb_has_feature(unsigned int feature)
  91 {
  92         return ((amd_northbridges.flags & feature) == feature);
  93 }
  94 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
  95
  96 struct amd_northbridge *node_to_amd_nb(int node)
  97 {
  98         return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
  99 }
 100 EXPORT_SYMBOL_GPL(node_to_amd_nb);
 101
 102 static struct pci_dev *next_northbridge(struct pci_dev *dev,
 103                                         const struct pci_device_id *ids)
 104 {
 105         do {
 106                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
 107                 if (!dev)
 108                         break;
 109         } while (!pci_match_id(ids, dev));
 110         return dev;
 111 }
 112
 113 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
 114 {
 115         struct pci_dev *root;
 116         int err = -ENODEV;
 117
 118         if (node >= amd_northbridges.num)
 119                 goto out;
 120
 121         root = node_to_amd_nb(node)->root;
 122         if (!root)
 123                 goto out;
 124
 125         mutex_lock(&smn_mutex);
 126
 127         err = pci_write_config_dword(root, 0x60, address);
 128         if (err) {
 129                 pr_warn("Error programming SMN address 0x%x.\n", address);
 130                 goto out_unlock;
 131         }
 132
 133         err = (write ? pci_write_config_dword(root, 0x64, *value)
 134                      : pci_read_config_dword(root, 0x64, value));
 135         if (err)
 136                 pr_warn("Error %s SMN address 0x%x.\n",
 137                         (write ? "writing to" : "reading from"), address);
 138
 139 out_unlock:
 140         mutex_unlock(&smn_mutex);
 141
 142 out:
 143         return err;
 144 }
 145
 146 int amd_smn_read(u16 node, u32 address, u32 *value)
 147 {
 148         return __amd_smn_rw(node, address, value, false);
 149 }
 150 EXPORT_SYMBOL_GPL(amd_smn_read);
 151
 152 int amd_smn_write(u16 node, u32 address, u32 value)
 153 {
 154         return __amd_smn_rw(node, address, &value, true);
 155 }
 156 EXPORT_SYMBOL_GPL(amd_smn_write);
 157
 158 /*
 159  * Data Fabric Indirect Access uses FICAA/FICAD.
 160  *
 161  * Fabric Indirect Configuration Access Address (FICAA): Constructed based
 162  * on the device's Instance Id and the PCI function and register offset of
 163  * the desired register.
 164  *
 165  * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
 166  * and FICAD HI registers but so far we only need the LO register.
 167  */
 168 int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
 169 {
 170         struct pci_dev *F4;
 171         u32 ficaa;
 172         int err = -ENODEV;
 173
 174         if (node >= amd_northbridges.num)
 175                 goto out;
 176
 177         F4 = node_to_amd_nb(node)->link;
 178         if (!F4)
 179                 goto out;
 180
 181         ficaa  = 1;
 182         ficaa |= reg & 0x3FC;
 183         ficaa |= (func & 0x7) << 11;
 184         ficaa |= instance_id << 16;
 185
 186         mutex_lock(&smn_mutex);
 187
 188         err = pci_write_config_dword(F4, 0x5C, ficaa);
 189         if (err) {
 190                 pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
 191                 goto out_unlock;
 192         }
 193
 194         err = pci_read_config_dword(F4, 0x98, lo);
 195         if (err)
 196                 pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
 197
 198 out_unlock:
 199         mutex_unlock(&smn_mutex);
 200
 201 out:
 202         return err;
 203 }
 204 EXPORT_SYMBOL_GPL(amd_df_indirect_read);
 205
 206 int amd_cache_northbridges(void)
 207 {
 208         u16 i = 0;
 209         struct amd_northbridge *nb;
 210         struct pci_dev *root, *misc, *link;
 211
 212         if (amd_northbridges.num)
 213                 return 0;
 214
 215         misc = NULL;
 216         while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
 217                 i++;
 218
 219         if (!i)
 220                 return -ENODEV;
 221
 222         nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
 223         if (!nb)
 224                 return -ENOMEM;
 225
 226         amd_northbridges.nb = nb;
 227         amd_northbridges.num = i;
 228
 229         link = misc = root = NULL;
 230         for (i = 0; i != amd_northbridges.num; i++) {
 231                 node_to_amd_nb(i)->root = root =
 232                         next_northbridge(root, amd_root_ids);
 233                 node_to_amd_nb(i)->misc = misc =
 234                         next_northbridge(misc, amd_nb_misc_ids);
 235                 node_to_amd_nb(i)->link = link =
 236                         next_northbridge(link, amd_nb_link_ids);
 237         }
 238
 239         if (amd_gart_present())
 240                 amd_northbridges.flags |= AMD_NB_GART;
 241
 242         /*
 243          * Check for L3 cache presence.
 244          */
 245         if (!cpuid_edx(0x80000006))
 246                 return 0;
 247
 248         /*
 249          * Some CPU families support L3 Cache Index Disable. There are some
 250          * limitations because of E382 and E388 on family 0x10.
 251          */
 252         if (boot_cpu_data.x86 == 0x10 &&
 253             boot_cpu_data.x86_model >= 0x8 &&
 254             (boot_cpu_data.x86_model > 0x9 ||
 255              boot_cpu_data.x86_stepping >= 0x1))
 256                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 257
 258         if (boot_cpu_data.x86 == 0x15)
 259                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 260
 261         /* L3 cache partitioning is supported on family 0x15 */
 262         if (boot_cpu_data.x86 == 0x15)
 263                 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
 264
 265         return 0;
 266 }
 267 EXPORT_SYMBOL_GPL(amd_cache_northbridges);
 268
 269 /*
 270  * Ignores subdevice/subvendor but as far as I can figure out
 271  * they're useless anyways
 272  */
 273 bool __init early_is_amd_nb(u32 device)
 274 {
 275         const struct pci_device_id *id;
 276         u32 vendor = device & 0xffff;
 277
 278         device >>= 16;
 279         for (id = amd_nb_misc_ids; id->vendor; id++)
 280                 if (vendor == id->vendor && device == id->device)
 281                         return true;
 282         return false;
 283 }
 284
 285 struct resource *amd_get_mmconfig_range(struct resource *res)
 286 {
 287         u32 address;
 288         u64 base, msr;
 289         unsigned int segn_busn_bits;
 290
 291         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 292                 return NULL;
 293
 294         /* assume all cpus from fam10h have mmconfig */
 295         if (boot_cpu_data.x86 < 0x10)
 296                 return NULL;
 297
 298         address = MSR_FAM10H_MMIO_CONF_BASE;
 299         rdmsrl(address, msr);
 300
 301         /* mmconfig is not enabled */
 302         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 303                 return NULL;
 304
 305         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 306
 307         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 308                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 309
 310         res->flags = IORESOURCE_MEM;
 311         res->start = base;
 312         res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 313         return res;
 314 }
 315
 316 int amd_get_subcaches(int cpu)
 317 {
 318         struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
 319         unsigned int mask;
 320
 321         if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 322                 return 0;
 323
 324         pci_read_config_dword(link, 0x1d4, &mask);
 325
 326         return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
 327 }
 328
 329 int amd_set_subcaches(int cpu, unsigned long mask)
 330 {
 331         static unsigned int reset, ban;
 332         struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
 333         unsigned int reg;
 334         int cuid;
 335
 336         if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
 337                 return -EINVAL;
 338
 339         /* if necessary, collect reset state of L3 partitioning and BAN mode */
 340         if (reset == 0) {
 341                 pci_read_config_dword(nb->link, 0x1d4, &reset);
 342                 pci_read_config_dword(nb->misc, 0x1b8, &ban);
 343                 ban &= 0x180000;
 344         }
 345
 346         /* deactivate BAN mode if any subcaches are to be disabled */
 347         if (mask != 0xf) {
 348                 pci_read_config_dword(nb->misc, 0x1b8, &reg);
 349                 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
 350         }
 351
 352         cuid = cpu_data(cpu).cpu_core_id;
 353         mask <<= 4 * cuid;
 354         mask |= (0xf ^ (1 << cuid)) << 26;
 355
 356         pci_write_config_dword(nb->link, 0x1d4, mask);
 357
 358         /* reset BAN mode if L3 partitioning returned to reset state */
 359         pci_read_config_dword(nb->link, 0x1d4, &reg);
 360         if (reg == reset) {
 361                 pci_read_config_dword(nb->misc, 0x1b8, &reg);
 362                 reg &= ~0x180000;
 363                 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
 364         }
 365
 366         return 0;
 367 }
 368
 369 static void amd_cache_gart(void)
 370 {
 371         u16 i;
 372
 373         if (!amd_nb_has_feature(AMD_NB_GART))
 374                 return;
 375
 376         flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
 377         if (!flush_words) {
 378                 amd_northbridges.flags &= ~AMD_NB_GART;
 379                 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
 380                 return;
 381         }
 382
 383         for (i = 0; i != amd_northbridges.num; i++)
 384                 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
 385 }
 386
 387 void amd_flush_garts(void)
 388 {
 389         int flushed, i;
 390         unsigned long flags;
 391         static DEFINE_SPINLOCK(gart_lock);
 392
 393         if (!amd_nb_has_feature(AMD_NB_GART))
 394                 return;
 395
 396         /*
 397          * Avoid races between AGP and IOMMU. In theory it's not needed
 398          * but I'm not sure if the hardware won't lose flush requests
 399          * when another is pending. This whole thing is so expensive anyways
 400          * that it doesn't matter to serialize more. -AK
 401          */
 402         spin_lock_irqsave(&gart_lock, flags);
 403         flushed = 0;
 404         for (i = 0; i < amd_northbridges.num; i++) {
 405                 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
 406                                        flush_words[i] | 1);
 407                 flushed++;
 408         }
 409         for (i = 0; i < amd_northbridges.num; i++) {
 410                 u32 w;
 411                 /* Make sure the hardware actually executed the flush*/
 412                 for (;;) {
 413                         pci_read_config_dword(node_to_amd_nb(i)->misc,
 414                                               0x9c, &w);
 415                         if (!(w & 1))
 416                                 break;
 417                         cpu_relax();
 418                 }
 419         }
 420         spin_unlock_irqrestore(&gart_lock, flags);
 421         if (!flushed)
 422                 pr_notice("nothing to flush?\n");
 423 }
 424 EXPORT_SYMBOL_GPL(amd_flush_garts);
 425
 426 static void __fix_erratum_688(void *info)
 427 {
 428 #define MSR_AMD64_IC_CFG 0xC0011021
 429
 430         msr_set_bit(MSR_AMD64_IC_CFG, 3);
 431         msr_set_bit(MSR_AMD64_IC_CFG, 14);
 432 }
 433
 434 /* Apply erratum 688 fix so machines without a BIOS fix work. */
 435 static __init void fix_erratum_688(void)
 436 {
 437         struct pci_dev *F4;
 438         u32 val;
 439
 440         if (boot_cpu_data.x86 != 0x14)
 441                 return;
 442
 443         if (!amd_northbridges.num)
 444                 return;
 445
 446         F4 = node_to_amd_nb(0)->link;
 447         if (!F4)
 448                 return;
 449
 450         if (pci_read_config_dword(F4, 0x164, &val))
 451                 return;
 452
 453         if (val & BIT(2))
 454                 return;
 455
 456         on_each_cpu(__fix_erratum_688, NULL, 0);
 457
 458         pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
 459 }
 460
 461 static __init int init_amd_nbs(void)
 462 {
 463         amd_cache_northbridges();
 464         amd_cache_gart();
 465
 466         fix_erratum_688();
 467
 468         return 0;
 469 }
 470
 471 /* This has to go after the PCI subsystem */
 472 fs_initcall(init_amd_nbs);