1 #define pr_fmt(fmt) "SMP alternatives: " fmt
3 #include <linux/module.h>
4 #include <linux/sched.h>
5 #include <linux/mutex.h>
6 #include <linux/list.h>
7 #include <linux/stringify.h>
9 #include <linux/vmalloc.h>
10 #include <linux/memory.h>
11 #include <linux/stop_machine.h>
12 #include <linux/slab.h>
13 #include <linux/kdebug.h>
14 #include <asm/text-patching.h>
15 #include <asm/alternative.h>
16 #include <asm/sections.h>
17 #include <asm/pgtable.h>
20 #include <asm/cacheflush.h>
21 #include <asm/tlbflush.h>
23 #include <asm/fixmap.h>
25 int __read_mostly alternatives_patched;
27 EXPORT_SYMBOL_GPL(alternatives_patched);
29 #define MAX_PATCH_LEN (255-1)
31 static int __initdata_or_module debug_alternative;
33 static int __init debug_alt(char *str)
35 debug_alternative = 1;
38 __setup("debug-alternative", debug_alt);
40 static int noreplace_smp;
42 static int __init setup_noreplace_smp(char *str)
47 __setup("noreplace-smp", setup_noreplace_smp);
49 #define DPRINTK(fmt, args...) \
51 if (debug_alternative) \
52 printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
55 #define DUMP_BYTES(buf, len, fmt, args...) \
57 if (unlikely(debug_alternative)) { \
63 printk(KERN_DEBUG fmt, ##args); \
64 for (j = 0; j < (len) - 1; j++) \
65 printk(KERN_CONT "%02hhx ", buf[j]); \
66 printk(KERN_CONT "%02hhx\n", buf[j]); \
71 * Each GENERIC_NOPX is of X bytes, and defined as an array of bytes
72 * that correspond to that nop. Getting from one nop to the next, we
73 * add to the array the offset that is equal to the sum of all sizes of
74 * nops preceding the one we are after.
76 * Note: The GENERIC_NOP5_ATOMIC is at the end, as it breaks the
77 * nice symmetry of sizes of the previous nops.
79 #if defined(GENERIC_NOP1) && !defined(CONFIG_X86_64)
80 static const unsigned char intelnops[] =
92 static const unsigned char * const intel_nops[ASM_NOP_MAX+2] =
98 intelnops + 1 + 2 + 3,
99 intelnops + 1 + 2 + 3 + 4,
100 intelnops + 1 + 2 + 3 + 4 + 5,
101 intelnops + 1 + 2 + 3 + 4 + 5 + 6,
102 intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
103 intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
108 static const unsigned char k8nops[] =
120 static const unsigned char * const k8_nops[ASM_NOP_MAX+2] =
127 k8nops + 1 + 2 + 3 + 4,
128 k8nops + 1 + 2 + 3 + 4 + 5,
129 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
130 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
131 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
135 #if defined(K7_NOP1) && !defined(CONFIG_X86_64)
136 static const unsigned char k7nops[] =
148 static const unsigned char * const k7_nops[ASM_NOP_MAX+2] =
155 k7nops + 1 + 2 + 3 + 4,
156 k7nops + 1 + 2 + 3 + 4 + 5,
157 k7nops + 1 + 2 + 3 + 4 + 5 + 6,
158 k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
159 k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
164 static const unsigned char p6nops[] =
176 static const unsigned char * const p6_nops[ASM_NOP_MAX+2] =
183 p6nops + 1 + 2 + 3 + 4,
184 p6nops + 1 + 2 + 3 + 4 + 5,
185 p6nops + 1 + 2 + 3 + 4 + 5 + 6,
186 p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
187 p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
191 /* Initialize these to a safe default */
193 const unsigned char * const *ideal_nops = p6_nops;
195 const unsigned char * const *ideal_nops = intel_nops;
198 void __init arch_init_ideal_nops(void)
200 switch (boot_cpu_data.x86_vendor) {
201 case X86_VENDOR_INTEL:
203 * Due to a decoder implementation quirk, some
204 * specific Intel CPUs actually perform better with
205 * the "k8_nops" than with the SDM-recommended NOPs.
207 if (boot_cpu_data.x86 == 6 &&
208 boot_cpu_data.x86_model >= 0x0f &&
209 boot_cpu_data.x86_model != 0x1c &&
210 boot_cpu_data.x86_model != 0x26 &&
211 boot_cpu_data.x86_model != 0x27 &&
212 boot_cpu_data.x86_model < 0x30) {
213 ideal_nops = k8_nops;
214 } else if (boot_cpu_has(X86_FEATURE_NOPL)) {
215 ideal_nops = p6_nops;
218 ideal_nops = k8_nops;
220 ideal_nops = intel_nops;
226 if (boot_cpu_data.x86 > 0xf) {
227 ideal_nops = p6_nops;
235 ideal_nops = k8_nops;
237 if (boot_cpu_has(X86_FEATURE_K8))
238 ideal_nops = k8_nops;
239 else if (boot_cpu_has(X86_FEATURE_K7))
240 ideal_nops = k7_nops;
242 ideal_nops = intel_nops;
247 /* Use this to add nops to a buffer, then text_poke the whole buffer. */
248 static void __init_or_module add_nops(void *insns, unsigned int len)
251 unsigned int noplen = len;
252 if (noplen > ASM_NOP_MAX)
253 noplen = ASM_NOP_MAX;
254 memcpy(insns, ideal_nops[noplen], noplen);
260 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
261 extern s32 __smp_locks[], __smp_locks_end[];
262 void *text_poke_early(void *addr, const void *opcode, size_t len);
265 * Are we looking at a near JMP with a 1 or 4-byte displacement.
267 static inline bool is_jmp(const u8 opcode)
269 return opcode == 0xeb || opcode == 0xe9;
272 static void __init_or_module
273 recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insnbuf)
275 u8 *next_rip, *tgt_rip;
279 if (a->replacementlen != 5)
282 o_dspl = *(s32 *)(insnbuf + 1);
284 /* next_rip of the replacement JMP */
285 next_rip = repl_insn + a->replacementlen;
286 /* target rip of the replacement JMP */
287 tgt_rip = next_rip + o_dspl;
288 n_dspl = tgt_rip - orig_insn;
290 DPRINTK("target RIP: %p, new_displ: 0x%x", tgt_rip, n_dspl);
292 if (tgt_rip - orig_insn >= 0) {
293 if (n_dspl - 2 <= 127)
297 /* negative offset */
299 if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
309 insnbuf[1] = (s8)n_dspl;
310 add_nops(insnbuf + 2, 3);
319 *(s32 *)&insnbuf[1] = n_dspl;
325 DPRINTK("final displ: 0x%08x, JMP 0x%lx",
326 n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
330 * "noinline" to cause control flow change and thus invalidate I$ and
331 * cause refetch after modification.
333 static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 *instr)
338 for (i = 0; i < a->padlen; i++) {
339 if (instr[i] != 0x90)
343 local_irq_save(flags);
344 add_nops(instr + (a->instrlen - a->padlen), a->padlen);
345 local_irq_restore(flags);
347 DUMP_BYTES(instr, a->instrlen, "%p: [%d:%d) optimized NOPs: ",
348 instr, a->instrlen - a->padlen, a->padlen);
352 * Replace instructions with better alternatives for this CPU type. This runs
353 * before SMP is initialized to avoid SMP problems with self modifying code.
354 * This implies that asymmetric systems where APs have less capabilities than
355 * the boot processor are not handled. Tough. Make sure you disable such
358 * Marked "noinline" to cause control flow change and thus insn cache
359 * to refetch changed I$ lines.
361 void __init_or_module noinline apply_alternatives(struct alt_instr *start,
362 struct alt_instr *end)
365 u8 *instr, *replacement;
366 u8 insnbuf[MAX_PATCH_LEN];
368 DPRINTK("alt table %p -> %p", start, end);
370 * The scan order should be from start to end. A later scanned
371 * alternative code can overwrite previously scanned alternative code.
372 * Some kernel functions (e.g. memcpy, memset, etc) use this order to
375 * So be careful if you want to change the scan order to any other
378 for (a = start; a < end; a++) {
381 instr = (u8 *)&a->instr_offset + a->instr_offset;
382 replacement = (u8 *)&a->repl_offset + a->repl_offset;
383 BUG_ON(a->instrlen > sizeof(insnbuf));
384 BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
385 if (!boot_cpu_has(a->cpuid)) {
387 optimize_nops(a, instr);
392 DPRINTK("feat: %d*32+%d, old: (%p, len: %d), repl: (%p, len: %d), pad: %d",
396 replacement, a->replacementlen, a->padlen);
398 DUMP_BYTES(instr, a->instrlen, "%p: old_insn: ", instr);
399 DUMP_BYTES(replacement, a->replacementlen, "%p: rpl_insn: ", replacement);
401 memcpy(insnbuf, replacement, a->replacementlen);
402 insnbuf_sz = a->replacementlen;
405 * 0xe8 is a relative jump; fix the offset.
407 * Instruction length is checked before the opcode to avoid
408 * accessing uninitialized bytes for zero-length replacements.
410 if (a->replacementlen == 5 && *insnbuf == 0xe8) {
411 *(s32 *)(insnbuf + 1) += replacement - instr;
412 DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
413 *(s32 *)(insnbuf + 1),
414 (unsigned long)instr + *(s32 *)(insnbuf + 1) + 5);
417 if (a->replacementlen && is_jmp(replacement[0]))
418 recompute_jump(a, instr, replacement, insnbuf);
420 if (a->instrlen > a->replacementlen) {
421 add_nops(insnbuf + a->replacementlen,
422 a->instrlen - a->replacementlen);
423 insnbuf_sz += a->instrlen - a->replacementlen;
425 DUMP_BYTES(insnbuf, insnbuf_sz, "%p: final_insn: ", instr);
427 text_poke_early(instr, insnbuf, insnbuf_sz);
432 static void alternatives_smp_lock(const s32 *start, const s32 *end,
433 u8 *text, u8 *text_end)
437 mutex_lock(&text_mutex);
438 for (poff = start; poff < end; poff++) {
439 u8 *ptr = (u8 *)poff + *poff;
441 if (!*poff || ptr < text || ptr >= text_end)
443 /* turn DS segment override prefix into lock prefix */
445 text_poke(ptr, ((unsigned char []){0xf0}), 1);
447 mutex_unlock(&text_mutex);
450 static void alternatives_smp_unlock(const s32 *start, const s32 *end,
451 u8 *text, u8 *text_end)
455 mutex_lock(&text_mutex);
456 for (poff = start; poff < end; poff++) {
457 u8 *ptr = (u8 *)poff + *poff;
459 if (!*poff || ptr < text || ptr >= text_end)
461 /* turn lock prefix into DS segment override prefix */
463 text_poke(ptr, ((unsigned char []){0x3E}), 1);
465 mutex_unlock(&text_mutex);
468 struct smp_alt_module {
469 /* what is this ??? */
473 /* ptrs to lock prefixes */
475 const s32 *locks_end;
477 /* .text segment, needed to avoid patching init code ;) */
481 struct list_head next;
483 static LIST_HEAD(smp_alt_modules);
484 static DEFINE_MUTEX(smp_alt);
485 static bool uniproc_patched = false; /* protected by smp_alt */
487 void __init_or_module alternatives_smp_module_add(struct module *mod,
489 void *locks, void *locks_end,
490 void *text, void *text_end)
492 struct smp_alt_module *smp;
494 mutex_lock(&smp_alt);
495 if (!uniproc_patched)
498 if (num_possible_cpus() == 1)
499 /* Don't bother remembering, we'll never have to undo it. */
502 smp = kzalloc(sizeof(*smp), GFP_KERNEL);
504 /* we'll run the (safe but slow) SMP code then ... */
510 smp->locks_end = locks_end;
512 smp->text_end = text_end;
513 DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
514 smp->locks, smp->locks_end,
515 smp->text, smp->text_end, smp->name);
517 list_add_tail(&smp->next, &smp_alt_modules);
519 alternatives_smp_unlock(locks, locks_end, text, text_end);
521 mutex_unlock(&smp_alt);
524 void __init_or_module alternatives_smp_module_del(struct module *mod)
526 struct smp_alt_module *item;
528 mutex_lock(&smp_alt);
529 list_for_each_entry(item, &smp_alt_modules, next) {
530 if (mod != item->mod)
532 list_del(&item->next);
536 mutex_unlock(&smp_alt);
539 void alternatives_enable_smp(void)
541 struct smp_alt_module *mod;
543 /* Why bother if there are no other CPUs? */
544 BUG_ON(num_possible_cpus() == 1);
546 mutex_lock(&smp_alt);
548 if (uniproc_patched) {
549 pr_info("switching to SMP code\n");
550 BUG_ON(num_online_cpus() != 1);
551 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
552 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
553 list_for_each_entry(mod, &smp_alt_modules, next)
554 alternatives_smp_lock(mod->locks, mod->locks_end,
555 mod->text, mod->text_end);
556 uniproc_patched = false;
558 mutex_unlock(&smp_alt);
561 /* Return 1 if the address range is reserved for smp-alternatives */
562 int alternatives_text_reserved(void *start, void *end)
564 struct smp_alt_module *mod;
566 u8 *text_start = start;
569 list_for_each_entry(mod, &smp_alt_modules, next) {
570 if (mod->text > text_end || mod->text_end < text_start)
572 for (poff = mod->locks; poff < mod->locks_end; poff++) {
573 const u8 *ptr = (const u8 *)poff + *poff;
575 if (text_start <= ptr && text_end > ptr)
582 #endif /* CONFIG_SMP */
584 #ifdef CONFIG_PARAVIRT
585 void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
586 struct paravirt_patch_site *end)
588 struct paravirt_patch_site *p;
589 char insnbuf[MAX_PATCH_LEN];
591 for (p = start; p < end; p++) {
594 BUG_ON(p->len > MAX_PATCH_LEN);
595 /* prep the buffer with the original instructions */
596 memcpy(insnbuf, p->instr, p->len);
597 used = pv_init_ops.patch(p->instrtype, p->clobbers, insnbuf,
598 (unsigned long)p->instr, p->len);
600 BUG_ON(used > p->len);
602 /* Pad the rest with nops */
603 add_nops(insnbuf + used, p->len - used);
604 text_poke_early(p->instr, insnbuf, p->len);
607 extern struct paravirt_patch_site __start_parainstructions[],
608 __stop_parainstructions[];
609 #endif /* CONFIG_PARAVIRT */
611 void __init alternative_instructions(void)
613 /* The patching is not fully atomic, so try to avoid local interruptions
614 that might execute the to be patched code.
615 Other CPUs are not running. */
619 * Don't stop machine check exceptions while patching.
620 * MCEs only happen when something got corrupted and in this
621 * case we must do something about the corruption.
622 * Ignoring it is worse than a unlikely patching race.
623 * Also machine checks tend to be broadcast and if one CPU
624 * goes into machine check the others follow quickly, so we don't
625 * expect a machine check to cause undue problems during to code
629 apply_alternatives(__alt_instructions, __alt_instructions_end);
632 /* Patch to UP if other cpus not imminent. */
633 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
634 uniproc_patched = true;
635 alternatives_smp_module_add(NULL, "core kernel",
636 __smp_locks, __smp_locks_end,
640 if (!uniproc_patched || num_possible_cpus() == 1)
641 free_init_pages("SMP alternatives",
642 (unsigned long)__smp_locks,
643 (unsigned long)__smp_locks_end);
646 apply_paravirt(__parainstructions, __parainstructions_end);
649 alternatives_patched = 1;
653 * text_poke_early - Update instructions on a live kernel at boot time
654 * @addr: address to modify
655 * @opcode: source of the copy
656 * @len: length to copy
658 * When you use this code to patch more than one byte of an instruction
659 * you need to make sure that other CPUs cannot execute this code in parallel.
660 * Also no thread must be currently preempted in the middle of these
661 * instructions. And on the local CPU you need to be protected again NMI or MCE
662 * handlers seeing an inconsistent instruction while you patch.
664 void *__init_or_module text_poke_early(void *addr, const void *opcode,
668 local_irq_save(flags);
669 memcpy(addr, opcode, len);
670 local_irq_restore(flags);
671 /* Could also do a CLFLUSH here to speed up CPU recovery; but
672 that causes hangs on some VIA CPUs. */
677 * text_poke - Update instructions on a live kernel
678 * @addr: address to modify
679 * @opcode: source of the copy
680 * @len: length to copy
682 * Only atomic text poke/set should be allowed when not doing early patching.
683 * It means the size must be writable atomically and the address must be aligned
684 * in a way that permits an atomic write. It also makes sure we fit on a single
687 * Note: Must be called under text_mutex.
689 void *text_poke(void *addr, const void *opcode, size_t len)
693 struct page *pages[2];
696 if (!core_kernel_text((unsigned long)addr)) {
697 pages[0] = vmalloc_to_page(addr);
698 pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
700 pages[0] = virt_to_page(addr);
701 WARN_ON(!PageReserved(pages[0]));
702 pages[1] = virt_to_page(addr + PAGE_SIZE);
705 local_irq_save(flags);
706 set_fixmap(FIX_TEXT_POKE0, page_to_phys(pages[0]));
708 set_fixmap(FIX_TEXT_POKE1, page_to_phys(pages[1]));
709 vaddr = (char *)fix_to_virt(FIX_TEXT_POKE0);
710 memcpy(&vaddr[(unsigned long)addr & ~PAGE_MASK], opcode, len);
711 clear_fixmap(FIX_TEXT_POKE0);
713 clear_fixmap(FIX_TEXT_POKE1);
716 /* Could also do a CLFLUSH here to speed up CPU recovery; but
717 that causes hangs on some VIA CPUs. */
718 for (i = 0; i < len; i++)
719 BUG_ON(((char *)addr)[i] != ((char *)opcode)[i]);
720 local_irq_restore(flags);
724 static void do_sync_core(void *info)
729 static bool bp_patching_in_progress;
730 static void *bp_int3_handler, *bp_int3_addr;
732 int poke_int3_handler(struct pt_regs *regs)
735 * Having observed our INT3 instruction, we now must observe
736 * bp_patching_in_progress.
738 * in_progress = TRUE INT3
740 * write INT3 if (in_progress)
742 * Idem for bp_int3_handler.
746 if (likely(!bp_patching_in_progress))
749 if (user_mode(regs) || regs->ip != (unsigned long)bp_int3_addr)
752 /* set up the specified breakpoint handler */
753 regs->ip = (unsigned long) bp_int3_handler;
760 * text_poke_bp() -- update instructions on live kernel on SMP
761 * @addr: address to patch
762 * @opcode: opcode of new instruction
763 * @len: length to copy
764 * @handler: address to jump to when the temporary breakpoint is hit
766 * Modify multi-byte instruction by using int3 breakpoint on SMP.
767 * We completely avoid stop_machine() here, and achieve the
768 * synchronization using int3 breakpoint.
770 * The way it is done:
771 * - add a int3 trap to the address that will be patched
773 * - update all but the first byte of the patched range
775 * - replace the first byte (int3) by the first byte of
779 * Note: must be called under text_mutex.
781 void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
783 unsigned char int3 = 0xcc;
785 bp_int3_handler = handler;
786 bp_int3_addr = (u8 *)addr + sizeof(int3);
787 bp_patching_in_progress = true;
789 * Corresponding read barrier in int3 notifier for making sure the
790 * in_progress and handler are correctly ordered wrt. patching.
794 text_poke(addr, &int3, sizeof(int3));
796 on_each_cpu(do_sync_core, NULL, 1);
798 if (len - sizeof(int3) > 0) {
799 /* patch all but the first byte */
800 text_poke((char *)addr + sizeof(int3),
801 (const char *) opcode + sizeof(int3),
804 * According to Intel, this core syncing is very likely
805 * not necessary and we'd be safe even without it. But
806 * better safe than sorry (plus there's not only Intel).
808 on_each_cpu(do_sync_core, NULL, 1);
811 /* patch the first byte */
812 text_poke(addr, opcode, sizeof(int3));
814 on_each_cpu(do_sync_core, NULL, 1);
816 * sync_core() implies an smp_mb() and orders this store against
817 * the writing of the new instruction.
819 bp_patching_in_progress = false;