1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
4 #include <linux/module.h>
5 #include <linux/sched.h>
6 #include <linux/perf_event.h>
7 #include <linux/mutex.h>
8 #include <linux/list.h>
9 #include <linux/stringify.h>
10 #include <linux/highmem.h>
12 #include <linux/vmalloc.h>
13 #include <linux/memory.h>
14 #include <linux/stop_machine.h>
15 #include <linux/slab.h>
16 #include <linux/kdebug.h>
17 #include <linux/kprobes.h>
18 #include <linux/mmu_context.h>
19 #include <linux/bsearch.h>
20 #include <linux/sync_core.h>
21 #include <asm/text-patching.h>
22 #include <asm/alternative.h>
23 #include <asm/sections.h>
26 #include <asm/cacheflush.h>
27 #include <asm/tlbflush.h>
30 #include <asm/fixmap.h>
31 #include <asm/paravirt.h>
32 #include <asm/asm-prototypes.h>
34 int __read_mostly alternatives_patched;
36 EXPORT_SYMBOL_GPL(alternatives_patched);
38 #define MAX_PATCH_LEN (255-1)
40 static int __initdata_or_module debug_alternative;
42 static int __init debug_alt(char *str)
44 debug_alternative = 1;
47 __setup("debug-alternative", debug_alt);
49 static int noreplace_smp;
51 static int __init setup_noreplace_smp(char *str)
56 __setup("noreplace-smp", setup_noreplace_smp);
58 #define DPRINTK(fmt, args...) \
60 if (debug_alternative) \
61 printk(KERN_DEBUG pr_fmt(fmt) "\n", ##args); \
64 #define DUMP_BYTES(buf, len, fmt, args...) \
66 if (unlikely(debug_alternative)) { \
72 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
73 for (j = 0; j < (len) - 1; j++) \
74 printk(KERN_CONT "%02hhx ", buf[j]); \
75 printk(KERN_CONT "%02hhx\n", buf[j]); \
79 static const unsigned char x86nops[] =
91 const unsigned char * const x86_nops[ASM_NOP_MAX+1] =
98 x86nops + 1 + 2 + 3 + 4,
99 x86nops + 1 + 2 + 3 + 4 + 5,
100 x86nops + 1 + 2 + 3 + 4 + 5 + 6,
101 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
104 /* Use this to add nops to a buffer, then text_poke the whole buffer. */
105 static void __init_or_module add_nops(void *insns, unsigned int len)
108 unsigned int noplen = len;
109 if (noplen > ASM_NOP_MAX)
110 noplen = ASM_NOP_MAX;
111 memcpy(insns, x86_nops[noplen], noplen);
117 extern s32 __retpoline_sites[], __retpoline_sites_end[];
118 extern s32 __ibt_endbr_seal[], __ibt_endbr_seal_end[];
119 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
120 extern s32 __smp_locks[], __smp_locks_end[];
121 void text_poke_early(void *addr, const void *opcode, size_t len);
124 * Are we looking at a near JMP with a 1 or 4-byte displacement.
126 static inline bool is_jmp(const u8 opcode)
128 return opcode == 0xeb || opcode == 0xe9;
131 static void __init_or_module
132 recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insn_buff)
134 u8 *next_rip, *tgt_rip;
138 if (a->replacementlen != 5)
141 o_dspl = *(s32 *)(insn_buff + 1);
143 /* next_rip of the replacement JMP */
144 next_rip = repl_insn + a->replacementlen;
145 /* target rip of the replacement JMP */
146 tgt_rip = next_rip + o_dspl;
147 n_dspl = tgt_rip - orig_insn;
149 DPRINTK("target RIP: %px, new_displ: 0x%x", tgt_rip, n_dspl);
151 if (tgt_rip - orig_insn >= 0) {
152 if (n_dspl - 2 <= 127)
156 /* negative offset */
158 if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
168 insn_buff[1] = (s8)n_dspl;
169 add_nops(insn_buff + 2, 3);
178 *(s32 *)&insn_buff[1] = n_dspl;
184 DPRINTK("final displ: 0x%08x, JMP 0x%lx",
185 n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
189 * optimize_nops_range() - Optimize a sequence of single byte NOPs (0x90)
191 * @instr: instruction byte stream
192 * @instrlen: length of the above
193 * @off: offset within @instr where the first NOP has been detected
195 * Return: number of NOPs found (and replaced).
197 static __always_inline int optimize_nops_range(u8 *instr, u8 instrlen, int off)
202 while (i < instrlen) {
203 if (instr[i] != 0x90)
214 local_irq_save(flags);
215 add_nops(instr + off, nnops);
216 local_irq_restore(flags);
218 DUMP_BYTES(instr, instrlen, "%px: [%d:%d) optimized NOPs: ", instr, off, i);
224 * "noinline" to cause control flow change and thus invalidate I$ and
225 * cause refetch after modification.
227 static void __init_or_module noinline optimize_nops(u8 *instr, size_t len)
233 * Jump over the non-NOP insns and optimize single-byte NOPs into bigger
237 if (insn_decode_kernel(&insn, &instr[i]))
241 * See if this and any potentially following NOPs can be
244 if (insn.length == 1 && insn.opcode.bytes[0] == 0x90)
245 i += optimize_nops_range(instr, len, i);
255 * Replace instructions with better alternatives for this CPU type. This runs
256 * before SMP is initialized to avoid SMP problems with self modifying code.
257 * This implies that asymmetric systems where APs have less capabilities than
258 * the boot processor are not handled. Tough. Make sure you disable such
261 * Marked "noinline" to cause control flow change and thus insn cache
262 * to refetch changed I$ lines.
264 void __init_or_module noinline apply_alternatives(struct alt_instr *start,
265 struct alt_instr *end)
268 u8 *instr, *replacement;
269 u8 insn_buff[MAX_PATCH_LEN];
271 DPRINTK("alt table %px, -> %px", start, end);
273 * The scan order should be from start to end. A later scanned
274 * alternative code can overwrite previously scanned alternative code.
275 * Some kernel functions (e.g. memcpy, memset, etc) use this order to
278 * So be careful if you want to change the scan order to any other
281 for (a = start; a < end; a++) {
282 int insn_buff_sz = 0;
283 /* Mask away "NOT" flag bit for feature to test. */
284 u16 feature = a->cpuid & ~ALTINSTR_FLAG_INV;
286 instr = (u8 *)&a->instr_offset + a->instr_offset;
287 replacement = (u8 *)&a->repl_offset + a->repl_offset;
288 BUG_ON(a->instrlen > sizeof(insn_buff));
289 BUG_ON(feature >= (NCAPINTS + NBUGINTS) * 32);
293 * - feature is present
294 * - feature not present but ALTINSTR_FLAG_INV is set to mean,
295 * patch if feature is *NOT* present.
297 if (!boot_cpu_has(feature) == !(a->cpuid & ALTINSTR_FLAG_INV))
300 DPRINTK("feat: %s%d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d)",
301 (a->cpuid & ALTINSTR_FLAG_INV) ? "!" : "",
304 instr, instr, a->instrlen,
305 replacement, a->replacementlen);
307 DUMP_BYTES(instr, a->instrlen, "%px: old_insn: ", instr);
308 DUMP_BYTES(replacement, a->replacementlen, "%px: rpl_insn: ", replacement);
310 memcpy(insn_buff, replacement, a->replacementlen);
311 insn_buff_sz = a->replacementlen;
314 * 0xe8 is a relative jump; fix the offset.
316 * Instruction length is checked before the opcode to avoid
317 * accessing uninitialized bytes for zero-length replacements.
319 if (a->replacementlen == 5 && *insn_buff == 0xe8) {
320 *(s32 *)(insn_buff + 1) += replacement - instr;
321 DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
322 *(s32 *)(insn_buff + 1),
323 (unsigned long)instr + *(s32 *)(insn_buff + 1) + 5);
326 if (a->replacementlen && is_jmp(replacement[0]))
327 recompute_jump(a, instr, replacement, insn_buff);
329 for (; insn_buff_sz < a->instrlen; insn_buff_sz++)
330 insn_buff[insn_buff_sz] = 0x90;
332 DUMP_BYTES(insn_buff, insn_buff_sz, "%px: final_insn: ", instr);
334 text_poke_early(instr, insn_buff, insn_buff_sz);
337 optimize_nops(instr, a->instrlen);
341 #if defined(CONFIG_RETPOLINE) && defined(CONFIG_OBJTOOL)
346 static int emit_indirect(int op, int reg, u8 *bytes)
352 case CALL_INSN_OPCODE:
353 modrm = 0x10; /* Reg = 2; CALL r/m */
356 case JMP32_INSN_OPCODE:
357 modrm = 0x20; /* Reg = 4; JMP r/m */
366 bytes[i++] = 0x41; /* REX.B prefix */
370 modrm |= 0xc0; /* Mod = 3 */
373 bytes[i++] = 0xff; /* opcode */
380 * Rewrite the compiler generated retpoline thunk calls.
382 * For spectre_v2=off (!X86_FEATURE_RETPOLINE), rewrite them into immediate
383 * indirect instructions, avoiding the extra indirection.
385 * For example, convert:
387 * CALL __x86_indirect_thunk_\reg
393 * It also tries to inline spectre_v2=retpoline,lfence when size permits.
395 static int patch_retpoline(void *addr, struct insn *insn, u8 *bytes)
397 retpoline_thunk_t *target;
401 target = addr + insn->length + insn->immediate.value;
402 reg = target - __x86_indirect_thunk_array;
404 if (WARN_ON_ONCE(reg & ~0xf))
407 /* If anyone ever does: CALL/JMP *%rsp, we're in deep trouble. */
410 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) &&
411 !cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE))
414 op = insn->opcode.bytes[0];
419 * Jcc.d32 __x86_indirect_thunk_\reg
429 /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */
430 if (op == 0x0f && (insn->opcode.bytes[1] & 0xf0) == 0x80) {
431 cc = insn->opcode.bytes[1] & 0xf;
432 cc ^= 1; /* invert condition */
434 bytes[i++] = 0x70 + cc; /* Jcc.d8 */
435 bytes[i++] = insn->length - 2; /* sizeof(Jcc.d8) == 2 */
437 /* Continue as if: JMP.d32 __x86_indirect_thunk_\reg */
438 op = JMP32_INSN_OPCODE;
442 * For RETPOLINE_LFENCE: prepend the indirect CALL/JMP with an LFENCE.
444 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
447 bytes[i++] = 0xe8; /* LFENCE */
450 ret = emit_indirect(op, reg, bytes + i);
455 for (; i < insn->length;)
456 bytes[i++] = BYTES_NOP1;
462 * Generated by 'objtool --retpoline'.
464 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end)
468 for (s = start; s < end; s++) {
469 void *addr = (void *)s + *s;
475 ret = insn_decode_kernel(&insn, addr);
476 if (WARN_ON_ONCE(ret < 0))
479 op1 = insn.opcode.bytes[0];
480 op2 = insn.opcode.bytes[1];
483 case CALL_INSN_OPCODE:
484 case JMP32_INSN_OPCODE:
487 case 0x0f: /* escape */
488 if (op2 >= 0x80 && op2 <= 0x8f)
496 DPRINTK("retpoline at: %pS (%px) len: %d to: %pS",
497 addr, addr, insn.length,
498 addr + insn.length + insn.immediate.value);
500 len = patch_retpoline(addr, &insn, bytes);
501 if (len == insn.length) {
502 optimize_nops(bytes, len);
503 DUMP_BYTES(((u8*)addr), len, "%px: orig: ", addr);
504 DUMP_BYTES(((u8*)bytes), len, "%px: repl: ", addr);
505 text_poke_early(addr, bytes, len);
510 #else /* !CONFIG_RETPOLINE || !CONFIG_OBJTOOL */
512 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) { }
514 #endif /* CONFIG_RETPOLINE && CONFIG_OBJTOOL */
516 #ifdef CONFIG_X86_KERNEL_IBT
519 * Generated by: objtool --ibt
521 void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end)
525 for (s = start; s < end; s++) {
526 u32 endbr, poison = gen_endbr_poison();
527 void *addr = (void *)s + *s;
529 if (WARN_ON_ONCE(get_kernel_nofault(endbr, addr)))
532 if (WARN_ON_ONCE(!is_endbr(endbr)))
535 DPRINTK("ENDBR at: %pS (%px)", addr, addr);
538 * When we have IBT, the lack of ENDBR will trigger #CP
540 DUMP_BYTES(((u8*)addr), 4, "%px: orig: ", addr);
541 DUMP_BYTES(((u8*)&poison), 4, "%px: repl: ", addr);
542 text_poke_early(addr, &poison, 4);
548 void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end) { }
550 #endif /* CONFIG_X86_KERNEL_IBT */
553 static void alternatives_smp_lock(const s32 *start, const s32 *end,
554 u8 *text, u8 *text_end)
558 for (poff = start; poff < end; poff++) {
559 u8 *ptr = (u8 *)poff + *poff;
561 if (!*poff || ptr < text || ptr >= text_end)
563 /* turn DS segment override prefix into lock prefix */
565 text_poke(ptr, ((unsigned char []){0xf0}), 1);
569 static void alternatives_smp_unlock(const s32 *start, const s32 *end,
570 u8 *text, u8 *text_end)
574 for (poff = start; poff < end; poff++) {
575 u8 *ptr = (u8 *)poff + *poff;
577 if (!*poff || ptr < text || ptr >= text_end)
579 /* turn lock prefix into DS segment override prefix */
581 text_poke(ptr, ((unsigned char []){0x3E}), 1);
585 struct smp_alt_module {
586 /* what is this ??? */
590 /* ptrs to lock prefixes */
592 const s32 *locks_end;
594 /* .text segment, needed to avoid patching init code ;) */
598 struct list_head next;
600 static LIST_HEAD(smp_alt_modules);
601 static bool uniproc_patched = false; /* protected by text_mutex */
603 void __init_or_module alternatives_smp_module_add(struct module *mod,
605 void *locks, void *locks_end,
606 void *text, void *text_end)
608 struct smp_alt_module *smp;
610 mutex_lock(&text_mutex);
611 if (!uniproc_patched)
614 if (num_possible_cpus() == 1)
615 /* Don't bother remembering, we'll never have to undo it. */
618 smp = kzalloc(sizeof(*smp), GFP_KERNEL);
620 /* we'll run the (safe but slow) SMP code then ... */
626 smp->locks_end = locks_end;
628 smp->text_end = text_end;
629 DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
630 smp->locks, smp->locks_end,
631 smp->text, smp->text_end, smp->name);
633 list_add_tail(&smp->next, &smp_alt_modules);
635 alternatives_smp_unlock(locks, locks_end, text, text_end);
637 mutex_unlock(&text_mutex);
640 void __init_or_module alternatives_smp_module_del(struct module *mod)
642 struct smp_alt_module *item;
644 mutex_lock(&text_mutex);
645 list_for_each_entry(item, &smp_alt_modules, next) {
646 if (mod != item->mod)
648 list_del(&item->next);
652 mutex_unlock(&text_mutex);
655 void alternatives_enable_smp(void)
657 struct smp_alt_module *mod;
659 /* Why bother if there are no other CPUs? */
660 BUG_ON(num_possible_cpus() == 1);
662 mutex_lock(&text_mutex);
664 if (uniproc_patched) {
665 pr_info("switching to SMP code\n");
666 BUG_ON(num_online_cpus() != 1);
667 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
668 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
669 list_for_each_entry(mod, &smp_alt_modules, next)
670 alternatives_smp_lock(mod->locks, mod->locks_end,
671 mod->text, mod->text_end);
672 uniproc_patched = false;
674 mutex_unlock(&text_mutex);
678 * Return 1 if the address range is reserved for SMP-alternatives.
679 * Must hold text_mutex.
681 int alternatives_text_reserved(void *start, void *end)
683 struct smp_alt_module *mod;
685 u8 *text_start = start;
688 lockdep_assert_held(&text_mutex);
690 list_for_each_entry(mod, &smp_alt_modules, next) {
691 if (mod->text > text_end || mod->text_end < text_start)
693 for (poff = mod->locks; poff < mod->locks_end; poff++) {
694 const u8 *ptr = (const u8 *)poff + *poff;
696 if (text_start <= ptr && text_end > ptr)
703 #endif /* CONFIG_SMP */
705 #ifdef CONFIG_PARAVIRT
706 void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
707 struct paravirt_patch_site *end)
709 struct paravirt_patch_site *p;
710 char insn_buff[MAX_PATCH_LEN];
712 for (p = start; p < end; p++) {
715 BUG_ON(p->len > MAX_PATCH_LEN);
716 /* prep the buffer with the original instructions */
717 memcpy(insn_buff, p->instr, p->len);
718 used = paravirt_patch(p->type, insn_buff, (unsigned long)p->instr, p->len);
720 BUG_ON(used > p->len);
722 /* Pad the rest with nops */
723 add_nops(insn_buff + used, p->len - used);
724 text_poke_early(p->instr, insn_buff, p->len);
727 extern struct paravirt_patch_site __start_parainstructions[],
728 __stop_parainstructions[];
729 #endif /* CONFIG_PARAVIRT */
732 * Self-test for the INT3 based CALL emulation code.
734 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up
735 * properly and that there is a stack gap between the INT3 frame and the
736 * previous context. Without this gap doing a virtual PUSH on the interrupted
737 * stack would corrupt the INT3 IRET frame.
739 * See entry_{32,64}.S for more details.
743 * We define the int3_magic() function in assembly to control the calling
744 * convention such that we can 'call' it from assembly.
747 extern void int3_magic(unsigned int *ptr); /* defined in asm */
750 " .pushsection .init.text, \"ax\", @progbits\n"
751 " .type int3_magic, @function\n"
754 " movl $1, (%" _ASM_ARG1 ")\n"
756 " .size int3_magic, .-int3_magic\n"
760 extern void int3_selftest_ip(void); /* defined in asm below */
763 int3_exception_notify(struct notifier_block *self, unsigned long val, void *data)
765 unsigned long selftest = (unsigned long)&int3_selftest_ip;
766 struct die_args *args = data;
767 struct pt_regs *regs = args->regs;
769 OPTIMIZER_HIDE_VAR(selftest);
771 if (!regs || user_mode(regs))
777 if (regs->ip - INT3_INSN_SIZE != selftest)
780 int3_emulate_call(regs, (unsigned long)&int3_magic);
784 /* Must be noinline to ensure uniqueness of int3_selftest_ip. */
785 static noinline void __init int3_selftest(void)
787 static __initdata struct notifier_block int3_exception_nb = {
788 .notifier_call = int3_exception_notify,
789 .priority = INT_MAX-1, /* last */
791 unsigned int val = 0;
793 BUG_ON(register_die_notifier(&int3_exception_nb));
796 * Basically: int3_magic(&val); but really complicated :-)
798 * INT3 padded with NOP to CALL_INSN_SIZE. The int3_exception_nb
799 * notifier above will emulate CALL for us.
801 asm volatile ("int3_selftest_ip:\n\t"
803 " int3; nop; nop; nop; nop\n\t"
804 : ASM_CALL_CONSTRAINT
805 : __ASM_SEL_RAW(a, D) (&val)
810 unregister_die_notifier(&int3_exception_nb);
813 void __init alternative_instructions(void)
818 * The patching is not fully atomic, so try to avoid local
819 * interruptions that might execute the to be patched code.
820 * Other CPUs are not running.
825 * Don't stop machine check exceptions while patching.
826 * MCEs only happen when something got corrupted and in this
827 * case we must do something about the corruption.
828 * Ignoring it is worse than an unlikely patching race.
829 * Also machine checks tend to be broadcast and if one CPU
830 * goes into machine check the others follow quickly, so we don't
831 * expect a machine check to cause undue problems during to code
836 * Paravirt patching and alternative patching can be combined to
837 * replace a function call with a short direct code sequence (e.g.
838 * by setting a constant return value instead of doing that in an
839 * external function).
840 * In order to make this work the following sequence is required:
841 * 1. set (artificial) features depending on used paravirt
842 * functions which can later influence alternative patching
843 * 2. apply paravirt patching (generally replacing an indirect
844 * function call with a direct one)
845 * 3. apply alternative patching (e.g. replacing a direct function
846 * call with a custom code sequence)
847 * Doing paravirt patching after alternative patching would clobber
848 * the optimization of the custom code with a function call again.
853 * First patch paravirt functions, such that we overwrite the indirect
854 * call with the direct call.
856 apply_paravirt(__parainstructions, __parainstructions_end);
859 * Rewrite the retpolines, must be done before alternatives since
860 * those can rewrite the retpoline thunks.
862 apply_retpolines(__retpoline_sites, __retpoline_sites_end);
865 * Then patch alternatives, such that those paravirt calls that are in
866 * alternatives can be overwritten by their immediate fragments.
868 apply_alternatives(__alt_instructions, __alt_instructions_end);
870 apply_ibt_endbr(__ibt_endbr_seal, __ibt_endbr_seal_end);
873 /* Patch to UP if other cpus not imminent. */
874 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
875 uniproc_patched = true;
876 alternatives_smp_module_add(NULL, "core kernel",
877 __smp_locks, __smp_locks_end,
881 if (!uniproc_patched || num_possible_cpus() == 1) {
882 free_init_pages("SMP alternatives",
883 (unsigned long)__smp_locks,
884 (unsigned long)__smp_locks_end);
889 alternatives_patched = 1;
893 * text_poke_early - Update instructions on a live kernel at boot time
894 * @addr: address to modify
895 * @opcode: source of the copy
896 * @len: length to copy
898 * When you use this code to patch more than one byte of an instruction
899 * you need to make sure that other CPUs cannot execute this code in parallel.
900 * Also no thread must be currently preempted in the middle of these
901 * instructions. And on the local CPU you need to be protected against NMI or
902 * MCE handlers seeing an inconsistent instruction while you patch.
904 void __init_or_module text_poke_early(void *addr, const void *opcode,
909 if (boot_cpu_has(X86_FEATURE_NX) &&
910 is_module_text_address((unsigned long)addr)) {
912 * Modules text is marked initially as non-executable, so the
913 * code cannot be running and speculative code-fetches are
914 * prevented. Just change the code.
916 memcpy(addr, opcode, len);
918 local_irq_save(flags);
919 memcpy(addr, opcode, len);
920 local_irq_restore(flags);
924 * Could also do a CLFLUSH here to speed up CPU recovery; but
925 * that causes hangs on some VIA CPUs.
931 struct mm_struct *mm;
935 * Using a temporary mm allows to set temporary mappings that are not accessible
936 * by other CPUs. Such mappings are needed to perform sensitive memory writes
937 * that override the kernel memory protections (e.g., W^X), without exposing the
938 * temporary page-table mappings that are required for these write operations to
939 * other CPUs. Using a temporary mm also allows to avoid TLB shootdowns when the
940 * mapping is torn down.
942 * Context: The temporary mm needs to be used exclusively by a single core. To
943 * harden security IRQs must be disabled while the temporary mm is
944 * loaded, thereby preventing interrupt handler bugs from overriding
945 * the kernel memory protection.
947 static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm)
949 temp_mm_state_t temp_state;
951 lockdep_assert_irqs_disabled();
954 * Make sure not to be in TLB lazy mode, as otherwise we'll end up
955 * with a stale address space WITHOUT being in lazy mode after
956 * restoring the previous mm.
958 if (this_cpu_read(cpu_tlbstate_shared.is_lazy))
959 leave_mm(smp_processor_id());
961 temp_state.mm = this_cpu_read(cpu_tlbstate.loaded_mm);
962 switch_mm_irqs_off(NULL, mm, current);
965 * If breakpoints are enabled, disable them while the temporary mm is
966 * used. Userspace might set up watchpoints on addresses that are used
967 * in the temporary mm, which would lead to wrong signals being sent or
970 * Note that breakpoints are not disabled selectively, which also causes
971 * kernel breakpoints (e.g., perf's) to be disabled. This might be
972 * undesirable, but still seems reasonable as the code that runs in the
973 * temporary mm should be short.
975 if (hw_breakpoint_active())
976 hw_breakpoint_disable();
981 static inline void unuse_temporary_mm(temp_mm_state_t prev_state)
983 lockdep_assert_irqs_disabled();
984 switch_mm_irqs_off(NULL, prev_state.mm, current);
987 * Restore the breakpoints if they were disabled before the temporary mm
990 if (hw_breakpoint_active())
991 hw_breakpoint_restore();
994 __ro_after_init struct mm_struct *poking_mm;
995 __ro_after_init unsigned long poking_addr;
997 static void text_poke_memcpy(void *dst, const void *src, size_t len)
999 memcpy(dst, src, len);
1002 static void text_poke_memset(void *dst, const void *src, size_t len)
1004 int c = *(const int *)src;
1006 memset(dst, c, len);
1009 typedef void text_poke_f(void *dst, const void *src, size_t len);
1011 static void *__text_poke(text_poke_f func, void *addr, const void *src, size_t len)
1013 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE;
1014 struct page *pages[2] = {NULL};
1015 temp_mm_state_t prev;
1016 unsigned long flags;
1022 * While boot memory allocator is running we cannot use struct pages as
1023 * they are not yet initialized. There is no way to recover.
1025 BUG_ON(!after_bootmem);
1027 if (!core_kernel_text((unsigned long)addr)) {
1028 pages[0] = vmalloc_to_page(addr);
1029 if (cross_page_boundary)
1030 pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
1032 pages[0] = virt_to_page(addr);
1033 WARN_ON(!PageReserved(pages[0]));
1034 if (cross_page_boundary)
1035 pages[1] = virt_to_page(addr + PAGE_SIZE);
1038 * If something went wrong, crash and burn since recovery paths are not
1041 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1]));
1044 * Map the page without the global bit, as TLB flushing is done with
1045 * flush_tlb_mm_range(), which is intended for non-global PTEs.
1047 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL);
1050 * The lock is not really needed, but this allows to avoid open-coding.
1052 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
1055 * This must not fail; preallocated in poking_init().
1059 local_irq_save(flags);
1061 pte = mk_pte(pages[0], pgprot);
1062 set_pte_at(poking_mm, poking_addr, ptep, pte);
1064 if (cross_page_boundary) {
1065 pte = mk_pte(pages[1], pgprot);
1066 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
1070 * Loading the temporary mm behaves as a compiler barrier, which
1071 * guarantees that the PTE will be set at the time memcpy() is done.
1073 prev = use_temporary_mm(poking_mm);
1075 kasan_disable_current();
1076 func((u8 *)poking_addr + offset_in_page(addr), src, len);
1077 kasan_enable_current();
1080 * Ensure that the PTE is only cleared after the instructions of memcpy
1081 * were issued by using a compiler barrier.
1085 pte_clear(poking_mm, poking_addr, ptep);
1086 if (cross_page_boundary)
1087 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1);
1090 * Loading the previous page-table hierarchy requires a serializing
1091 * instruction that already allows the core to see the updated version.
1092 * Xen-PV is assumed to serialize execution in a similar manner.
1094 unuse_temporary_mm(prev);
1097 * Flushing the TLB might involve IPIs, which would require enabled
1098 * IRQs, but not if the mm is not used, as it is in this point.
1100 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr +
1101 (cross_page_boundary ? 2 : 1) * PAGE_SIZE,
1104 if (func == text_poke_memcpy) {
1106 * If the text does not match what we just wrote then something is
1107 * fundamentally screwy; there's nothing we can really do about that.
1109 BUG_ON(memcmp(addr, src, len));
1112 local_irq_restore(flags);
1113 pte_unmap_unlock(ptep, ptl);
1118 * text_poke - Update instructions on a live kernel
1119 * @addr: address to modify
1120 * @opcode: source of the copy
1121 * @len: length to copy
1123 * Only atomic text poke/set should be allowed when not doing early patching.
1124 * It means the size must be writable atomically and the address must be aligned
1125 * in a way that permits an atomic write. It also makes sure we fit on a single
1128 * Note that the caller must ensure that if the modified code is part of a
1129 * module, the module would not be removed during poking. This can be achieved
1130 * by registering a module notifier, and ordering module removal and patching
1133 void *text_poke(void *addr, const void *opcode, size_t len)
1135 lockdep_assert_held(&text_mutex);
1137 return __text_poke(text_poke_memcpy, addr, opcode, len);
1141 * text_poke_kgdb - Update instructions on a live kernel by kgdb
1142 * @addr: address to modify
1143 * @opcode: source of the copy
1144 * @len: length to copy
1146 * Only atomic text poke/set should be allowed when not doing early patching.
1147 * It means the size must be writable atomically and the address must be aligned
1148 * in a way that permits an atomic write. It also makes sure we fit on a single
1151 * Context: should only be used by kgdb, which ensures no other core is running,
1152 * despite the fact it does not hold the text_mutex.
1154 void *text_poke_kgdb(void *addr, const void *opcode, size_t len)
1156 return __text_poke(text_poke_memcpy, addr, opcode, len);
1160 * text_poke_copy - Copy instructions into (an unused part of) RX memory
1161 * @addr: address to modify
1162 * @opcode: source of the copy
1163 * @len: length to copy, could be more than 2x PAGE_SIZE
1165 * Not safe against concurrent execution; useful for JITs to dump
1166 * new code blocks into unused regions of RX memory. Can be used in
1167 * conjunction with synchronize_rcu_tasks() to wait for existing
1168 * execution to quiesce after having made sure no existing functions
1169 * pointers are live.
1171 void *text_poke_copy(void *addr, const void *opcode, size_t len)
1173 unsigned long start = (unsigned long)addr;
1176 if (WARN_ON_ONCE(core_kernel_text(start)))
1179 mutex_lock(&text_mutex);
1180 while (patched < len) {
1181 unsigned long ptr = start + patched;
1184 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched);
1186 __text_poke(text_poke_memcpy, (void *)ptr, opcode + patched, s);
1189 mutex_unlock(&text_mutex);
1194 * text_poke_set - memset into (an unused part of) RX memory
1195 * @addr: address to modify
1196 * @c: the byte to fill the area with
1197 * @len: length to copy, could be more than 2x PAGE_SIZE
1199 * This is useful to overwrite unused regions of RX memory with illegal
1202 void *text_poke_set(void *addr, int c, size_t len)
1204 unsigned long start = (unsigned long)addr;
1207 if (WARN_ON_ONCE(core_kernel_text(start)))
1210 mutex_lock(&text_mutex);
1211 while (patched < len) {
1212 unsigned long ptr = start + patched;
1215 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched);
1217 __text_poke(text_poke_memset, (void *)ptr, (void *)&c, s);
1220 mutex_unlock(&text_mutex);
1224 static void do_sync_core(void *info)
1229 void text_poke_sync(void)
1231 on_each_cpu(do_sync_core, NULL, 1);
1234 struct text_poke_loc {
1235 /* addr := _stext + rel_addr */
1240 const u8 text[POKE_MAX_OPCODE_SIZE];
1241 /* see text_poke_bp_batch() */
1245 struct bp_patching_desc {
1246 struct text_poke_loc *vec;
1251 static struct bp_patching_desc *bp_desc;
1253 static __always_inline
1254 struct bp_patching_desc *try_get_desc(struct bp_patching_desc **descp)
1256 /* rcu_dereference */
1257 struct bp_patching_desc *desc = __READ_ONCE(*descp);
1259 if (!desc || !arch_atomic_inc_not_zero(&desc->refs))
1265 static __always_inline void put_desc(struct bp_patching_desc *desc)
1267 smp_mb__before_atomic();
1268 arch_atomic_dec(&desc->refs);
1271 static __always_inline void *text_poke_addr(struct text_poke_loc *tp)
1273 return _stext + tp->rel_addr;
1276 static __always_inline int patch_cmp(const void *key, const void *elt)
1278 struct text_poke_loc *tp = (struct text_poke_loc *) elt;
1280 if (key < text_poke_addr(tp))
1282 if (key > text_poke_addr(tp))
1287 noinstr int poke_int3_handler(struct pt_regs *regs)
1289 struct bp_patching_desc *desc;
1290 struct text_poke_loc *tp;
1294 if (user_mode(regs))
1298 * Having observed our INT3 instruction, we now must observe
1301 * bp_desc = desc INT3
1303 * write INT3 if (desc)
1307 desc = try_get_desc(&bp_desc);
1312 * Discount the INT3. See text_poke_bp_batch().
1314 ip = (void *) regs->ip - INT3_INSN_SIZE;
1317 * Skip the binary search if there is a single member in the vector.
1319 if (unlikely(desc->nr_entries > 1)) {
1320 tp = __inline_bsearch(ip, desc->vec, desc->nr_entries,
1321 sizeof(struct text_poke_loc),
1327 if (text_poke_addr(tp) != ip)
1333 switch (tp->opcode) {
1334 case INT3_INSN_OPCODE:
1336 * Someone poked an explicit INT3, they'll want to handle it,
1341 case RET_INSN_OPCODE:
1342 int3_emulate_ret(regs);
1345 case CALL_INSN_OPCODE:
1346 int3_emulate_call(regs, (long)ip + tp->disp);
1349 case JMP32_INSN_OPCODE:
1350 case JMP8_INSN_OPCODE:
1351 int3_emulate_jmp(regs, (long)ip + tp->disp);
1365 #define TP_VEC_MAX (PAGE_SIZE / sizeof(struct text_poke_loc))
1366 static struct text_poke_loc tp_vec[TP_VEC_MAX];
1367 static int tp_vec_nr;
1370 * text_poke_bp_batch() -- update instructions on live kernel on SMP
1371 * @tp: vector of instructions to patch
1372 * @nr_entries: number of entries in the vector
1374 * Modify multi-byte instruction by using int3 breakpoint on SMP.
1375 * We completely avoid stop_machine() here, and achieve the
1376 * synchronization using int3 breakpoint.
1378 * The way it is done:
1379 * - For each entry in the vector:
1380 * - add a int3 trap to the address that will be patched
1382 * - For each entry in the vector:
1383 * - update all but the first byte of the patched range
1385 * - For each entry in the vector:
1386 * - replace the first byte (int3) by the first byte of
1390 static void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries)
1392 struct bp_patching_desc desc = {
1394 .nr_entries = nr_entries,
1395 .refs = ATOMIC_INIT(1),
1397 unsigned char int3 = INT3_INSN_OPCODE;
1401 lockdep_assert_held(&text_mutex);
1403 smp_store_release(&bp_desc, &desc); /* rcu_assign_pointer */
1406 * Corresponding read barrier in int3 notifier for making sure the
1407 * nr_entries and handler are correctly ordered wrt. patching.
1412 * First step: add a int3 trap to the address that will be patched.
1414 for (i = 0; i < nr_entries; i++) {
1415 tp[i].old = *(u8 *)text_poke_addr(&tp[i]);
1416 text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE);
1422 * Second step: update all but the first byte of the patched range.
1424 for (do_sync = 0, i = 0; i < nr_entries; i++) {
1425 u8 old[POKE_MAX_OPCODE_SIZE] = { tp[i].old, };
1426 int len = tp[i].len;
1428 if (len - INT3_INSN_SIZE > 0) {
1429 memcpy(old + INT3_INSN_SIZE,
1430 text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
1431 len - INT3_INSN_SIZE);
1432 text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
1433 (const char *)tp[i].text + INT3_INSN_SIZE,
1434 len - INT3_INSN_SIZE);
1439 * Emit a perf event to record the text poke, primarily to
1440 * support Intel PT decoding which must walk the executable code
1441 * to reconstruct the trace. The flow up to here is:
1444 * - write instruction tail
1445 * At this point the actual control flow will be through the
1446 * INT3 and handler and not hit the old or new instruction.
1447 * Intel PT outputs FUP/TIP packets for the INT3, so the flow
1448 * can still be decoded. Subsequently:
1449 * - emit RECORD_TEXT_POKE with the new instruction
1451 * - write first byte
1453 * So before the text poke event timestamp, the decoder will see
1454 * either the old instruction flow or FUP/TIP of INT3. After the
1455 * text poke event timestamp, the decoder will see either the
1456 * new instruction flow or FUP/TIP of INT3. Thus decoders can
1457 * use the timestamp as the point at which to modify the
1459 * The old instruction is recorded so that the event can be
1460 * processed forwards or backwards.
1462 perf_event_text_poke(text_poke_addr(&tp[i]), old, len,
1468 * According to Intel, this core syncing is very likely
1469 * not necessary and we'd be safe even without it. But
1470 * better safe than sorry (plus there's not only Intel).
1476 * Third step: replace the first byte (int3) by the first byte of
1479 for (do_sync = 0, i = 0; i < nr_entries; i++) {
1480 if (tp[i].text[0] == INT3_INSN_OPCODE)
1483 text_poke(text_poke_addr(&tp[i]), tp[i].text, INT3_INSN_SIZE);
1491 * Remove and synchronize_rcu(), except we have a very primitive
1492 * refcount based completion.
1494 WRITE_ONCE(bp_desc, NULL); /* RCU_INIT_POINTER */
1495 if (!atomic_dec_and_test(&desc.refs))
1496 atomic_cond_read_acquire(&desc.refs, !VAL);
1499 static void text_poke_loc_init(struct text_poke_loc *tp, void *addr,
1500 const void *opcode, size_t len, const void *emulate)
1505 memcpy((void *)tp->text, opcode, len);
1509 ret = insn_decode_kernel(&insn, emulate);
1512 tp->rel_addr = addr - (void *)_stext;
1514 tp->opcode = insn.opcode.bytes[0];
1516 switch (tp->opcode) {
1517 case RET_INSN_OPCODE:
1518 case JMP32_INSN_OPCODE:
1519 case JMP8_INSN_OPCODE:
1521 * Control flow instructions without implied execution of the
1522 * next instruction can be padded with INT3.
1524 for (i = insn.length; i < len; i++)
1525 BUG_ON(tp->text[i] != INT3_INSN_OPCODE);
1529 BUG_ON(len != insn.length);
1533 switch (tp->opcode) {
1534 case INT3_INSN_OPCODE:
1535 case RET_INSN_OPCODE:
1538 case CALL_INSN_OPCODE:
1539 case JMP32_INSN_OPCODE:
1540 case JMP8_INSN_OPCODE:
1541 tp->disp = insn.immediate.value;
1544 default: /* assume NOP */
1546 case 2: /* NOP2 -- emulate as JMP8+0 */
1547 BUG_ON(memcmp(emulate, x86_nops[len], len));
1548 tp->opcode = JMP8_INSN_OPCODE;
1552 case 5: /* NOP5 -- emulate as JMP32+0 */
1553 BUG_ON(memcmp(emulate, x86_nops[len], len));
1554 tp->opcode = JMP32_INSN_OPCODE;
1558 default: /* unknown instruction */
1566 * We hard rely on the tp_vec being ordered; ensure this is so by flushing
1569 static bool tp_order_fail(void *addr)
1571 struct text_poke_loc *tp;
1576 if (!addr) /* force */
1579 tp = &tp_vec[tp_vec_nr - 1];
1580 if ((unsigned long)text_poke_addr(tp) > (unsigned long)addr)
1586 static void text_poke_flush(void *addr)
1588 if (tp_vec_nr == TP_VEC_MAX || tp_order_fail(addr)) {
1589 text_poke_bp_batch(tp_vec, tp_vec_nr);
1594 void text_poke_finish(void)
1596 text_poke_flush(NULL);
1599 void __ref text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate)
1601 struct text_poke_loc *tp;
1603 if (unlikely(system_state == SYSTEM_BOOTING)) {
1604 text_poke_early(addr, opcode, len);
1608 text_poke_flush(addr);
1610 tp = &tp_vec[tp_vec_nr++];
1611 text_poke_loc_init(tp, addr, opcode, len, emulate);
1615 * text_poke_bp() -- update instructions on live kernel on SMP
1616 * @addr: address to patch
1617 * @opcode: opcode of new instruction
1618 * @len: length to copy
1619 * @emulate: instruction to be emulated
1621 * Update a single instruction with the vector in the stack, avoiding
1622 * dynamically allocated memory. This function should be used when it is
1623 * not possible to allocate memory.
1625 void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate)
1627 struct text_poke_loc tp;
1629 if (unlikely(system_state == SYSTEM_BOOTING)) {
1630 text_poke_early(addr, opcode, len);
1634 text_poke_loc_init(&tp, addr, opcode, len, emulate);
1635 text_poke_bp_batch(&tp, 1);