1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
6 #include <linux/sched.h>
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
12 #include <asm/invpcid.h>
14 #include <asm/processor-flags.h>
17 * The x86 feature is called PCID (Process Context IDentifier). It is similar
18 * to what is traditionally called ASID on the RISC processors.
20 * We don't use the traditional ASID implementation, where each process/mm gets
21 * its own ASID and flush/restart when we run out of ASID space.
23 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
24 * that came by on this CPU, allowing cheaper switch_mm between processes on
27 * We end up with different spaces for different things. To avoid confusion we
28 * use different names for each of them:
30 * ASID - [0, TLB_NR_DYN_ASIDS-1]
31 * the canonical identifier for an mm
33 * kPCID - [1, TLB_NR_DYN_ASIDS]
34 * the value we write into the PCID part of CR3; corresponds to the
35 * ASID+1, because PCID 0 is special.
37 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
38 * for KPTI each mm has two address spaces and thus needs two
39 * PCID values, but we can still do with a single ASID denomination
40 * for each mm. Corresponds to kPCID + 2048.
44 /* There are 12 bits of space for ASIDS in CR3 */
45 #define CR3_HW_ASID_BITS 12
48 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
49 * user/kernel switches
51 #ifdef CONFIG_PAGE_TABLE_ISOLATION
52 # define PTI_CONSUMED_PCID_BITS 1
54 # define PTI_CONSUMED_PCID_BITS 0
57 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
60 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
61 * for them being zero-based. Another -1 is because PCID 0 is reserved for
62 * use by non-PCID-aware users.
64 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
67 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
70 #define TLB_NR_DYN_ASIDS 6
73 * Given @asid, compute kPCID
75 static inline u16 kern_pcid(u16 asid)
77 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
79 #ifdef CONFIG_PAGE_TABLE_ISOLATION
81 * Make sure that the dynamic ASID space does not confict with the
82 * bit we are using to switch between user and kernel ASIDs.
84 BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
87 * The ASID being passed in here should have respected the
88 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
90 VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
93 * The dynamically-assigned ASIDs that get passed in are small
94 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
95 * so do not bother to clear it.
97 * If PCID is on, ASID-aware code paths put the ASID+1 into the
98 * PCID bits. This serves two purposes. It prevents a nasty
99 * situation in which PCID-unaware code saves CR3, loads some other
100 * value (with PCID == 0), and then restores CR3, thus corrupting
101 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
102 * that any bugs involving loading a PCID-enabled CR3 with
103 * CR4.PCIDE off will trigger deterministically.
109 * Given @asid, compute uPCID
111 static inline u16 user_pcid(u16 asid)
113 u16 ret = kern_pcid(asid);
114 #ifdef CONFIG_PAGE_TABLE_ISOLATION
115 ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
121 static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
123 if (static_cpu_has(X86_FEATURE_PCID)) {
124 return __sme_pa(pgd) | kern_pcid(asid);
126 VM_WARN_ON_ONCE(asid != 0);
127 return __sme_pa(pgd);
131 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
133 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
135 * Use boot_cpu_has() instead of this_cpu_has() as this function
136 * might be called during early boot. This should work even after
137 * boot because all CPU's the have same capabilities:
139 VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
140 return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
143 #ifdef CONFIG_PARAVIRT
144 #include <asm/paravirt.h>
146 #define __flush_tlb() __native_flush_tlb()
147 #define __flush_tlb_global() __native_flush_tlb_global()
148 #define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
151 static inline bool tlb_defer_switch_to_init_mm(void)
154 * If we have PCID, then switching to init_mm is reasonably
155 * fast. If we don't have PCID, then switching to init_mm is
156 * quite slow, so we try to defer it in the hopes that we can
157 * avoid it entirely. The latter approach runs the risk of
158 * receiving otherwise unnecessary IPIs.
160 * This choice is just a heuristic. The tlb code can handle this
161 * function returning true or false regardless of whether we have
164 return !static_cpu_has(X86_FEATURE_PCID);
174 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
175 * are on. This means that it may not match current->active_mm,
176 * which will contain the previous user mm when we're in lazy TLB
177 * mode even if we've already switched back to swapper_pg_dir.
179 * During switch_mm_irqs_off(), loaded_mm will be set to
180 * LOADED_MM_SWITCHING during the brief interrupts-off window
181 * when CR3 and loaded_mm would otherwise be inconsistent. This
182 * is for nmi_uaccess_okay()'s benefit.
184 struct mm_struct *loaded_mm;
186 #define LOADED_MM_SWITCHING ((struct mm_struct *)1)
188 /* Last user mm for optimizing IBPB */
190 struct mm_struct *last_user_mm;
191 unsigned long last_user_mm_ibpb;
198 * We can be in one of several states:
200 * - Actively using an mm. Our CPU's bit will be set in
201 * mm_cpumask(loaded_mm) and is_lazy == false;
203 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
204 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
206 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
207 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
208 * We're heuristically guessing that the CR3 load we
209 * skipped more than makes up for the overhead added by
215 * If set we changed the page tables in such a way that we
216 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
217 * This tells us to go invalidate all the non-loaded ctxs[]
218 * on the next context switch.
220 * The current ctx was kept up-to-date as it ran and does not
221 * need to be invalidated.
223 bool invalidate_other;
226 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
227 * the corresponding user PCID needs a flush next time we
228 * switch to it; see SWITCH_TO_USER_CR3.
230 unsigned short user_pcid_flush_mask;
233 * Access to this CR4 shadow and to H/W CR4 is protected by
234 * disabling interrupts when modifying either one.
239 * This is a list of all contexts that might exist in the TLB.
240 * There is one per ASID that we use, and the ASID (what the
241 * CPU calls PCID) is the index into ctxts.
243 * For each context, ctx_id indicates which mm the TLB's user
244 * entries came from. As an invariant, the TLB will never
245 * contain entries that are out-of-date as when that mm reached
246 * the tlb_gen in the list.
248 * To be clear, this means that it's legal for the TLB code to
249 * flush the TLB without updating tlb_gen. This can happen
250 * (for now, at least) due to paravirt remote flushes.
252 * NB: context 0 is a bit special, since it's also used by
253 * various bits of init code. This is fine -- code that
254 * isn't aware of PCID will end up harmlessly flushing
257 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
259 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
262 * Blindly accessing user memory from NMI context can be dangerous
263 * if we're in the middle of switching the current user task or
264 * switching the loaded mm. It can also be dangerous if we
265 * interrupted some kernel code that was temporarily using a
268 static inline bool nmi_uaccess_okay(void)
270 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
271 struct mm_struct *current_mm = current->mm;
273 VM_WARN_ON_ONCE(!loaded_mm);
276 * The condition we want to check is
277 * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though,
278 * if we're running in a VM with shadow paging, and nmi_uaccess_okay()
279 * is supposed to be reasonably fast.
281 * Instead, we check the almost equivalent but somewhat conservative
282 * condition below, and we rely on the fact that switch_mm_irqs_off()
283 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
285 if (loaded_mm != current_mm)
288 VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
293 /* Initialize cr4 shadow for this CPU. */
294 static inline void cr4_init_shadow(void)
296 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
299 /* Set in this cpu's CR4. */
300 static inline void cr4_set_bits(unsigned long mask)
304 cr4 = this_cpu_read(cpu_tlbstate.cr4);
305 if ((cr4 | mask) != cr4) {
307 this_cpu_write(cpu_tlbstate.cr4, cr4);
312 /* Clear in this cpu's CR4. */
313 static inline void cr4_clear_bits(unsigned long mask)
317 cr4 = this_cpu_read(cpu_tlbstate.cr4);
318 if ((cr4 & ~mask) != cr4) {
320 this_cpu_write(cpu_tlbstate.cr4, cr4);
325 static inline void cr4_toggle_bits(unsigned long mask)
329 cr4 = this_cpu_read(cpu_tlbstate.cr4);
331 this_cpu_write(cpu_tlbstate.cr4, cr4);
335 /* Read the CR4 shadow. */
336 static inline unsigned long cr4_read_shadow(void)
338 return this_cpu_read(cpu_tlbstate.cr4);
342 * Mark all other ASIDs as invalid, preserves the current.
344 static inline void invalidate_other_asid(void)
346 this_cpu_write(cpu_tlbstate.invalidate_other, true);
350 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
351 * enable and PPro Global page enable), so that any CPU's that boot
352 * up after us can get the correct flags. This should only be used
353 * during boot on the boot cpu.
355 extern unsigned long mmu_cr4_features;
356 extern u32 *trampoline_cr4_features;
358 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
360 mmu_cr4_features |= mask;
361 if (trampoline_cr4_features)
362 *trampoline_cr4_features = mmu_cr4_features;
366 extern void initialize_tlbstate_and_flush(void);
369 * Given an ASID, flush the corresponding user ASID. We can delay this
370 * until the next time we switch to it.
372 * See SWITCH_TO_USER_CR3.
374 static inline void invalidate_user_asid(u16 asid)
376 /* There is no user ASID if address space separation is off */
377 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
381 * We only have a single ASID if PCID is off and the CR3
382 * write will have flushed it.
384 if (!cpu_feature_enabled(X86_FEATURE_PCID))
387 if (!static_cpu_has(X86_FEATURE_PTI))
390 __set_bit(kern_pcid(asid),
391 (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
395 * flush the entire current user mapping
397 static inline void __native_flush_tlb(void)
400 * Preemption or interrupts must be disabled to protect the access
401 * to the per CPU variable and to prevent being preempted between
402 * read_cr3() and write_cr3().
404 WARN_ON_ONCE(preemptible());
406 invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
408 /* If current->mm == NULL then the read_cr3() "borrows" an mm */
409 native_write_cr3(__native_read_cr3());
415 static inline void __native_flush_tlb_global(void)
417 unsigned long cr4, flags;
419 if (static_cpu_has(X86_FEATURE_INVPCID)) {
421 * Using INVPCID is considerably faster than a pair of writes
422 * to CR4 sandwiched inside an IRQ flag save/restore.
424 * Note, this works with CR4.PCIDE=0 or 1.
431 * Read-modify-write to CR4 - protect it from preemption and
432 * from interrupts. (Use the raw variant because this code can
433 * be called from deep inside debugging code.)
435 raw_local_irq_save(flags);
437 cr4 = this_cpu_read(cpu_tlbstate.cr4);
439 native_write_cr4(cr4 ^ X86_CR4_PGE);
440 /* write old PGE again and flush TLBs */
441 native_write_cr4(cr4);
443 raw_local_irq_restore(flags);
447 * flush one page in the user mapping
449 static inline void __native_flush_tlb_one_user(unsigned long addr)
451 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
453 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
455 if (!static_cpu_has(X86_FEATURE_PTI))
459 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
460 * Just use invalidate_user_asid() in case we are called early.
462 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
463 invalidate_user_asid(loaded_mm_asid);
465 invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
471 static inline void __flush_tlb_all(void)
474 * This is to catch users with enabled preemption and the PGE feature
475 * and don't trigger the warning in __native_flush_tlb().
477 VM_WARN_ON_ONCE(preemptible());
479 if (boot_cpu_has(X86_FEATURE_PGE)) {
480 __flush_tlb_global();
483 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
490 * flush one page in the kernel mapping
492 static inline void __flush_tlb_one_kernel(unsigned long addr)
494 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
497 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
498 * paravirt equivalent. Even with PCID, this is sufficient: we only
499 * use PCID if we also use global PTEs for the kernel mapping, and
500 * INVLPG flushes global translations across all address spaces.
502 * If PTI is on, then the kernel is mapped with non-global PTEs, and
503 * __flush_tlb_one_user() will flush the given address for the current
504 * kernel address space and for its usermode counterpart, but it does
505 * not flush it for other address spaces.
507 __flush_tlb_one_user(addr);
509 if (!static_cpu_has(X86_FEATURE_PTI))
513 * See above. We need to propagate the flush to all other address
514 * spaces. In principle, we only need to propagate it to kernelmode
515 * address spaces, but the extra bookkeeping we would need is not
518 invalidate_other_asid();
521 #define TLB_FLUSH_ALL -1UL
526 * - flush_tlb_all() flushes all processes TLBs
527 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
528 * - flush_tlb_page(vma, vmaddr) flushes one page
529 * - flush_tlb_range(vma, start, end) flushes a range of pages
530 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
531 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
533 * ..but the i386 has somewhat limited tlb flushing capabilities,
534 * and page-granular flushes are available only on i486 and up.
536 struct flush_tlb_info {
538 * We support several kinds of flushes.
540 * - Fully flush a single mm. .mm will be set, .end will be
541 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
542 * which the IPI sender is trying to catch us up.
544 * - Partially flush a single mm. .mm will be set, .start and
545 * .end will indicate the range, and .new_tlb_gen will be set
546 * such that the changes between generation .new_tlb_gen-1 and
547 * .new_tlb_gen are entirely contained in the indicated range.
549 * - Fully flush all mms whose tlb_gens have been updated. .mm
550 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
553 struct mm_struct *mm;
559 #define local_flush_tlb() __flush_tlb()
561 #define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
563 #define flush_tlb_range(vma, start, end) \
564 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
566 extern void flush_tlb_all(void);
567 extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
568 unsigned long end, unsigned long vmflag);
569 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
571 static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
573 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
576 void native_flush_tlb_others(const struct cpumask *cpumask,
577 const struct flush_tlb_info *info);
579 static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
582 * Bump the generation count. This also serves as a full barrier
583 * that synchronizes with switch_mm(): callers are required to order
584 * their read of mm_cpumask after their writes to the paging
587 return atomic64_inc_return(&mm->context.tlb_gen);
590 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
591 struct mm_struct *mm)
594 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
597 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
599 #ifndef CONFIG_PARAVIRT
600 #define flush_tlb_others(mask, info) \
601 native_flush_tlb_others(mask, info)
604 #endif /* _ASM_X86_TLBFLUSH_H */