1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/asm/svm.h>
14 INTERCEPT_SELECTIVE_CR0,
38 INTERCEPT_TASK_SWITCH,
39 INTERCEPT_FERR_FREEZE,
58 struct __attribute__ ((__packed__)) vmcb_control_area {
61 u32 intercept_exceptions;
64 u16 pause_filter_thresh;
65 u16 pause_filter_count;
81 u32 exit_int_info_err;
94 u64 avic_backing_page; /* Offset 0xe0 */
95 u8 reserved_6[8]; /* Offset 0xe8 */
96 u64 avic_logical_id; /* Offset 0xf0 */
97 u64 avic_physical_id; /* Offset 0xf8 */
102 #define TLB_CONTROL_DO_NOTHING 0
103 #define TLB_CONTROL_FLUSH_ALL_ASID 1
104 #define TLB_CONTROL_FLUSH_ASID 3
105 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
107 #define V_TPR_MASK 0x0f
109 #define V_IRQ_SHIFT 8
110 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
112 #define V_GIF_SHIFT 9
113 #define V_GIF_MASK (1 << V_GIF_SHIFT)
115 #define V_INTR_PRIO_SHIFT 16
116 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
118 #define V_IGN_TPR_SHIFT 20
119 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
121 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
123 #define V_INTR_MASKING_SHIFT 24
124 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
126 #define V_GIF_ENABLE_SHIFT 25
127 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
129 #define AVIC_ENABLE_SHIFT 31
130 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
132 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
133 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
135 #define SVM_INTERRUPT_SHADOW_MASK 1
137 #define SVM_IOIO_STR_SHIFT 2
138 #define SVM_IOIO_REP_SHIFT 3
139 #define SVM_IOIO_SIZE_SHIFT 4
140 #define SVM_IOIO_ASIZE_SHIFT 7
142 #define SVM_IOIO_TYPE_MASK 1
143 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
144 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
145 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
146 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
148 #define SVM_VM_CR_VALID_MASK 0x001fULL
149 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
150 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
152 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
153 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
155 struct __attribute__ ((__packed__)) vmcb_seg {
162 struct __attribute__ ((__packed__)) vmcb_save_area {
169 struct vmcb_seg gdtr;
170 struct vmcb_seg ldtr;
171 struct vmcb_seg idtr;
207 struct __attribute__ ((__packed__)) vmcb {
208 struct vmcb_control_area control;
209 struct vmcb_save_area save;
212 #define SVM_CPUID_FUNC 0x8000000a
214 #define SVM_VM_CR_SVM_DISABLE 4
216 #define SVM_SELECTOR_S_SHIFT 4
217 #define SVM_SELECTOR_DPL_SHIFT 5
218 #define SVM_SELECTOR_P_SHIFT 7
219 #define SVM_SELECTOR_AVL_SHIFT 8
220 #define SVM_SELECTOR_L_SHIFT 9
221 #define SVM_SELECTOR_DB_SHIFT 10
222 #define SVM_SELECTOR_G_SHIFT 11
224 #define SVM_SELECTOR_TYPE_MASK (0xf)
225 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
226 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
227 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
228 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
229 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
230 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
231 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
233 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
234 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
235 #define SVM_SELECTOR_CODE_MASK (1 << 3)
237 #define INTERCEPT_CR0_READ 0
238 #define INTERCEPT_CR3_READ 3
239 #define INTERCEPT_CR4_READ 4
240 #define INTERCEPT_CR8_READ 8
241 #define INTERCEPT_CR0_WRITE (16 + 0)
242 #define INTERCEPT_CR3_WRITE (16 + 3)
243 #define INTERCEPT_CR4_WRITE (16 + 4)
244 #define INTERCEPT_CR8_WRITE (16 + 8)
246 #define INTERCEPT_DR0_READ 0
247 #define INTERCEPT_DR1_READ 1
248 #define INTERCEPT_DR2_READ 2
249 #define INTERCEPT_DR3_READ 3
250 #define INTERCEPT_DR4_READ 4
251 #define INTERCEPT_DR5_READ 5
252 #define INTERCEPT_DR6_READ 6
253 #define INTERCEPT_DR7_READ 7
254 #define INTERCEPT_DR0_WRITE (16 + 0)
255 #define INTERCEPT_DR1_WRITE (16 + 1)
256 #define INTERCEPT_DR2_WRITE (16 + 2)
257 #define INTERCEPT_DR3_WRITE (16 + 3)
258 #define INTERCEPT_DR4_WRITE (16 + 4)
259 #define INTERCEPT_DR5_WRITE (16 + 5)
260 #define INTERCEPT_DR6_WRITE (16 + 6)
261 #define INTERCEPT_DR7_WRITE (16 + 7)
263 #define SVM_EVTINJ_VEC_MASK 0xff
265 #define SVM_EVTINJ_TYPE_SHIFT 8
266 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
268 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
269 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
270 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
271 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
273 #define SVM_EVTINJ_VALID (1 << 31)
274 #define SVM_EVTINJ_VALID_ERR (1 << 11)
276 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
277 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
279 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
280 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
281 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
282 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
284 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
285 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
287 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
288 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
289 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
291 #define SVM_EXITINFO_REG_MASK 0x0F
293 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
295 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
296 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
297 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
298 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
299 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
300 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"