4 #include <uapi/asm/svm.h>
13 INTERCEPT_SELECTIVE_CR0,
37 INTERCEPT_TASK_SWITCH,
38 INTERCEPT_FERR_FREEZE,
57 struct __attribute__ ((__packed__)) vmcb_control_area {
60 u32 intercept_exceptions;
63 u16 pause_filter_count;
79 u32 exit_int_info_err;
92 u64 avic_backing_page; /* Offset 0xe0 */
93 u8 reserved_6[8]; /* Offset 0xe8 */
94 u64 avic_logical_id; /* Offset 0xf0 */
95 u64 avic_physical_id; /* Offset 0xf8 */
100 #define TLB_CONTROL_DO_NOTHING 0
101 #define TLB_CONTROL_FLUSH_ALL_ASID 1
102 #define TLB_CONTROL_FLUSH_ASID 3
103 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
105 #define V_TPR_MASK 0x0f
107 #define V_IRQ_SHIFT 8
108 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
110 #define V_INTR_PRIO_SHIFT 16
111 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
113 #define V_IGN_TPR_SHIFT 20
114 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
116 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
118 #define V_INTR_MASKING_SHIFT 24
119 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
121 #define AVIC_ENABLE_SHIFT 31
122 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
124 #define SVM_INTERRUPT_SHADOW_MASK 1
126 #define SVM_IOIO_STR_SHIFT 2
127 #define SVM_IOIO_REP_SHIFT 3
128 #define SVM_IOIO_SIZE_SHIFT 4
129 #define SVM_IOIO_ASIZE_SHIFT 7
131 #define SVM_IOIO_TYPE_MASK 1
132 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
133 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
134 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
135 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
137 #define SVM_VM_CR_VALID_MASK 0x001fULL
138 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
139 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
141 struct __attribute__ ((__packed__)) vmcb_seg {
148 struct __attribute__ ((__packed__)) vmcb_save_area {
155 struct vmcb_seg gdtr;
156 struct vmcb_seg ldtr;
157 struct vmcb_seg idtr;
193 struct __attribute__ ((__packed__)) vmcb {
194 struct vmcb_control_area control;
195 struct vmcb_save_area save;
198 #define SVM_CPUID_FUNC 0x8000000a
200 #define SVM_VM_CR_SVM_DISABLE 4
202 #define SVM_SELECTOR_S_SHIFT 4
203 #define SVM_SELECTOR_DPL_SHIFT 5
204 #define SVM_SELECTOR_P_SHIFT 7
205 #define SVM_SELECTOR_AVL_SHIFT 8
206 #define SVM_SELECTOR_L_SHIFT 9
207 #define SVM_SELECTOR_DB_SHIFT 10
208 #define SVM_SELECTOR_G_SHIFT 11
210 #define SVM_SELECTOR_TYPE_MASK (0xf)
211 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
212 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
213 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
214 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
215 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
216 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
217 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
219 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
220 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
221 #define SVM_SELECTOR_CODE_MASK (1 << 3)
223 #define INTERCEPT_CR0_READ 0
224 #define INTERCEPT_CR3_READ 3
225 #define INTERCEPT_CR4_READ 4
226 #define INTERCEPT_CR8_READ 8
227 #define INTERCEPT_CR0_WRITE (16 + 0)
228 #define INTERCEPT_CR3_WRITE (16 + 3)
229 #define INTERCEPT_CR4_WRITE (16 + 4)
230 #define INTERCEPT_CR8_WRITE (16 + 8)
232 #define INTERCEPT_DR0_READ 0
233 #define INTERCEPT_DR1_READ 1
234 #define INTERCEPT_DR2_READ 2
235 #define INTERCEPT_DR3_READ 3
236 #define INTERCEPT_DR4_READ 4
237 #define INTERCEPT_DR5_READ 5
238 #define INTERCEPT_DR6_READ 6
239 #define INTERCEPT_DR7_READ 7
240 #define INTERCEPT_DR0_WRITE (16 + 0)
241 #define INTERCEPT_DR1_WRITE (16 + 1)
242 #define INTERCEPT_DR2_WRITE (16 + 2)
243 #define INTERCEPT_DR3_WRITE (16 + 3)
244 #define INTERCEPT_DR4_WRITE (16 + 4)
245 #define INTERCEPT_DR5_WRITE (16 + 5)
246 #define INTERCEPT_DR6_WRITE (16 + 6)
247 #define INTERCEPT_DR7_WRITE (16 + 7)
249 #define SVM_EVTINJ_VEC_MASK 0xff
251 #define SVM_EVTINJ_TYPE_SHIFT 8
252 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
254 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
255 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
256 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
257 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
259 #define SVM_EVTINJ_VALID (1 << 31)
260 #define SVM_EVTINJ_VALID_ERR (1 << 11)
262 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
263 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
265 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
266 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
267 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
268 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
270 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
271 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
273 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
274 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
275 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
277 #define SVM_EXITINFO_REG_MASK 0x0F
279 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
281 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
282 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
283 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
284 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
285 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
286 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"