1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_SPECIAL_INSNS_H
3 #define _ASM_X86_SPECIAL_INSNS_H
9 #include <asm/processor-flags.h>
10 #include <linux/jump_label.h>
13 * The compiler should not reorder volatile asm statements with respect to each
14 * other: they should execute in program order. However GCC 4.9.x and 5.x have
15 * a bug (which was fixed in 8.1, 7.3 and 6.5) where they might reorder
16 * volatile asm. The write functions are not affected since they have memory
17 * clobbers preventing reordering. To prevent reads from being reordered with
18 * respect to writes, use a dummy memory operand.
21 #define __FORCE_ORDER "m"(*(unsigned int *)0x1000UL)
23 void native_write_cr0(unsigned long val);
25 static inline unsigned long native_read_cr0(void)
28 asm volatile("mov %%cr0,%0\n\t" : "=r" (val) : __FORCE_ORDER);
32 static inline unsigned long native_read_cr2(void)
35 asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : __FORCE_ORDER);
39 static inline void native_write_cr2(unsigned long val)
41 asm volatile("mov %0,%%cr2": : "r" (val) : "memory");
44 static inline unsigned long __native_read_cr3(void)
47 asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER);
51 static inline void native_write_cr3(unsigned long val)
53 asm volatile("mov %0,%%cr3": : "r" (val) : "memory");
56 static inline unsigned long native_read_cr4(void)
61 * This could fault if CR4 does not exist. Non-existent CR4
62 * is functionally equivalent to CR4 == 0. Keep it simple and pretend
63 * that CR4 == 0 on CPUs that don't have CR4.
65 asm volatile("1: mov %%cr4, %0\n"
68 : "=r" (val) : "0" (0), __FORCE_ORDER);
70 /* CR4 always exists on x86_64. */
71 asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : __FORCE_ORDER);
76 void native_write_cr4(unsigned long val);
78 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
79 static inline u32 rdpkru(void)
85 * "rdpkru" instruction. Places PKRU contents in to EAX,
86 * clears EDX and requires that ecx=0.
88 asm volatile(".byte 0x0f,0x01,0xee\n\t"
89 : "=a" (pkru), "=d" (edx)
94 static inline void wrpkru(u32 pkru)
99 * "wrpkru" instruction. Loads contents in EAX to PKRU,
100 * requires that ecx = edx = 0.
102 asm volatile(".byte 0x0f,0x01,0xef\n\t"
103 : : "a" (pkru), "c"(ecx), "d"(edx));
106 static inline void __write_pkru(u32 pkru)
109 * WRPKRU is relatively expensive compared to RDPKRU.
110 * Avoid WRPKRU when it would not change the value.
112 if (pkru == rdpkru())
119 static inline u32 rdpkru(void)
124 static inline void __write_pkru(u32 pkru)
129 static inline void native_wbinvd(void)
131 asm volatile("wbinvd": : :"memory");
134 extern asmlinkage void native_load_gs_index(unsigned);
136 static inline unsigned long __read_cr4(void)
138 return native_read_cr4();
141 #ifdef CONFIG_PARAVIRT_XXL
142 #include <asm/paravirt.h>
145 static inline unsigned long read_cr0(void)
147 return native_read_cr0();
150 static inline void write_cr0(unsigned long x)
155 static inline unsigned long read_cr2(void)
157 return native_read_cr2();
160 static inline void write_cr2(unsigned long x)
166 * Careful! CR3 contains more than just an address. You probably want
167 * read_cr3_pa() instead.
169 static inline unsigned long __read_cr3(void)
171 return __native_read_cr3();
174 static inline void write_cr3(unsigned long x)
179 static inline void __write_cr4(unsigned long x)
184 static inline void wbinvd(void)
191 static inline void load_gs_index(unsigned selector)
193 native_load_gs_index(selector);
198 #endif /* CONFIG_PARAVIRT_XXL */
200 static inline void clflush(volatile void *__p)
202 asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
205 static inline void clflushopt(volatile void *__p)
207 alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
208 ".byte 0x66; clflush %P0",
209 X86_FEATURE_CLFLUSHOPT,
210 "+m" (*(volatile char __force *)__p));
213 static inline void clwb(volatile void *__p)
215 volatile struct { char x[64]; } *p = __p;
217 asm volatile(ALTERNATIVE_2(
218 ".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])",
219 ".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */
220 X86_FEATURE_CLFLUSHOPT,
221 ".byte 0x66, 0x0f, 0xae, 0x30", /* clwb (%%rax) */
227 #define nop() asm volatile ("nop")
230 #endif /* __KERNEL__ */
232 #endif /* _ASM_X86_SPECIAL_INSNS_H */