1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PGTABLE_64_H
3 #define _ASM_X86_PGTABLE_64_H
5 #include <linux/const.h>
6 #include <asm/pgtable_64_types.h>
11 * This file contains the functions and defines necessary to modify and use
12 * the x86-64 page table tree.
14 #include <asm/processor.h>
15 #include <linux/bitops.h>
16 #include <linux/threads.h>
17 #include <asm/fixmap.h>
19 extern p4d_t level4_kernel_pgt[512];
20 extern p4d_t level4_ident_pgt[512];
21 extern pud_t level3_kernel_pgt[512];
22 extern pud_t level3_ident_pgt[512];
23 extern pmd_t level2_kernel_pgt[512];
24 extern pmd_t level2_fixmap_pgt[512];
25 extern pmd_t level2_ident_pgt[512];
26 extern pte_t level1_fixmap_pgt[512 * FIXMAP_PMD_NUM];
27 extern pgd_t init_top_pgt[];
29 #define swapper_pg_dir init_top_pgt
31 extern void paging_init(void);
32 static inline void sync_initial_page_table(void) { }
34 #define pte_ERROR(e) \
35 pr_err("%s:%d: bad pte %p(%016lx)\n", \
36 __FILE__, __LINE__, &(e), pte_val(e))
37 #define pmd_ERROR(e) \
38 pr_err("%s:%d: bad pmd %p(%016lx)\n", \
39 __FILE__, __LINE__, &(e), pmd_val(e))
40 #define pud_ERROR(e) \
41 pr_err("%s:%d: bad pud %p(%016lx)\n", \
42 __FILE__, __LINE__, &(e), pud_val(e))
44 #if CONFIG_PGTABLE_LEVELS >= 5
45 #define p4d_ERROR(e) \
46 pr_err("%s:%d: bad p4d %p(%016lx)\n", \
47 __FILE__, __LINE__, &(e), p4d_val(e))
50 #define pgd_ERROR(e) \
51 pr_err("%s:%d: bad pgd %p(%016lx)\n", \
52 __FILE__, __LINE__, &(e), pgd_val(e))
56 void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte);
57 void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte);
59 static inline void native_set_pte(pte_t *ptep, pte_t pte)
61 WRITE_ONCE(*ptep, pte);
64 static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
67 native_set_pte(ptep, native_make_pte(0));
70 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
72 native_set_pte(ptep, pte);
75 static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
77 WRITE_ONCE(*pmdp, pmd);
80 static inline void native_pmd_clear(pmd_t *pmd)
82 native_set_pmd(pmd, native_make_pmd(0));
85 static inline pte_t native_ptep_get_and_clear(pte_t *xp)
88 return native_make_pte(xchg(&xp->pte, 0));
90 /* native_local_ptep_get_and_clear,
91 but duplicated because of cyclic dependency */
93 native_pte_clear(NULL, 0, xp);
98 static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
101 return native_make_pmd(xchg(&xp->pmd, 0));
103 /* native_local_pmdp_get_and_clear,
104 but duplicated because of cyclic dependency */
106 native_pmd_clear(xp);
111 static inline void native_set_pud(pud_t *pudp, pud_t pud)
113 WRITE_ONCE(*pudp, pud);
116 static inline void native_pud_clear(pud_t *pud)
118 native_set_pud(pud, native_make_pud(0));
121 static inline pud_t native_pudp_get_and_clear(pud_t *xp)
124 return native_make_pud(xchg(&xp->pud, 0));
126 /* native_local_pudp_get_and_clear,
127 * but duplicated because of cyclic dependency
131 native_pud_clear(xp);
136 #ifdef CONFIG_PAGE_TABLE_ISOLATION
138 * All top-level PAGE_TABLE_ISOLATION page tables are order-1 pages
139 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and
140 * the user one is in the last 4k. To switch between them, you
141 * just need to flip the 12th bit in their addresses.
143 #define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT
146 * This generates better code than the inline assembly in
149 static inline void *ptr_set_bit(void *ptr, int bit)
151 unsigned long __ptr = (unsigned long)ptr;
154 return (void *)__ptr;
156 static inline void *ptr_clear_bit(void *ptr, int bit)
158 unsigned long __ptr = (unsigned long)ptr;
161 return (void *)__ptr;
164 static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp)
166 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT);
169 static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp)
171 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT);
174 static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp)
176 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT);
179 static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp)
181 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT);
183 #endif /* CONFIG_PAGE_TABLE_ISOLATION */
186 * Page table pages are page-aligned. The lower half of the top
187 * level is used for userspace and the top half for the kernel.
189 * Returns true for parts of the PGD that map userspace and
190 * false for the parts that map the kernel.
192 static inline bool pgdp_maps_userspace(void *__ptr)
194 unsigned long ptr = (unsigned long)__ptr;
196 return (ptr & ~PAGE_MASK) < (PAGE_SIZE / 2);
199 #ifdef CONFIG_PAGE_TABLE_ISOLATION
200 pgd_t __pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd);
203 * Take a PGD location (pgdp) and a pgd value that needs to be set there.
204 * Populates the user and returns the resulting PGD that must be set in
205 * the kernel copy of the page tables.
207 static inline pgd_t pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd)
209 if (!static_cpu_has(X86_FEATURE_PTI))
211 return __pti_set_user_pgd(pgdp, pgd);
214 static inline pgd_t pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd)
220 static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d)
222 #if defined(CONFIG_PAGE_TABLE_ISOLATION) && !defined(CONFIG_X86_5LEVEL)
223 WRITE_ONCE(p4dp->pgd, pti_set_user_pgd(&p4dp->pgd, p4d.pgd));
225 WRITE_ONCE(*p4dp, p4d);
229 static inline void native_p4d_clear(p4d_t *p4d)
231 #ifdef CONFIG_X86_5LEVEL
232 native_set_p4d(p4d, native_make_p4d(0));
234 native_set_p4d(p4d, (p4d_t) { .pgd = native_make_pgd(0)});
238 static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
240 #ifdef CONFIG_PAGE_TABLE_ISOLATION
241 WRITE_ONCE(*pgdp, pti_set_user_pgd(pgdp, pgd));
243 WRITE_ONCE(*pgdp, pgd);
247 static inline void native_pgd_clear(pgd_t *pgd)
249 native_set_pgd(pgd, native_make_pgd(0));
252 extern void sync_global_pgds(unsigned long start, unsigned long end);
255 * Conversion functions: convert a page and protection to a page entry,
256 * and a page entry and page directory to the page they refer to.
262 static inline int pgd_large(pgd_t pgd) { return 0; }
263 #define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
265 /* PUD - Level3 access */
267 /* PMD - Level 2 access */
269 /* PTE - Level 1 access. */
271 /* x86-64 always has all page tables mapped. */
272 #define pte_offset_map(dir, address) pte_offset_kernel((dir), (address))
273 #define pte_unmap(pte) ((void)(pte))/* NOP */
276 * Encode and de-code a swap entry
278 * | ... | 11| 10| 9|8|7|6|5| 4| 3|2| 1|0| <- bit number
279 * | ... |SW3|SW2|SW1|G|L|D|A|CD|WT|U| W|P| <- bit names
280 * | TYPE (59-63) | ~OFFSET (9-58) |0|0|X|X| X| X|X|SD|0| <- swp entry
282 * G (8) is aliased and used as a PROT_NONE indicator for
283 * !present ptes. We need to start storing swap entries above
284 * there. We also need to avoid using A and D because of an
285 * erratum where they can be incorrectly set by hardware on
288 * SD (1) in swp entry is used to store soft dirty bit, which helps us
289 * remember soft dirty over page migration
291 * Bit 7 in swp entry should be 0 because pmd_present checks not only P,
294 * The offset is inverted by a binary not operation to make the high
297 #define SWP_TYPE_BITS 5
299 #define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
301 /* We always extract/encode the offset by shifting it all the way up, and then down again */
302 #define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT+SWP_TYPE_BITS)
304 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
306 /* Extract the high bits for type */
307 #define __swp_type(x) ((x).val >> (64 - SWP_TYPE_BITS))
309 /* Shift up (to get rid of type), then down to get value */
310 #define __swp_offset(x) (~(x).val << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT)
313 * Shift the offset up "too far" by TYPE bits, then down again
314 * The offset is inverted by a binary not operation to make the high
317 #define __swp_entry(type, offset) ((swp_entry_t) { \
318 (~(unsigned long)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
319 | ((unsigned long)(type) << (64-SWP_TYPE_BITS)) })
321 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) })
322 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val((pmd)) })
323 #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
324 #define __swp_entry_to_pmd(x) ((pmd_t) { .pmd = (x).val })
326 extern int kern_addr_valid(unsigned long addr);
327 extern void cleanup_highmap(void);
329 #define HAVE_ARCH_UNMAPPED_AREA
330 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
332 #define pgtable_cache_init() do { } while (0)
333 #define check_pgt_cache() do { } while (0)
335 #define PAGE_AGP PAGE_KERNEL_NOCACHE
336 #define HAVE_PAGE_AGP 1
338 /* fs/proc/kcore.c */
339 #define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
340 #define kc_offset_to_vaddr(o) ((o) | ~__VIRTUAL_MASK)
342 #define __HAVE_ARCH_PTE_SAME
344 #define vmemmap ((struct page *)VMEMMAP_START)
346 extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
347 extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
349 #define gup_fast_permitted gup_fast_permitted
350 static inline bool gup_fast_permitted(unsigned long start, int nr_pages,
353 unsigned long len, end;
355 len = (unsigned long)nr_pages << PAGE_SHIFT;
359 if (end >> __VIRTUAL_MASK_SHIFT)
364 #include <asm/pgtable-invert.h>
366 #endif /* !__ASSEMBLY__ */
367 #endif /* _ASM_X86_PGTABLE_64_H */