arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7 #include <linux/objtool.h>
   8 #include <linux/linkage.h>
   9
  10 #include <asm/alternative.h>
  11 #include <asm/cpufeatures.h>
  12 #include <asm/msr-index.h>
  13 #include <asm/unwind_hints.h>
  14 #include <asm/percpu.h>
  15
  16 #define RETPOLINE_THUNK_SIZE    32
  17
  18 /*
  19  * Fill the CPU return stack buffer.
  20  *
  21  * Each entry in the RSB, if used for a speculative 'ret', contains an
  22  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  23  *
  24  * This is required in various cases for retpoline and IBRS-based
  25  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  26  * eliminate potentially bogus entries from the RSB, and sometimes
  27  * purely to ensure that it doesn't get empty, which on some CPUs would
  28  * allow predictions from other (unwanted!) sources to be used.
  29  *
  30  * We define a CPP macro such that it can be used from both .S files and
  31  * inline assembly. It's possible to do a .macro and then include that
  32  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  33  */
  34
  35 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  36
  37 /*
  38  * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
  39  */
  40 #define __FILL_RETURN_SLOT                      \
  41         ANNOTATE_INTRA_FUNCTION_CALL;           \
  42         call    772f;                           \
  43         int3;                                   \
  44 772:
  45
  46 /*
  47  * Stuff the entire RSB.
  48  *
  49  * Google experimented with loop-unrolling and this turned out to be
  50  * the optimal version - two calls, each with their own speculation
  51  * trap should their return address end up getting used, in a loop.
  52  */
  53 #ifdef CONFIG_X86_64
  54 #define __FILL_RETURN_BUFFER(reg, nr)                   \
  55         mov     $(nr/2), reg;                           \
  56 771:                                                    \
  57         __FILL_RETURN_SLOT                              \
  58         __FILL_RETURN_SLOT                              \
  59         add     $(BITS_PER_LONG/8) * 2, %_ASM_SP;       \
  60         dec     reg;                                    \
  61         jnz     771b;                                   \
  62         /* barrier for jnz misprediction */             \
  63         lfence;
  64 #else
  65 /*
  66  * i386 doesn't unconditionally have LFENCE, as such it can't
  67  * do a loop.
  68  */
  69 #define __FILL_RETURN_BUFFER(reg, nr)                   \
  70         .rept nr;                                       \
  71         __FILL_RETURN_SLOT;                             \
  72         .endr;                                          \
  73         add     $(BITS_PER_LONG/8) * nr, %_ASM_SP;
  74 #endif
  75
  76 /*
  77  * Stuff a single RSB slot.
  78  *
  79  * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
  80  * forced to retire before letting a RET instruction execute.
  81  *
  82  * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
  83  * before this point.
  84  */
  85 #define __FILL_ONE_RETURN                               \
  86         __FILL_RETURN_SLOT                              \
  87         add     $(BITS_PER_LONG/8), %_ASM_SP;           \
  88         lfence;
  89
  90 #ifdef __ASSEMBLY__
  91
  92 /*
  93  * This should be used immediately before an indirect jump/call. It tells
  94  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  95  * builds.
  96  */
  97 .macro ANNOTATE_RETPOLINE_SAFE
  98         .Lannotate_\@:
  99         .pushsection .discard.retpoline_safe
 100         _ASM_PTR .Lannotate_\@
 101         .popsection
 102 .endm
 103
 104 /*
 105  * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
 106  * vs RETBleed validation.
 107  */
 108 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
 109
 110 /*
 111  * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
 112  * eventually turn into it's own annotation.
 113  */
 114 .macro ANNOTATE_UNRET_END
 115 #if (defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO))
 116         ANNOTATE_RETPOLINE_SAFE
 117         nop
 118 #endif
 119 .endm
 120
 121 /*
 122  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
 123  * indirect jmp/call which may be susceptible to the Spectre variant 2
 124  * attack.
 125  */
 126 .macro JMP_NOSPEC reg:req
 127 #ifdef CONFIG_RETPOLINE
 128         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
 129                       __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
 130                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
 131 #else
 132         jmp     *%\reg
 133 #endif
 134 .endm
 135
 136 .macro CALL_NOSPEC reg:req
 137 #ifdef CONFIG_RETPOLINE
 138         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
 139                       __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
 140                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
 141 #else
 142         call    *%\reg
 143 #endif
 144 .endm
 145
 146  /*
 147   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 148   * monstrosity above, manually.
 149   */
 150 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
 151         ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
 152                 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
 153                 __stringify(__FILL_ONE_RETURN), \ftr2
 154
 155 .Lskip_rsb_\@:
 156 .endm
 157
 158 #ifdef CONFIG_CPU_UNRET_ENTRY
 159 #define CALL_UNTRAIN_RET        "call entry_untrain_ret"
 160 #else
 161 #define CALL_UNTRAIN_RET        ""
 162 #endif
 163
 164 /*
 165  * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
 166  * return thunk isn't mapped into the userspace tables (then again, AMD
 167  * typically has NO_MELTDOWN).
 168  *
 169  * While retbleed_untrain_ret() doesn't clobber anything but requires stack,
 170  * entry_ibpb() will clobber AX, CX, DX.
 171  *
 172  * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
 173  * where we have a stack but before any RET instruction.
 174  */
 175 .macro UNTRAIN_RET
 176 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) || \
 177         defined(CONFIG_CPU_SRSO)
 178         ANNOTATE_UNRET_END
 179         ALTERNATIVE_2 "",                                               \
 180                       CALL_UNTRAIN_RET, X86_FEATURE_UNRET,              \
 181                       "call entry_ibpb", X86_FEATURE_ENTRY_IBPB
 182 #endif
 183 .endm
 184
 185 #else /* __ASSEMBLY__ */
 186
 187 #define ANNOTATE_RETPOLINE_SAFE                                 \
 188         "999:\n\t"                                              \
 189         ".pushsection .discard.retpoline_safe\n\t"              \
 190         _ASM_PTR " 999b\n\t"                                    \
 191         ".popsection\n\t"
 192
 193 #ifdef CONFIG_RETHUNK
 194 extern void __x86_return_thunk(void);
 195 #else
 196 static inline void __x86_return_thunk(void) {}
 197 #endif
 198
 199 extern void retbleed_return_thunk(void);
 200 extern void srso_return_thunk(void);
 201 extern void srso_alias_return_thunk(void);
 202
 203 extern void retbleed_untrain_ret(void);
 204 extern void srso_untrain_ret(void);
 205 extern void srso_alias_untrain_ret(void);
 206
 207 extern void entry_untrain_ret(void);
 208 extern void entry_ibpb(void);
 209
 210 #ifdef CONFIG_RETPOLINE
 211
 212 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
 213
 214 #define GEN(reg) \
 215         extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
 216 #include <asm/GEN-for-each-reg.h>
 217 #undef GEN
 218
 219 extern retpoline_thunk_t __x86_indirect_thunk_array[];
 220
 221 #ifdef CONFIG_X86_64
 222
 223 /*
 224  * Inline asm uses the %V modifier which is only in newer GCC
 225  * which is ensured when CONFIG_RETPOLINE is defined.
 226  */
 227 # define CALL_NOSPEC                                            \
 228         ALTERNATIVE_2(                                          \
 229         ANNOTATE_RETPOLINE_SAFE                                 \
 230         "call *%[thunk_target]\n",                              \
 231         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 232         X86_FEATURE_RETPOLINE,                                  \
 233         "lfence;\n"                                             \
 234         ANNOTATE_RETPOLINE_SAFE                                 \
 235         "call *%[thunk_target]\n",                              \
 236         X86_FEATURE_RETPOLINE_LFENCE)
 237
 238 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 239
 240 #else /* CONFIG_X86_32 */
 241 /*
 242  * For i386 we use the original ret-equivalent retpoline, because
 243  * otherwise we'll run out of registers. We don't care about CET
 244  * here, anyway.
 245  */
 246 # define CALL_NOSPEC                                            \
 247         ALTERNATIVE_2(                                          \
 248         ANNOTATE_RETPOLINE_SAFE                                 \
 249         "call *%[thunk_target]\n",                              \
 250         "       jmp    904f;\n"                                 \
 251         "       .align 16\n"                                    \
 252         "901:   call   903f;\n"                                 \
 253         "902:   pause;\n"                                       \
 254         "       lfence;\n"                                      \
 255         "       jmp    902b;\n"                                 \
 256         "       .align 16\n"                                    \
 257         "903:   lea    4(%%esp), %%esp;\n"                      \
 258         "       pushl  %[thunk_target];\n"                      \
 259         "       ret;\n"                                         \
 260         "       .align 16\n"                                    \
 261         "904:   call   901b;\n",                                \
 262         X86_FEATURE_RETPOLINE,                                  \
 263         "lfence;\n"                                             \
 264         ANNOTATE_RETPOLINE_SAFE                                 \
 265         "call *%[thunk_target]\n",                              \
 266         X86_FEATURE_RETPOLINE_LFENCE)
 267
 268 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 269 #endif
 270 #else /* No retpoline for C / inline asm */
 271 # define CALL_NOSPEC "call *%[thunk_target]\n"
 272 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 273 #endif
 274
 275 /* The Spectre V2 mitigation variants */
 276 enum spectre_v2_mitigation {
 277         SPECTRE_V2_NONE,
 278         SPECTRE_V2_RETPOLINE,
 279         SPECTRE_V2_LFENCE,
 280         SPECTRE_V2_EIBRS,
 281         SPECTRE_V2_EIBRS_RETPOLINE,
 282         SPECTRE_V2_EIBRS_LFENCE,
 283         SPECTRE_V2_IBRS,
 284 };
 285
 286 /* The indirect branch speculation control variants */
 287 enum spectre_v2_user_mitigation {
 288         SPECTRE_V2_USER_NONE,
 289         SPECTRE_V2_USER_STRICT,
 290         SPECTRE_V2_USER_STRICT_PREFERRED,
 291         SPECTRE_V2_USER_PRCTL,
 292         SPECTRE_V2_USER_SECCOMP,
 293 };
 294
 295 /* The Speculative Store Bypass disable variants */
 296 enum ssb_mitigation {
 297         SPEC_STORE_BYPASS_NONE,
 298         SPEC_STORE_BYPASS_DISABLE,
 299         SPEC_STORE_BYPASS_PRCTL,
 300         SPEC_STORE_BYPASS_SECCOMP,
 301 };
 302
 303 extern char __indirect_thunk_start[];
 304 extern char __indirect_thunk_end[];
 305
 306 static __always_inline
 307 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 308 {
 309         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 310                 : : "c" (msr),
 311                     "a" ((u32)val),
 312                     "d" ((u32)(val >> 32)),
 313                     [feature] "i" (feature)
 314                 : "memory");
 315 }
 316
 317 extern u64 x86_pred_cmd;
 318
 319 static inline void indirect_branch_prediction_barrier(void)
 320 {
 321         alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
 322 }
 323
 324 /* The Intel SPEC CTRL MSR base value cache */
 325 extern u64 x86_spec_ctrl_base;
 326 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
 327 extern void update_spec_ctrl_cond(u64 val);
 328 extern u64 spec_ctrl_current(void);
 329
 330 /*
 331  * With retpoline, we must use IBRS to restrict branch prediction
 332  * before calling into firmware.
 333  *
 334  * (Implemented as CPP macros due to header hell.)
 335  */
 336 #define firmware_restrict_branch_speculation_start()                    \
 337 do {                                                                    \
 338         preempt_disable();                                              \
 339         alternative_msr_write(MSR_IA32_SPEC_CTRL,                       \
 340                               spec_ctrl_current() | SPEC_CTRL_IBRS,     \
 341                               X86_FEATURE_USE_IBRS_FW);                 \
 342         alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB,         \
 343                               X86_FEATURE_USE_IBPB_FW);                 \
 344 } while (0)
 345
 346 #define firmware_restrict_branch_speculation_end()                      \
 347 do {                                                                    \
 348         alternative_msr_write(MSR_IA32_SPEC_CTRL,                       \
 349                               spec_ctrl_current(),                      \
 350                               X86_FEATURE_USE_IBRS_FW);                 \
 351         preempt_enable();                                               \
 352 } while (0)
 353
 354 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 355 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 356 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 357
 358 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 359 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 360
 361 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 362
 363 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 364
 365 #include <asm/segment.h>
 366
 367 /**
 368  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 369  *
 370  * This uses the otherwise unused and obsolete VERW instruction in
 371  * combination with microcode which triggers a CPU buffer flush when the
 372  * instruction is executed.
 373  */
 374 static __always_inline void mds_clear_cpu_buffers(void)
 375 {
 376         static const u16 ds = __KERNEL_DS;
 377
 378         /*
 379          * Has to be the memory-operand variant because only that
 380          * guarantees the CPU buffer flush functionality according to
 381          * documentation. The register-operand variant does not.
 382          * Works with any segment selector, but a valid writable
 383          * data segment is the fastest variant.
 384          *
 385          * "cc" clobber is required because VERW modifies ZF.
 386          */
 387         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 388 }
 389
 390 /**
 391  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 392  *
 393  * Clear CPU buffers if the corresponding static key is enabled
 394  */
 395 static __always_inline void mds_user_clear_cpu_buffers(void)
 396 {
 397         if (static_branch_likely(&mds_user_clear))
 398                 mds_clear_cpu_buffers();
 399 }
 400
 401 /**
 402  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 403  *
 404  * Clear CPU buffers if the corresponding static key is enabled
 405  */
 406 static inline void mds_idle_clear_cpu_buffers(void)
 407 {
 408         if (static_branch_likely(&mds_idle_clear))
 409                 mds_clear_cpu_buffers();
 410 }
 411
 412 #endif /* __ASSEMBLY__ */
 413
 414 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */