arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7
   8 #include <asm/alternative.h>
   9 #include <asm/alternative-asm.h>
  10 #include <asm/cpufeatures.h>
  11 #include <asm/msr-index.h>
  12
  13 /*
  14  * Fill the CPU return stack buffer.
  15  *
  16  * Each entry in the RSB, if used for a speculative 'ret', contains an
  17  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  18  *
  19  * This is required in various cases for retpoline and IBRS-based
  20  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  21  * eliminate potentially bogus entries from the RSB, and sometimes
  22  * purely to ensure that it doesn't get empty, which on some CPUs would
  23  * allow predictions from other (unwanted!) sources to be used.
  24  *
  25  * We define a CPP macro such that it can be used from both .S files and
  26  * inline assembly. It's possible to do a .macro and then include that
  27  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  28  */
  29
  30 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  31 #define RSB_FILL_LOOPS          16      /* To avoid underflow */
  32
  33 /*
  34  * Google experimented with loop-unrolling and this turned out to be
  35  * the optimal version — two calls, each with their own speculation
  36  * trap should their return address end up getting used, in a loop.
  37  */
  38 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  39         mov     $(nr/2), reg;                   \
  40 771:                                            \
  41         call    772f;                           \
  42 773:    /* speculation trap */                  \
  43         pause;                                  \
  44         lfence;                                 \
  45         jmp     773b;                           \
  46 772:                                            \
  47         call    774f;                           \
  48 775:    /* speculation trap */                  \
  49         pause;                                  \
  50         lfence;                                 \
  51         jmp     775b;                           \
  52 774:                                            \
  53         dec     reg;                            \
  54         jnz     771b;                           \
  55         add     $(BITS_PER_LONG/8) * nr, sp;
  56
  57 #ifdef __ASSEMBLY__
  58
  59 /*
  60  * This should be used immediately before a retpoline alternative.  It tells
  61  * objtool where the retpolines are so that it can make sense of the control
  62  * flow by just reading the original instruction(s) and ignoring the
  63  * alternatives.
  64  */
  65 .macro ANNOTATE_NOSPEC_ALTERNATIVE
  66         .Lannotate_\@:
  67         .pushsection .discard.nospec
  68         .long .Lannotate_\@ - .
  69         .popsection
  70 .endm
  71
  72 /*
  73  * This should be used immediately before an indirect jump/call. It tells
  74  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  75  * builds.
  76  */
  77 .macro ANNOTATE_RETPOLINE_SAFE
  78         .Lannotate_\@:
  79         .pushsection .discard.retpoline_safe
  80         _ASM_PTR .Lannotate_\@
  81         .popsection
  82 .endm
  83
  84 /*
  85  * These are the bare retpoline primitives for indirect jmp and call.
  86  * Do not use these directly; they only exist to make the ALTERNATIVE
  87  * invocation below less ugly.
  88  */
  89 .macro RETPOLINE_JMP reg:req
  90         call    .Ldo_rop_\@
  91 .Lspec_trap_\@:
  92         pause
  93         lfence
  94         jmp     .Lspec_trap_\@
  95 .Ldo_rop_\@:
  96         mov     \reg, (%_ASM_SP)
  97         ret
  98 .endm
  99
 100 /*
 101  * This is a wrapper around RETPOLINE_JMP so the called function in reg
 102  * returns to the instruction after the macro.
 103  */
 104 .macro RETPOLINE_CALL reg:req
 105         jmp     .Ldo_call_\@
 106 .Ldo_retpoline_jmp_\@:
 107         RETPOLINE_JMP \reg
 108 .Ldo_call_\@:
 109         call    .Ldo_retpoline_jmp_\@
 110 .endm
 111
 112 /*
 113  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
 114  * indirect jmp/call which may be susceptible to the Spectre variant 2
 115  * attack.
 116  */
 117 .macro JMP_NOSPEC reg:req
 118 #ifdef CONFIG_RETPOLINE
 119         ANNOTATE_NOSPEC_ALTERNATIVE
 120         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *\reg),  \
 121                 __stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE, \
 122                 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
 123 #else
 124         jmp     *\reg
 125 #endif
 126 .endm
 127
 128 .macro CALL_NOSPEC reg:req
 129 #ifdef CONFIG_RETPOLINE
 130         ANNOTATE_NOSPEC_ALTERNATIVE
 131         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *\reg), \
 132                 __stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
 133                 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *\reg), X86_FEATURE_RETPOLINE_AMD
 134 #else
 135         call    *\reg
 136 #endif
 137 .endm
 138
 139  /*
 140   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 141   * monstrosity above, manually.
 142   */
 143 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 144 #ifdef CONFIG_RETPOLINE
 145         ANNOTATE_NOSPEC_ALTERNATIVE
 146         ALTERNATIVE "jmp .Lskip_rsb_\@",                                \
 147                 __stringify(__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP))    \
 148                 \ftr
 149 .Lskip_rsb_\@:
 150 #endif
 151 .endm
 152
 153 #else /* __ASSEMBLY__ */
 154
 155 #define ANNOTATE_NOSPEC_ALTERNATIVE                             \
 156         "999:\n\t"                                              \
 157         ".pushsection .discard.nospec\n\t"                      \
 158         ".long 999b - .\n\t"                                    \
 159         ".popsection\n\t"
 160
 161 #define ANNOTATE_RETPOLINE_SAFE                                 \
 162         "999:\n\t"                                              \
 163         ".pushsection .discard.retpoline_safe\n\t"              \
 164         _ASM_PTR " 999b\n\t"                                    \
 165         ".popsection\n\t"
 166
 167 #if defined(CONFIG_X86_64) && defined(RETPOLINE)
 168
 169 /*
 170  * Since the inline asm uses the %V modifier which is only in newer GCC,
 171  * the 64-bit one is dependent on RETPOLINE not CONFIG_RETPOLINE.
 172  */
 173 # define CALL_NOSPEC                                            \
 174         ANNOTATE_NOSPEC_ALTERNATIVE                             \
 175         ALTERNATIVE(                                            \
 176         ANNOTATE_RETPOLINE_SAFE                                 \
 177         "call *%[thunk_target]\n",                              \
 178         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 179         X86_FEATURE_RETPOLINE)
 180 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 181
 182 #elif defined(CONFIG_X86_32) && defined(CONFIG_RETPOLINE)
 183 /*
 184  * For i386 we use the original ret-equivalent retpoline, because
 185  * otherwise we'll run out of registers. We don't care about CET
 186  * here, anyway.
 187  */
 188 # define CALL_NOSPEC                                            \
 189         ALTERNATIVE(                                            \
 190         ANNOTATE_RETPOLINE_SAFE                                 \
 191         "call *%[thunk_target]\n",                              \
 192         "       jmp    904f;\n"                                 \
 193         "       .align 16\n"                                    \
 194         "901:   call   903f;\n"                                 \
 195         "902:   pause;\n"                                       \
 196         "       lfence;\n"                                      \
 197         "       jmp    902b;\n"                                 \
 198         "       .align 16\n"                                    \
 199         "903:   lea    4(%%esp), %%esp;\n"                      \
 200         "       pushl  %[thunk_target];\n"                      \
 201         "       ret;\n"                                         \
 202         "       .align 16\n"                                    \
 203         "904:   call   901b;\n",                                \
 204         X86_FEATURE_RETPOLINE)
 205
 206 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 207 #else /* No retpoline for C / inline asm */
 208 # define CALL_NOSPEC "call *%[thunk_target]\n"
 209 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 210 #endif
 211
 212 /* The Spectre V2 mitigation variants */
 213 enum spectre_v2_mitigation {
 214         SPECTRE_V2_NONE,
 215         SPECTRE_V2_RETPOLINE_MINIMAL,
 216         SPECTRE_V2_RETPOLINE_MINIMAL_AMD,
 217         SPECTRE_V2_RETPOLINE_GENERIC,
 218         SPECTRE_V2_RETPOLINE_AMD,
 219         SPECTRE_V2_IBRS_ENHANCED,
 220 };
 221
 222 /* The indirect branch speculation control variants */
 223 enum spectre_v2_user_mitigation {
 224         SPECTRE_V2_USER_NONE,
 225         SPECTRE_V2_USER_STRICT,
 226         SPECTRE_V2_USER_STRICT_PREFERRED,
 227         SPECTRE_V2_USER_PRCTL,
 228         SPECTRE_V2_USER_SECCOMP,
 229 };
 230
 231 /* The Speculative Store Bypass disable variants */
 232 enum ssb_mitigation {
 233         SPEC_STORE_BYPASS_NONE,
 234         SPEC_STORE_BYPASS_DISABLE,
 235         SPEC_STORE_BYPASS_PRCTL,
 236         SPEC_STORE_BYPASS_SECCOMP,
 237 };
 238
 239 extern char __indirect_thunk_start[];
 240 extern char __indirect_thunk_end[];
 241
 242 /*
 243  * On VMEXIT we must ensure that no RSB predictions learned in the guest
 244  * can be followed in the host, by overwriting the RSB completely. Both
 245  * retpoline and IBRS mitigations for Spectre v2 need this; only on future
 246  * CPUs with IBRS_ALL *might* it be avoided.
 247  */
 248 static inline void vmexit_fill_RSB(void)
 249 {
 250 #ifdef CONFIG_RETPOLINE
 251         unsigned long loops;
 252
 253         asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
 254                       ALTERNATIVE("jmp 910f",
 255                                   __stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
 256                                   X86_FEATURE_RETPOLINE)
 257                       "910:"
 258                       : "=r" (loops), ASM_CALL_CONSTRAINT
 259                       : : "memory" );
 260 #endif
 261 }
 262
 263 static __always_inline
 264 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 265 {
 266         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 267                 : : "c" (msr),
 268                     "a" ((u32)val),
 269                     "d" ((u32)(val >> 32)),
 270                     [feature] "i" (feature)
 271                 : "memory");
 272 }
 273
 274 static inline void indirect_branch_prediction_barrier(void)
 275 {
 276         u64 val = PRED_CMD_IBPB;
 277
 278         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 279 }
 280
 281 /* The Intel SPEC CTRL MSR base value cache */
 282 extern u64 x86_spec_ctrl_base;
 283
 284 /*
 285  * With retpoline, we must use IBRS to restrict branch prediction
 286  * before calling into firmware.
 287  *
 288  * (Implemented as CPP macros due to header hell.)
 289  */
 290 #define firmware_restrict_branch_speculation_start()                    \
 291 do {                                                                    \
 292         u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;                  \
 293                                                                         \
 294         preempt_disable();                                              \
 295         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 296                               X86_FEATURE_USE_IBRS_FW);                 \
 297 } while (0)
 298
 299 #define firmware_restrict_branch_speculation_end()                      \
 300 do {                                                                    \
 301         u64 val = x86_spec_ctrl_base;                                   \
 302                                                                         \
 303         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 304                               X86_FEATURE_USE_IBRS_FW);                 \
 305         preempt_enable();                                               \
 306 } while (0)
 307
 308 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 309 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 310 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 311
 312 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 313 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 314
 315 #include <asm/segment.h>
 316
 317 /**
 318  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 319  *
 320  * This uses the otherwise unused and obsolete VERW instruction in
 321  * combination with microcode which triggers a CPU buffer flush when the
 322  * instruction is executed.
 323  */
 324 static __always_inline void mds_clear_cpu_buffers(void)
 325 {
 326         static const u16 ds = __KERNEL_DS;
 327
 328         /*
 329          * Has to be the memory-operand variant because only that
 330          * guarantees the CPU buffer flush functionality according to
 331          * documentation. The register-operand variant does not.
 332          * Works with any segment selector, but a valid writable
 333          * data segment is the fastest variant.
 334          *
 335          * "cc" clobber is required because VERW modifies ZF.
 336          */
 337         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 338 }
 339
 340 /**
 341  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 342  *
 343  * Clear CPU buffers if the corresponding static key is enabled
 344  */
 345 static __always_inline void mds_user_clear_cpu_buffers(void)
 346 {
 347         if (static_branch_likely(&mds_user_clear))
 348                 mds_clear_cpu_buffers();
 349 }
 350
 351 /**
 352  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 353  *
 354  * Clear CPU buffers if the corresponding static key is enabled
 355  */
 356 static inline void mds_idle_clear_cpu_buffers(void)
 357 {
 358         if (static_branch_likely(&mds_idle_clear))
 359                 mds_clear_cpu_buffers();
 360 }
 361
 362 #endif /* __ASSEMBLY__ */
 363
 364 /*
 365  * Below is used in the eBPF JIT compiler and emits the byte sequence
 366  * for the following assembly:
 367  *
 368  * With retpolines configured:
 369  *
 370  *    callq do_rop
 371  *  spec_trap:
 372  *    pause
 373  *    lfence
 374  *    jmp spec_trap
 375  *  do_rop:
 376  *    mov %rax,(%rsp)
 377  *    retq
 378  *
 379  * Without retpolines configured:
 380  *
 381  *    jmp *%rax
 382  */
 383 #ifdef CONFIG_RETPOLINE
 384 # define RETPOLINE_RAX_BPF_JIT_SIZE     17
 385 # define RETPOLINE_RAX_BPF_JIT()                                \
 386         EMIT1_off32(0xE8, 7);    /* callq do_rop */             \
 387         /* spec_trap: */                                        \
 388         EMIT2(0xF3, 0x90);       /* pause */                    \
 389         EMIT3(0x0F, 0xAE, 0xE8); /* lfence */                   \
 390         EMIT2(0xEB, 0xF9);       /* jmp spec_trap */            \
 391         /* do_rop: */                                           \
 392         EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */    \
 393         EMIT1(0xC3);             /* retq */
 394 #else
 395 # define RETPOLINE_RAX_BPF_JIT_SIZE     2
 396 # define RETPOLINE_RAX_BPF_JIT()                                \
 397         EMIT2(0xFF, 0xE0);       /* jmp *%rax */
 398 #endif
 399
 400 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */