10 #include <asm/cpumask.h>
11 #include <uapi/asm/msr.h>
30 struct msr_regs_info {
42 struct saved_msr *array;
46 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
47 * constraint has different meanings. For i386, "A" means exactly
48 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
49 * it means rax *or* rdx.
52 /* Using 64-bit values saves one instruction clearing the high half of low */
53 #define DECLARE_ARGS(val, low, high) unsigned long low, high
54 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32)
55 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
57 #define DECLARE_ARGS(val, low, high) unsigned long long val
58 #define EAX_EDX_VAL(val, low, high) (val)
59 #define EAX_EDX_RET(val, low, high) "=A" (val)
62 #ifdef CONFIG_TRACEPOINTS
64 * Be very careful with includes. This header is prone to include loops.
66 #include <asm/atomic.h>
67 #include <linux/tracepoint-defs.h>
69 extern struct tracepoint __tracepoint_read_msr;
70 extern struct tracepoint __tracepoint_write_msr;
71 extern struct tracepoint __tracepoint_rdpmc;
72 #define msr_tracepoint_active(t) static_key_false(&(t).key)
73 extern void do_trace_write_msr(unsigned msr, u64 val, int failed);
74 extern void do_trace_read_msr(unsigned msr, u64 val, int failed);
75 extern void do_trace_rdpmc(unsigned msr, u64 val, int failed);
77 #define msr_tracepoint_active(t) false
78 static inline void do_trace_write_msr(unsigned msr, u64 val, int failed) {}
79 static inline void do_trace_read_msr(unsigned msr, u64 val, int failed) {}
80 static inline void do_trace_rdpmc(unsigned msr, u64 val, int failed) {}
83 static inline unsigned long long native_read_msr(unsigned int msr)
85 DECLARE_ARGS(val, low, high);
87 asm volatile("1: rdmsr\n"
89 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe)
90 : EAX_EDX_RET(val, low, high) : "c" (msr));
91 if (msr_tracepoint_active(__tracepoint_read_msr))
92 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), 0);
93 return EAX_EDX_VAL(val, low, high);
96 static inline unsigned long long native_read_msr_safe(unsigned int msr,
99 DECLARE_ARGS(val, low, high);
101 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
103 ".section .fixup,\"ax\"\n\t"
104 "3: mov %[fault],%[err]\n\t"
105 "xorl %%eax, %%eax\n\t"
106 "xorl %%edx, %%edx\n\t"
110 : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
111 : "c" (msr), [fault] "i" (-EIO));
112 if (msr_tracepoint_active(__tracepoint_read_msr))
113 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
114 return EAX_EDX_VAL(val, low, high);
117 /* Can be uninlined because referenced by paravirt */
118 notrace static inline void native_write_msr(unsigned int msr,
119 unsigned low, unsigned high)
121 asm volatile("1: wrmsr\n"
123 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
124 : : "c" (msr), "a"(low), "d" (high) : "memory");
125 if (msr_tracepoint_active(__tracepoint_write_msr))
126 do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
129 /* Can be uninlined because referenced by paravirt */
130 notrace static inline int native_write_msr_safe(unsigned int msr,
131 unsigned low, unsigned high)
134 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
136 ".section .fixup,\"ax\"\n\t"
137 "3: mov %[fault],%[err] ; jmp 1b\n\t"
141 : "c" (msr), "0" (low), "d" (high),
144 if (msr_tracepoint_active(__tracepoint_write_msr))
145 do_trace_write_msr(msr, ((u64)high << 32 | low), err);
149 extern int rdmsr_safe_regs(u32 regs[8]);
150 extern int wrmsr_safe_regs(u32 regs[8]);
153 * rdtsc() - returns the current TSC without ordering constraints
155 * rdtsc() returns the result of RDTSC as a 64-bit integer. The
156 * only ordering constraint it supplies is the ordering implied by
157 * "asm volatile": it will put the RDTSC in the place you expect. The
158 * CPU can and will speculatively execute that RDTSC, though, so the
159 * results can be non-monotonic if compared on different CPUs.
161 static __always_inline unsigned long long rdtsc(void)
163 DECLARE_ARGS(val, low, high);
165 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
167 return EAX_EDX_VAL(val, low, high);
171 * rdtsc_ordered() - read the current TSC in program order
173 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
174 * It is ordered like a load to a global in-memory counter. It should
175 * be impossible to observe non-monotonic rdtsc_unordered() behavior
176 * across multiple CPUs as long as the TSC is synced.
178 static __always_inline unsigned long long rdtsc_ordered(void)
181 * The RDTSC instruction is not ordered relative to memory
182 * access. The Intel SDM and the AMD APM are both vague on this
183 * point, but empirically an RDTSC instruction can be
184 * speculatively executed before prior loads. An RDTSC
185 * immediately after an appropriate barrier appears to be
186 * ordered as a normal load, that is, it provides the same
187 * ordering guarantees as reading from a global memory location
188 * that some other imaginary CPU is updating continuously with a
195 /* Deprecated, keep it for a cycle for easier merging: */
196 #define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0)
198 static inline unsigned long long native_read_pmc(int counter)
200 DECLARE_ARGS(val, low, high);
202 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
203 if (msr_tracepoint_active(__tracepoint_rdpmc))
204 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
205 return EAX_EDX_VAL(val, low, high);
208 #ifdef CONFIG_PARAVIRT
209 #include <asm/paravirt.h>
211 #include <linux/errno.h>
213 * Access to machine-specific registers (available on 586 and better only)
214 * Note: the rd* operations modify the parameters directly (without using
215 * pointer indirection), this allows gcc to optimize better
218 #define rdmsr(msr, low, high) \
220 u64 __val = native_read_msr((msr)); \
221 (void)((low) = (u32)__val); \
222 (void)((high) = (u32)(__val >> 32)); \
225 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
227 native_write_msr(msr, low, high);
230 #define rdmsrl(msr, val) \
231 ((val) = native_read_msr((msr)))
233 static inline void wrmsrl(unsigned msr, u64 val)
235 native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
238 /* wrmsr with exception handling */
239 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
241 return native_write_msr_safe(msr, low, high);
244 /* rdmsr with exception handling */
245 #define rdmsr_safe(msr, low, high) \
248 u64 __val = native_read_msr_safe((msr), &__err); \
249 (*low) = (u32)__val; \
250 (*high) = (u32)(__val >> 32); \
254 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
258 *p = native_read_msr_safe(msr, &err);
262 #define rdpmc(counter, low, high) \
264 u64 _l = native_read_pmc((counter)); \
266 (high) = (u32)(_l >> 32); \
269 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
271 #endif /* !CONFIG_PARAVIRT */
274 * 64-bit version of wrmsr_safe():
276 static inline int wrmsrl_safe(u32 msr, u64 val)
278 return wrmsr_safe(msr, (u32)val, (u32)(val >> 32));
281 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
283 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
285 struct msr *msrs_alloc(void);
286 void msrs_free(struct msr *msrs);
287 int msr_set_bit(u32 msr, u8 bit);
288 int msr_clear_bit(u32 msr, u8 bit);
291 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
292 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
293 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
294 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
295 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
296 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
297 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
298 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
299 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
300 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
301 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
302 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
303 #else /* CONFIG_SMP */
304 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
306 rdmsr(msr_no, *l, *h);
309 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
314 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
319 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
324 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
327 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
329 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
332 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
334 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
337 return rdmsr_safe(msr_no, l, h);
339 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
341 return wrmsr_safe(msr_no, l, h);
343 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
345 return rdmsrl_safe(msr_no, q);
347 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
349 return wrmsrl_safe(msr_no, q);
351 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
353 return rdmsr_safe_regs(regs);
355 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
357 return wrmsr_safe_regs(regs);
359 #endif /* CONFIG_SMP */
360 #endif /* __ASSEMBLY__ */
361 #endif /* _ASM_X86_MSR_H */