1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MSR_INDEX_H
3 #define _ASM_X86_MSR_INDEX_H
5 #include <linux/bits.h>
8 * CPU model specific register (MSR) numbers.
10 * Do not add new entries to this file unless the definitions are shared
11 * between multiple compilation units.
14 /* x86-64 specific MSRs */
15 #define MSR_EFER 0xc0000080 /* extended feature register */
16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
27 #define _EFER_LME 8 /* Long mode enable */
28 #define _EFER_LMA 10 /* Long mode active (read-only) */
29 #define _EFER_NX 11 /* No execute enable */
30 #define _EFER_SVME 12 /* Enable virtualization */
31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
34 #define EFER_SCE (1<<_EFER_SCE)
35 #define EFER_LME (1<<_EFER_LME)
36 #define EFER_LMA (1<<_EFER_LMA)
37 #define EFER_NX (1<<_EFER_NX)
38 #define EFER_SVME (1<<_EFER_SVME)
39 #define EFER_LMSLE (1<<_EFER_LMSLE)
40 #define EFER_FFXSR (1<<_EFER_FFXSR)
42 /* Intel MSRs. Some also available on other CPUs */
44 #define MSR_TEST_CTRL 0x00000033
45 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
46 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
50 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
51 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
52 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
53 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
54 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
55 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
57 /* A mask for bits which the kernel toggles when controlling mitigations */
58 #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
59 | SPEC_CTRL_RRSBA_DIS_S)
61 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
62 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
63 #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */
65 #define MSR_PPIN_CTL 0x0000004e
66 #define MSR_PPIN 0x0000004f
68 #define MSR_IA32_PERFCTR0 0x000000c1
69 #define MSR_IA32_PERFCTR1 0x000000c2
70 #define MSR_FSB_FREQ 0x000000cd
71 #define MSR_PLATFORM_INFO 0x000000ce
72 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
73 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
75 #define MSR_IA32_UMWAIT_CONTROL 0xe1
76 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
77 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
79 * The time field is bit[31:2], but representing a 32bit value with
82 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
84 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
85 #define MSR_IA32_CORE_CAPS 0x000000cf
86 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
87 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
89 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
90 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
91 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
92 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
93 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
94 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
96 #define MSR_MTRRcap 0x000000fe
98 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
99 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
100 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
101 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
102 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
103 #define ARCH_CAP_SSB_NO BIT(4) /*
104 * Not susceptible to Speculative Store Bypass
105 * attack, so no Speculative Store Bypass
108 #define ARCH_CAP_MDS_NO BIT(5) /*
110 * Microarchitectural Data
111 * Sampling (MDS) vulnerabilities.
113 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
114 * The processor is not susceptible to a
115 * machine check error due to modifying the
116 * code page size along with either the
117 * physical address or cache type
118 * without TLB invalidation.
120 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
121 #define ARCH_CAP_TAA_NO BIT(8) /*
123 * TSX Async Abort (TAA) vulnerabilities.
125 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /*
126 * Not susceptible to SBDR and SSDP
127 * variants of Processor MMIO stale data
130 #define ARCH_CAP_FBSDP_NO BIT(14) /*
131 * Not susceptible to FBSDP variant of
132 * Processor MMIO stale data
135 #define ARCH_CAP_PSDP_NO BIT(15) /*
136 * Not susceptible to PSDP variant of
137 * Processor MMIO stale data
140 #define ARCH_CAP_FB_CLEAR BIT(17) /*
141 * VERW clears CPU fill buffer
142 * even on MDS_NO CPUs.
144 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
145 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
146 * bit available to control VERW
149 #define ARCH_CAP_RRSBA BIT(19) /*
150 * Indicates RET may use predictors
151 * other than the RSB. With eIBRS
152 * enabled predictions in kernel mode
153 * are restricted to targets in
156 #define ARCH_CAP_PBRSB_NO BIT(24) /*
157 * Not susceptible to Post-Barrier
158 * Return Stack Buffer Predictions.
160 #define ARCH_CAP_GDS_CTRL BIT(25) /*
161 * CPU is vulnerable to Gather
162 * Data Sampling (GDS) and
163 * has controls for mitigation.
165 #define ARCH_CAP_GDS_NO BIT(26) /*
166 * CPU is not vulnerable to Gather
167 * Data Sampling (GDS).
170 #define MSR_IA32_FLUSH_CMD 0x0000010b
171 #define L1D_FLUSH BIT(0) /*
172 * Writeback and invalidate the
176 #define MSR_IA32_BBL_CR_CTL 0x00000119
177 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
179 #define MSR_IA32_TSX_CTRL 0x00000122
180 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
181 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
183 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
184 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
185 #define RTM_ALLOW BIT(1) /* TSX development mode */
186 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
187 #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */
188 #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */
190 #define MSR_IA32_SYSENTER_CS 0x00000174
191 #define MSR_IA32_SYSENTER_ESP 0x00000175
192 #define MSR_IA32_SYSENTER_EIP 0x00000176
194 #define MSR_IA32_MCG_CAP 0x00000179
195 #define MSR_IA32_MCG_STATUS 0x0000017a
196 #define MSR_IA32_MCG_CTL 0x0000017b
197 #define MSR_ERROR_CONTROL 0x0000017f
198 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
200 #define MSR_OFFCORE_RSP_0 0x000001a6
201 #define MSR_OFFCORE_RSP_1 0x000001a7
202 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
203 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
204 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
206 #define MSR_LBR_SELECT 0x000001c8
207 #define MSR_LBR_TOS 0x000001c9
209 #define MSR_IA32_POWER_CTL 0x000001fc
210 #define MSR_IA32_POWER_CTL_BIT_EE 19
212 #define MSR_LBR_NHM_FROM 0x00000680
213 #define MSR_LBR_NHM_TO 0x000006c0
214 #define MSR_LBR_CORE_FROM 0x00000040
215 #define MSR_LBR_CORE_TO 0x00000060
217 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
218 #define LBR_INFO_MISPRED BIT_ULL(63)
219 #define LBR_INFO_IN_TX BIT_ULL(62)
220 #define LBR_INFO_ABORT BIT_ULL(61)
221 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
222 #define LBR_INFO_CYCLES 0xffff
223 #define LBR_INFO_BR_TYPE_OFFSET 56
224 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
226 #define MSR_ARCH_LBR_CTL 0x000014ce
227 #define ARCH_LBR_CTL_LBREN BIT(0)
228 #define ARCH_LBR_CTL_CPL_OFFSET 1
229 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
230 #define ARCH_LBR_CTL_STACK_OFFSET 3
231 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
232 #define ARCH_LBR_CTL_FILTER_OFFSET 16
233 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
234 #define MSR_ARCH_LBR_DEPTH 0x000014cf
235 #define MSR_ARCH_LBR_FROM_0 0x00001500
236 #define MSR_ARCH_LBR_TO_0 0x00001600
237 #define MSR_ARCH_LBR_INFO_0 0x00001200
239 #define MSR_IA32_PEBS_ENABLE 0x000003f1
240 #define MSR_PEBS_DATA_CFG 0x000003f2
241 #define MSR_IA32_DS_AREA 0x00000600
242 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
243 #define PERF_CAP_METRICS_IDX 15
244 #define PERF_CAP_PT_IDX 16
246 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
248 #define MSR_IA32_RTIT_CTL 0x00000570
249 #define RTIT_CTL_TRACEEN BIT(0)
250 #define RTIT_CTL_CYCLEACC BIT(1)
251 #define RTIT_CTL_OS BIT(2)
252 #define RTIT_CTL_USR BIT(3)
253 #define RTIT_CTL_PWR_EVT_EN BIT(4)
254 #define RTIT_CTL_FUP_ON_PTW BIT(5)
255 #define RTIT_CTL_FABRIC_EN BIT(6)
256 #define RTIT_CTL_CR3EN BIT(7)
257 #define RTIT_CTL_TOPA BIT(8)
258 #define RTIT_CTL_MTC_EN BIT(9)
259 #define RTIT_CTL_TSC_EN BIT(10)
260 #define RTIT_CTL_DISRETC BIT(11)
261 #define RTIT_CTL_PTW_EN BIT(12)
262 #define RTIT_CTL_BRANCH_EN BIT(13)
263 #define RTIT_CTL_MTC_RANGE_OFFSET 14
264 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
265 #define RTIT_CTL_CYC_THRESH_OFFSET 19
266 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
267 #define RTIT_CTL_PSB_FREQ_OFFSET 24
268 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
269 #define RTIT_CTL_ADDR0_OFFSET 32
270 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
271 #define RTIT_CTL_ADDR1_OFFSET 36
272 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
273 #define RTIT_CTL_ADDR2_OFFSET 40
274 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
275 #define RTIT_CTL_ADDR3_OFFSET 44
276 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
277 #define MSR_IA32_RTIT_STATUS 0x00000571
278 #define RTIT_STATUS_FILTEREN BIT(0)
279 #define RTIT_STATUS_CONTEXTEN BIT(1)
280 #define RTIT_STATUS_TRIGGEREN BIT(2)
281 #define RTIT_STATUS_BUFFOVF BIT(3)
282 #define RTIT_STATUS_ERROR BIT(4)
283 #define RTIT_STATUS_STOPPED BIT(5)
284 #define RTIT_STATUS_BYTECNT_OFFSET 32
285 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
286 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
287 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
288 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
289 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
290 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
291 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
292 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
293 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
294 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
295 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
296 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
298 #define MSR_MTRRfix64K_00000 0x00000250
299 #define MSR_MTRRfix16K_80000 0x00000258
300 #define MSR_MTRRfix16K_A0000 0x00000259
301 #define MSR_MTRRfix4K_C0000 0x00000268
302 #define MSR_MTRRfix4K_C8000 0x00000269
303 #define MSR_MTRRfix4K_D0000 0x0000026a
304 #define MSR_MTRRfix4K_D8000 0x0000026b
305 #define MSR_MTRRfix4K_E0000 0x0000026c
306 #define MSR_MTRRfix4K_E8000 0x0000026d
307 #define MSR_MTRRfix4K_F0000 0x0000026e
308 #define MSR_MTRRfix4K_F8000 0x0000026f
309 #define MSR_MTRRdefType 0x000002ff
311 #define MSR_IA32_CR_PAT 0x00000277
313 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
314 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
315 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
316 #define MSR_IA32_LASTINTFROMIP 0x000001dd
317 #define MSR_IA32_LASTINTTOIP 0x000001de
319 #define MSR_IA32_PASID 0x00000d93
320 #define MSR_IA32_PASID_VALID BIT_ULL(31)
322 /* DEBUGCTLMSR bits (others vary by model): */
323 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
324 #define DEBUGCTLMSR_BTF_SHIFT 1
325 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
326 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
327 #define DEBUGCTLMSR_TR (1UL << 6)
328 #define DEBUGCTLMSR_BTS (1UL << 7)
329 #define DEBUGCTLMSR_BTINT (1UL << 8)
330 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
331 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
332 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
333 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
334 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
335 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
337 #define MSR_PEBS_FRONTEND 0x000003f7
339 #define MSR_IA32_MC0_CTL 0x00000400
340 #define MSR_IA32_MC0_STATUS 0x00000401
341 #define MSR_IA32_MC0_ADDR 0x00000402
342 #define MSR_IA32_MC0_MISC 0x00000403
344 /* C-state Residency Counters */
345 #define MSR_PKG_C3_RESIDENCY 0x000003f8
346 #define MSR_PKG_C6_RESIDENCY 0x000003f9
347 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
348 #define MSR_PKG_C7_RESIDENCY 0x000003fa
349 #define MSR_CORE_C3_RESIDENCY 0x000003fc
350 #define MSR_CORE_C6_RESIDENCY 0x000003fd
351 #define MSR_CORE_C7_RESIDENCY 0x000003fe
352 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
353 #define MSR_PKG_C2_RESIDENCY 0x0000060d
354 #define MSR_PKG_C8_RESIDENCY 0x00000630
355 #define MSR_PKG_C9_RESIDENCY 0x00000631
356 #define MSR_PKG_C10_RESIDENCY 0x00000632
358 /* Interrupt Response Limit */
359 #define MSR_PKGC3_IRTL 0x0000060a
360 #define MSR_PKGC6_IRTL 0x0000060b
361 #define MSR_PKGC7_IRTL 0x0000060c
362 #define MSR_PKGC8_IRTL 0x00000633
363 #define MSR_PKGC9_IRTL 0x00000634
364 #define MSR_PKGC10_IRTL 0x00000635
366 /* Run Time Average Power Limiting (RAPL) Interface */
368 #define MSR_RAPL_POWER_UNIT 0x00000606
370 #define MSR_PKG_POWER_LIMIT 0x00000610
371 #define MSR_PKG_ENERGY_STATUS 0x00000611
372 #define MSR_PKG_PERF_STATUS 0x00000613
373 #define MSR_PKG_POWER_INFO 0x00000614
375 #define MSR_DRAM_POWER_LIMIT 0x00000618
376 #define MSR_DRAM_ENERGY_STATUS 0x00000619
377 #define MSR_DRAM_PERF_STATUS 0x0000061b
378 #define MSR_DRAM_POWER_INFO 0x0000061c
380 #define MSR_PP0_POWER_LIMIT 0x00000638
381 #define MSR_PP0_ENERGY_STATUS 0x00000639
382 #define MSR_PP0_POLICY 0x0000063a
383 #define MSR_PP0_PERF_STATUS 0x0000063b
385 #define MSR_PP1_POWER_LIMIT 0x00000640
386 #define MSR_PP1_ENERGY_STATUS 0x00000641
387 #define MSR_PP1_POLICY 0x00000642
389 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
390 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
391 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
393 /* Config TDP MSRs */
394 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
395 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
396 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
397 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
398 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
400 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
402 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
403 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
404 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
405 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
407 #define MSR_CORE_C1_RES 0x00000660
408 #define MSR_MODULE_C6_RES_MS 0x00000664
410 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
411 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
413 #define MSR_ATOM_CORE_RATIOS 0x0000066a
414 #define MSR_ATOM_CORE_VIDS 0x0000066b
415 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
416 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
419 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
420 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
421 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
423 /* Hardware P state interface */
424 #define MSR_PPERF 0x0000064e
425 #define MSR_PERF_LIMIT_REASONS 0x0000064f
426 #define MSR_PM_ENABLE 0x00000770
427 #define MSR_HWP_CAPABILITIES 0x00000771
428 #define MSR_HWP_REQUEST_PKG 0x00000772
429 #define MSR_HWP_INTERRUPT 0x00000773
430 #define MSR_HWP_REQUEST 0x00000774
431 #define MSR_HWP_STATUS 0x00000777
434 #define HWP_BASE_BIT (1<<7)
435 #define HWP_NOTIFICATIONS_BIT (1<<8)
436 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
437 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
438 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
440 /* IA32_HWP_CAPABILITIES */
441 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
442 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
443 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
444 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
446 /* IA32_HWP_REQUEST */
447 #define HWP_MIN_PERF(x) (x & 0xff)
448 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
449 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
450 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
451 #define HWP_EPP_PERFORMANCE 0x00
452 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
453 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
454 #define HWP_EPP_POWERSAVE 0xFF
455 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
456 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
458 /* IA32_HWP_STATUS */
459 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
460 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
462 /* IA32_HWP_INTERRUPT */
463 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
464 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
466 #define MSR_AMD64_MC0_MASK 0xc0010044
468 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
469 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
470 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
471 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
473 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
475 /* These are consecutive and not in the normal 4er MCE bank block */
476 #define MSR_IA32_MC0_CTL2 0x00000280
477 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
479 #define MSR_P6_PERFCTR0 0x000000c1
480 #define MSR_P6_PERFCTR1 0x000000c2
481 #define MSR_P6_EVNTSEL0 0x00000186
482 #define MSR_P6_EVNTSEL1 0x00000187
484 #define MSR_KNC_PERFCTR0 0x00000020
485 #define MSR_KNC_PERFCTR1 0x00000021
486 #define MSR_KNC_EVNTSEL0 0x00000028
487 #define MSR_KNC_EVNTSEL1 0x00000029
489 /* Alternative perfctr range with full access. */
490 #define MSR_IA32_PMC0 0x000004c1
492 /* Auto-reload via MSR instead of DS area */
493 #define MSR_RELOAD_PMC0 0x000014c1
494 #define MSR_RELOAD_FIXED_CTR0 0x00001309
497 * AMD64 MSRs. Not complete. See the architecture manual for a more
500 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
501 #define MSR_AMD64_TSC_RATIO 0xc0000104
502 #define MSR_AMD64_NB_CFG 0xc001001f
503 #define MSR_AMD64_PATCH_LOADER 0xc0010020
504 #define MSR_AMD_PERF_CTL 0xc0010062
505 #define MSR_AMD_PERF_STATUS 0xc0010063
506 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
507 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
508 #define MSR_AMD64_OSVW_STATUS 0xc0010141
509 #define MSR_AMD_PPIN_CTL 0xc00102f0
510 #define MSR_AMD_PPIN 0xc00102f1
511 #define MSR_AMD64_CPUID_FN_1 0xc0011004
512 #define MSR_AMD64_LS_CFG 0xc0011020
513 #define MSR_AMD64_DC_CFG 0xc0011022
515 #define MSR_AMD64_DE_CFG 0xc0011029
516 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
517 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
518 #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
520 #define MSR_AMD64_BU_CFG2 0xc001102a
521 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
522 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
523 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
524 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
525 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
526 #define MSR_AMD64_IBSOPCTL 0xc0011033
527 #define MSR_AMD64_IBSOPRIP 0xc0011034
528 #define MSR_AMD64_IBSOPDATA 0xc0011035
529 #define MSR_AMD64_IBSOPDATA2 0xc0011036
530 #define MSR_AMD64_IBSOPDATA3 0xc0011037
531 #define MSR_AMD64_IBSDCLINAD 0xc0011038
532 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
533 #define MSR_AMD64_IBSOP_REG_COUNT 7
534 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
535 #define MSR_AMD64_IBSCTL 0xc001103a
536 #define MSR_AMD64_IBSBRTARGET 0xc001103b
537 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
538 #define MSR_AMD64_IBSOPDATA4 0xc001103d
539 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
540 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
541 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130
542 #define MSR_AMD64_SEV 0xc0010131
543 #define MSR_AMD64_SEV_ENABLED_BIT 0
544 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1
545 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
546 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
548 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
551 #define MSR_ZEN4_BP_CFG 0xc001102e
552 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
555 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
556 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
559 #define MSR_F17H_IRPERF 0xc00000e9
562 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
563 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
564 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
565 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
566 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
567 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
570 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
571 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
572 #define MSR_F15H_PERF_CTL 0xc0010200
573 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
574 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
575 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
576 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
577 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
578 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
580 #define MSR_F15H_PERF_CTR 0xc0010201
581 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
582 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
583 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
584 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
585 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
586 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
588 #define MSR_F15H_NB_PERF_CTL 0xc0010240
589 #define MSR_F15H_NB_PERF_CTR 0xc0010241
590 #define MSR_F15H_PTSC 0xc0010280
591 #define MSR_F15H_IC_CFG 0xc0011021
592 #define MSR_F15H_EX_CFG 0xc001102c
595 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
596 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
597 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
598 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
599 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
600 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
601 #define MSR_FAM10H_NODE_ID 0xc001100c
604 #define MSR_K8_TOP_MEM1 0xc001001a
605 #define MSR_K8_TOP_MEM2 0xc001001d
606 #define MSR_AMD64_SYSCFG 0xc0010010
607 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
608 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
609 #define MSR_K8_INT_PENDING_MSG 0xc0010055
610 /* C1E active bits in int pending message */
611 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
612 #define MSR_K8_TSEG_ADDR 0xc0010112
613 #define MSR_K8_TSEG_MASK 0xc0010113
614 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
615 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
616 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
619 #define MSR_K7_EVNTSEL0 0xc0010000
620 #define MSR_K7_PERFCTR0 0xc0010004
621 #define MSR_K7_EVNTSEL1 0xc0010001
622 #define MSR_K7_PERFCTR1 0xc0010005
623 #define MSR_K7_EVNTSEL2 0xc0010002
624 #define MSR_K7_PERFCTR2 0xc0010006
625 #define MSR_K7_EVNTSEL3 0xc0010003
626 #define MSR_K7_PERFCTR3 0xc0010007
627 #define MSR_K7_CLK_CTL 0xc001001b
628 #define MSR_K7_HWCR 0xc0010015
629 #define MSR_K7_HWCR_SMMLOCK_BIT 0
630 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
631 #define MSR_K7_HWCR_IRPERF_EN_BIT 30
632 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
633 #define MSR_K7_FID_VID_CTL 0xc0010041
634 #define MSR_K7_FID_VID_STATUS 0xc0010042
637 #define MSR_K6_WHCR 0xc0000082
638 #define MSR_K6_UWCCR 0xc0000085
639 #define MSR_K6_EPMR 0xc0000086
640 #define MSR_K6_PSOR 0xc0000087
641 #define MSR_K6_PFIR 0xc0000088
643 /* Centaur-Hauls/IDT defined MSRs. */
644 #define MSR_IDT_FCR1 0x00000107
645 #define MSR_IDT_FCR2 0x00000108
646 #define MSR_IDT_FCR3 0x00000109
647 #define MSR_IDT_FCR4 0x0000010a
649 #define MSR_IDT_MCR0 0x00000110
650 #define MSR_IDT_MCR1 0x00000111
651 #define MSR_IDT_MCR2 0x00000112
652 #define MSR_IDT_MCR3 0x00000113
653 #define MSR_IDT_MCR4 0x00000114
654 #define MSR_IDT_MCR5 0x00000115
655 #define MSR_IDT_MCR6 0x00000116
656 #define MSR_IDT_MCR7 0x00000117
657 #define MSR_IDT_MCR_CTRL 0x00000120
659 /* VIA Cyrix defined MSRs*/
660 #define MSR_VIA_FCR 0x00001107
661 #define MSR_VIA_LONGHAUL 0x0000110a
662 #define MSR_VIA_RNG 0x0000110b
663 #define MSR_VIA_BCR2 0x00001147
665 /* Transmeta defined MSRs */
666 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
667 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
668 #define MSR_TMTA_LRTI_READOUT 0x80868018
669 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
671 /* Intel defined MSRs. */
672 #define MSR_IA32_P5_MC_ADDR 0x00000000
673 #define MSR_IA32_P5_MC_TYPE 0x00000001
674 #define MSR_IA32_TSC 0x00000010
675 #define MSR_IA32_PLATFORM_ID 0x00000017
676 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
677 #define MSR_EBC_FREQUENCY_ID 0x0000002c
678 #define MSR_SMI_COUNT 0x00000034
680 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
681 #define MSR_IA32_FEAT_CTL 0x0000003a
682 #define FEAT_CTL_LOCKED BIT(0)
683 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
684 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
685 #define FEAT_CTL_SGX_LC_ENABLED BIT(17)
686 #define FEAT_CTL_SGX_ENABLED BIT(18)
687 #define FEAT_CTL_LMCE_ENABLED BIT(20)
689 #define MSR_IA32_TSC_ADJUST 0x0000003b
690 #define MSR_IA32_BNDCFGS 0x00000d90
692 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
694 #define MSR_IA32_XSS 0x00000da0
696 #define MSR_IA32_APICBASE 0x0000001b
697 #define MSR_IA32_APICBASE_BSP (1<<8)
698 #define MSR_IA32_APICBASE_ENABLE (1<<11)
699 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
701 #define MSR_IA32_UCODE_WRITE 0x00000079
702 #define MSR_IA32_UCODE_REV 0x0000008b
704 /* Intel SGX Launch Enclave Public Key Hash MSRs */
705 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
706 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
707 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
708 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
710 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
711 #define MSR_IA32_SMBASE 0x0000009e
713 #define MSR_IA32_PERF_STATUS 0x00000198
714 #define MSR_IA32_PERF_CTL 0x00000199
715 #define INTEL_PERF_CTL_MASK 0xffff
717 #define MSR_IA32_MPERF 0x000000e7
718 #define MSR_IA32_APERF 0x000000e8
720 #define MSR_IA32_THERM_CONTROL 0x0000019a
721 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
723 #define THERM_INT_HIGH_ENABLE (1 << 0)
724 #define THERM_INT_LOW_ENABLE (1 << 1)
725 #define THERM_INT_PLN_ENABLE (1 << 24)
727 #define MSR_IA32_THERM_STATUS 0x0000019c
729 #define THERM_STATUS_PROCHOT (1 << 0)
730 #define THERM_STATUS_POWER_LIMIT (1 << 10)
732 #define MSR_THERM2_CTL 0x0000019d
734 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
736 #define MSR_IA32_MISC_ENABLE 0x000001a0
738 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
740 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
741 #define MSR_MISC_PWR_MGMT 0x000001aa
743 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
744 #define ENERGY_PERF_BIAS_PERFORMANCE 0
745 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
746 #define ENERGY_PERF_BIAS_NORMAL 6
747 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
748 #define ENERGY_PERF_BIAS_POWERSAVE 15
750 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
752 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
753 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
755 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
757 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
758 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
759 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
761 /* Thermal Thresholds Support */
762 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
763 #define THERM_SHIFT_THRESHOLD0 8
764 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
765 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
766 #define THERM_SHIFT_THRESHOLD1 16
767 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
768 #define THERM_STATUS_THRESHOLD0 (1 << 6)
769 #define THERM_LOG_THRESHOLD0 (1 << 7)
770 #define THERM_STATUS_THRESHOLD1 (1 << 8)
771 #define THERM_LOG_THRESHOLD1 (1 << 9)
773 /* MISC_ENABLE bits: architectural */
774 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
775 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
776 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
777 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
778 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
779 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
780 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
781 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
782 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
783 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
784 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
785 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
786 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
787 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
788 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
789 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
790 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
791 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
792 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
793 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
795 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
796 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
797 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
798 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
799 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
800 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
801 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
802 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
803 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
804 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
805 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
806 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
807 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
808 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
809 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
810 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
811 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
812 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
813 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
814 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
815 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
816 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
817 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
818 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
819 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
820 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
821 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
822 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
823 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
824 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
825 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
827 /* MISC_FEATURES_ENABLES non-architectural features */
828 #define MSR_MISC_FEATURES_ENABLES 0x00000140
830 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
831 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
832 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
834 #define MSR_IA32_TSC_DEADLINE 0x000006E0
837 #define MSR_TSX_FORCE_ABORT 0x0000010F
839 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
840 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
841 #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
842 #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
843 #define MSR_TFA_SDV_ENABLE_RTM_BIT 2
844 #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
846 /* P4/Xeon+ specific */
847 #define MSR_IA32_MCG_EAX 0x00000180
848 #define MSR_IA32_MCG_EBX 0x00000181
849 #define MSR_IA32_MCG_ECX 0x00000182
850 #define MSR_IA32_MCG_EDX 0x00000183
851 #define MSR_IA32_MCG_ESI 0x00000184
852 #define MSR_IA32_MCG_EDI 0x00000185
853 #define MSR_IA32_MCG_EBP 0x00000186
854 #define MSR_IA32_MCG_ESP 0x00000187
855 #define MSR_IA32_MCG_EFLAGS 0x00000188
856 #define MSR_IA32_MCG_EIP 0x00000189
857 #define MSR_IA32_MCG_RESERVED 0x0000018a
859 /* Pentium IV performance counter MSRs */
860 #define MSR_P4_BPU_PERFCTR0 0x00000300
861 #define MSR_P4_BPU_PERFCTR1 0x00000301
862 #define MSR_P4_BPU_PERFCTR2 0x00000302
863 #define MSR_P4_BPU_PERFCTR3 0x00000303
864 #define MSR_P4_MS_PERFCTR0 0x00000304
865 #define MSR_P4_MS_PERFCTR1 0x00000305
866 #define MSR_P4_MS_PERFCTR2 0x00000306
867 #define MSR_P4_MS_PERFCTR3 0x00000307
868 #define MSR_P4_FLAME_PERFCTR0 0x00000308
869 #define MSR_P4_FLAME_PERFCTR1 0x00000309
870 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
871 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
872 #define MSR_P4_IQ_PERFCTR0 0x0000030c
873 #define MSR_P4_IQ_PERFCTR1 0x0000030d
874 #define MSR_P4_IQ_PERFCTR2 0x0000030e
875 #define MSR_P4_IQ_PERFCTR3 0x0000030f
876 #define MSR_P4_IQ_PERFCTR4 0x00000310
877 #define MSR_P4_IQ_PERFCTR5 0x00000311
878 #define MSR_P4_BPU_CCCR0 0x00000360
879 #define MSR_P4_BPU_CCCR1 0x00000361
880 #define MSR_P4_BPU_CCCR2 0x00000362
881 #define MSR_P4_BPU_CCCR3 0x00000363
882 #define MSR_P4_MS_CCCR0 0x00000364
883 #define MSR_P4_MS_CCCR1 0x00000365
884 #define MSR_P4_MS_CCCR2 0x00000366
885 #define MSR_P4_MS_CCCR3 0x00000367
886 #define MSR_P4_FLAME_CCCR0 0x00000368
887 #define MSR_P4_FLAME_CCCR1 0x00000369
888 #define MSR_P4_FLAME_CCCR2 0x0000036a
889 #define MSR_P4_FLAME_CCCR3 0x0000036b
890 #define MSR_P4_IQ_CCCR0 0x0000036c
891 #define MSR_P4_IQ_CCCR1 0x0000036d
892 #define MSR_P4_IQ_CCCR2 0x0000036e
893 #define MSR_P4_IQ_CCCR3 0x0000036f
894 #define MSR_P4_IQ_CCCR4 0x00000370
895 #define MSR_P4_IQ_CCCR5 0x00000371
896 #define MSR_P4_ALF_ESCR0 0x000003ca
897 #define MSR_P4_ALF_ESCR1 0x000003cb
898 #define MSR_P4_BPU_ESCR0 0x000003b2
899 #define MSR_P4_BPU_ESCR1 0x000003b3
900 #define MSR_P4_BSU_ESCR0 0x000003a0
901 #define MSR_P4_BSU_ESCR1 0x000003a1
902 #define MSR_P4_CRU_ESCR0 0x000003b8
903 #define MSR_P4_CRU_ESCR1 0x000003b9
904 #define MSR_P4_CRU_ESCR2 0x000003cc
905 #define MSR_P4_CRU_ESCR3 0x000003cd
906 #define MSR_P4_CRU_ESCR4 0x000003e0
907 #define MSR_P4_CRU_ESCR5 0x000003e1
908 #define MSR_P4_DAC_ESCR0 0x000003a8
909 #define MSR_P4_DAC_ESCR1 0x000003a9
910 #define MSR_P4_FIRM_ESCR0 0x000003a4
911 #define MSR_P4_FIRM_ESCR1 0x000003a5
912 #define MSR_P4_FLAME_ESCR0 0x000003a6
913 #define MSR_P4_FLAME_ESCR1 0x000003a7
914 #define MSR_P4_FSB_ESCR0 0x000003a2
915 #define MSR_P4_FSB_ESCR1 0x000003a3
916 #define MSR_P4_IQ_ESCR0 0x000003ba
917 #define MSR_P4_IQ_ESCR1 0x000003bb
918 #define MSR_P4_IS_ESCR0 0x000003b4
919 #define MSR_P4_IS_ESCR1 0x000003b5
920 #define MSR_P4_ITLB_ESCR0 0x000003b6
921 #define MSR_P4_ITLB_ESCR1 0x000003b7
922 #define MSR_P4_IX_ESCR0 0x000003c8
923 #define MSR_P4_IX_ESCR1 0x000003c9
924 #define MSR_P4_MOB_ESCR0 0x000003aa
925 #define MSR_P4_MOB_ESCR1 0x000003ab
926 #define MSR_P4_MS_ESCR0 0x000003c0
927 #define MSR_P4_MS_ESCR1 0x000003c1
928 #define MSR_P4_PMH_ESCR0 0x000003ac
929 #define MSR_P4_PMH_ESCR1 0x000003ad
930 #define MSR_P4_RAT_ESCR0 0x000003bc
931 #define MSR_P4_RAT_ESCR1 0x000003bd
932 #define MSR_P4_SAAT_ESCR0 0x000003ae
933 #define MSR_P4_SAAT_ESCR1 0x000003af
934 #define MSR_P4_SSU_ESCR0 0x000003be
935 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
937 #define MSR_P4_TBPU_ESCR0 0x000003c2
938 #define MSR_P4_TBPU_ESCR1 0x000003c3
939 #define MSR_P4_TC_ESCR0 0x000003c4
940 #define MSR_P4_TC_ESCR1 0x000003c5
941 #define MSR_P4_U2L_ESCR0 0x000003b0
942 #define MSR_P4_U2L_ESCR1 0x000003b1
944 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
946 /* Intel Core-based CPU performance counters */
947 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
948 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
949 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
950 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
951 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
952 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
953 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
954 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
956 #define MSR_PERF_METRICS 0x00000329
958 /* PERF_GLOBAL_OVF_CTL bits */
959 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
960 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
961 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
962 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
963 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
964 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
966 /* Geode defined MSRs */
967 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
970 #define MSR_IA32_VMX_BASIC 0x00000480
971 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
972 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
973 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
974 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
975 #define MSR_IA32_VMX_MISC 0x00000485
976 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
977 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
978 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
979 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
980 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
981 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
982 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
983 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
984 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
985 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
986 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
987 #define MSR_IA32_VMX_VMFUNC 0x00000491
989 /* VMX_BASIC bits and bitmasks */
990 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
991 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
992 #define VMX_BASIC_64 0x0001000000000000LLU
993 #define VMX_BASIC_MEM_TYPE_SHIFT 50
994 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
995 #define VMX_BASIC_MEM_TYPE_WB 6LLU
996 #define VMX_BASIC_INOUT 0x0040000000000000LLU
998 /* MSR_IA32_VMX_MISC bits */
999 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
1000 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
1001 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
1004 #define MSR_VM_CR 0xc0010114
1005 #define MSR_VM_IGNNE 0xc0010115
1006 #define MSR_VM_HSAVE_PA 0xc0010117
1008 #endif /* _ASM_X86_MSR_INDEX_H */