1 #ifndef _ASM_X86_MSR_INDEX_H
2 #define _ASM_X86_MSR_INDEX_H
4 #include <linux/bits.h>
7 * CPU model specific register (MSR) numbers.
9 * Do not add new entries to this file unless the definitions are shared
10 * between multiple compilation units.
13 /* x86-64 specific MSRs */
14 #define MSR_EFER 0xc0000080 /* extended feature register */
15 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
16 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
17 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
18 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
19 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
20 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
21 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
22 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
25 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
26 #define _EFER_LME 8 /* Long mode enable */
27 #define _EFER_LMA 10 /* Long mode active (read-only) */
28 #define _EFER_NX 11 /* No execute enable */
29 #define _EFER_SVME 12 /* Enable virtualization */
30 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
31 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
33 #define EFER_SCE (1<<_EFER_SCE)
34 #define EFER_LME (1<<_EFER_LME)
35 #define EFER_LMA (1<<_EFER_LMA)
36 #define EFER_NX (1<<_EFER_NX)
37 #define EFER_SVME (1<<_EFER_SVME)
38 #define EFER_LMSLE (1<<_EFER_LMSLE)
39 #define EFER_FFXSR (1<<_EFER_FFXSR)
41 /* Intel MSRs. Some also available on other CPUs */
42 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
43 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
44 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
45 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
46 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
47 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
49 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
50 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
52 #define MSR_IA32_PERFCTR0 0x000000c1
53 #define MSR_IA32_PERFCTR1 0x000000c2
54 #define MSR_FSB_FREQ 0x000000cd
55 #define MSR_PLATFORM_INFO 0x000000ce
57 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
58 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
59 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
60 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
61 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
62 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
64 #define MSR_MTRRcap 0x000000fe
66 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
67 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
68 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
69 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
70 #define ARCH_CAP_SSB_NO BIT(4) /*
71 * Not susceptible to Speculative Store Bypass
72 * attack, so no Speculative Store Bypass
75 #define ARCH_CAP_MDS_NO BIT(5) /*
77 * Microarchitectural Data
78 * Sampling (MDS) vulnerabilities.
80 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
81 * The processor is not susceptible to a
82 * machine check error due to modifying the
83 * code page size along with either the
84 * physical address or cache type
85 * without TLB invalidation.
87 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
88 #define ARCH_CAP_TAA_NO BIT(8) /*
90 * TSX Async Abort (TAA) vulnerabilities.
92 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /*
93 * Not susceptible to SBDR and SSDP
94 * variants of Processor MMIO stale data
97 #define ARCH_CAP_FBSDP_NO BIT(14) /*
98 * Not susceptible to FBSDP variant of
99 * Processor MMIO stale data
102 #define ARCH_CAP_PSDP_NO BIT(15) /*
103 * Not susceptible to PSDP variant of
104 * Processor MMIO stale data
107 #define ARCH_CAP_FB_CLEAR BIT(17) /*
108 * VERW clears CPU fill buffer
109 * even on MDS_NO CPUs.
111 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
112 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
113 * bit available to control VERW
117 #define MSR_IA32_FLUSH_CMD 0x0000010b
118 #define L1D_FLUSH BIT(0) /*
119 * Writeback and invalidate the
123 #define MSR_IA32_BBL_CR_CTL 0x00000119
124 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
126 #define MSR_IA32_TSX_CTRL 0x00000122
127 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
128 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
131 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
132 #define RNGDS_MITG_DIS BIT(0)
133 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
135 #define MSR_IA32_SYSENTER_CS 0x00000174
136 #define MSR_IA32_SYSENTER_ESP 0x00000175
137 #define MSR_IA32_SYSENTER_EIP 0x00000176
139 #define MSR_IA32_MCG_CAP 0x00000179
140 #define MSR_IA32_MCG_STATUS 0x0000017a
141 #define MSR_IA32_MCG_CTL 0x0000017b
142 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
144 #define MSR_OFFCORE_RSP_0 0x000001a6
145 #define MSR_OFFCORE_RSP_1 0x000001a7
146 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
147 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
148 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
150 #define MSR_LBR_SELECT 0x000001c8
151 #define MSR_LBR_TOS 0x000001c9
152 #define MSR_LBR_NHM_FROM 0x00000680
153 #define MSR_LBR_NHM_TO 0x000006c0
154 #define MSR_LBR_CORE_FROM 0x00000040
155 #define MSR_LBR_CORE_TO 0x00000060
157 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
158 #define LBR_INFO_MISPRED BIT_ULL(63)
159 #define LBR_INFO_IN_TX BIT_ULL(62)
160 #define LBR_INFO_ABORT BIT_ULL(61)
161 #define LBR_INFO_CYCLES 0xffff
163 #define MSR_IA32_PEBS_ENABLE 0x000003f1
164 #define MSR_IA32_DS_AREA 0x00000600
165 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
166 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
168 #define MSR_IA32_RTIT_CTL 0x00000570
169 #define MSR_IA32_RTIT_STATUS 0x00000571
170 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
171 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
172 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
173 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
174 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
175 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
176 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
177 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
178 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
179 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
180 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
182 #define MSR_MTRRfix64K_00000 0x00000250
183 #define MSR_MTRRfix16K_80000 0x00000258
184 #define MSR_MTRRfix16K_A0000 0x00000259
185 #define MSR_MTRRfix4K_C0000 0x00000268
186 #define MSR_MTRRfix4K_C8000 0x00000269
187 #define MSR_MTRRfix4K_D0000 0x0000026a
188 #define MSR_MTRRfix4K_D8000 0x0000026b
189 #define MSR_MTRRfix4K_E0000 0x0000026c
190 #define MSR_MTRRfix4K_E8000 0x0000026d
191 #define MSR_MTRRfix4K_F0000 0x0000026e
192 #define MSR_MTRRfix4K_F8000 0x0000026f
193 #define MSR_MTRRdefType 0x000002ff
195 #define MSR_IA32_CR_PAT 0x00000277
197 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
198 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
199 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
200 #define MSR_IA32_LASTINTFROMIP 0x000001dd
201 #define MSR_IA32_LASTINTTOIP 0x000001de
203 /* DEBUGCTLMSR bits (others vary by model): */
204 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
205 #define DEBUGCTLMSR_BTF_SHIFT 1
206 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
207 #define DEBUGCTLMSR_TR (1UL << 6)
208 #define DEBUGCTLMSR_BTS (1UL << 7)
209 #define DEBUGCTLMSR_BTINT (1UL << 8)
210 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
211 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
212 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
214 #define MSR_PEBS_FRONTEND 0x000003f7
216 #define MSR_IA32_POWER_CTL 0x000001fc
218 #define MSR_IA32_MC0_CTL 0x00000400
219 #define MSR_IA32_MC0_STATUS 0x00000401
220 #define MSR_IA32_MC0_ADDR 0x00000402
221 #define MSR_IA32_MC0_MISC 0x00000403
223 /* C-state Residency Counters */
224 #define MSR_PKG_C3_RESIDENCY 0x000003f8
225 #define MSR_PKG_C6_RESIDENCY 0x000003f9
226 #define MSR_PKG_C7_RESIDENCY 0x000003fa
227 #define MSR_CORE_C3_RESIDENCY 0x000003fc
228 #define MSR_CORE_C6_RESIDENCY 0x000003fd
229 #define MSR_CORE_C7_RESIDENCY 0x000003fe
230 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
231 #define MSR_PKG_C2_RESIDENCY 0x0000060d
232 #define MSR_PKG_C8_RESIDENCY 0x00000630
233 #define MSR_PKG_C9_RESIDENCY 0x00000631
234 #define MSR_PKG_C10_RESIDENCY 0x00000632
236 /* Interrupt Response Limit */
237 #define MSR_PKGC3_IRTL 0x0000060a
238 #define MSR_PKGC6_IRTL 0x0000060b
239 #define MSR_PKGC7_IRTL 0x0000060c
240 #define MSR_PKGC8_IRTL 0x00000633
241 #define MSR_PKGC9_IRTL 0x00000634
242 #define MSR_PKGC10_IRTL 0x00000635
244 /* Run Time Average Power Limiting (RAPL) Interface */
246 #define MSR_RAPL_POWER_UNIT 0x00000606
248 #define MSR_PKG_POWER_LIMIT 0x00000610
249 #define MSR_PKG_ENERGY_STATUS 0x00000611
250 #define MSR_PKG_PERF_STATUS 0x00000613
251 #define MSR_PKG_POWER_INFO 0x00000614
253 #define MSR_DRAM_POWER_LIMIT 0x00000618
254 #define MSR_DRAM_ENERGY_STATUS 0x00000619
255 #define MSR_DRAM_PERF_STATUS 0x0000061b
256 #define MSR_DRAM_POWER_INFO 0x0000061c
258 #define MSR_PP0_POWER_LIMIT 0x00000638
259 #define MSR_PP0_ENERGY_STATUS 0x00000639
260 #define MSR_PP0_POLICY 0x0000063a
261 #define MSR_PP0_PERF_STATUS 0x0000063b
263 #define MSR_PP1_POWER_LIMIT 0x00000640
264 #define MSR_PP1_ENERGY_STATUS 0x00000641
265 #define MSR_PP1_POLICY 0x00000642
267 /* Config TDP MSRs */
268 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
269 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
270 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
271 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
272 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
274 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
276 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
277 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
278 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
279 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
281 #define MSR_CORE_C1_RES 0x00000660
283 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
284 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
286 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
287 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
288 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
290 /* Hardware P state interface */
291 #define MSR_PPERF 0x0000064e
292 #define MSR_PERF_LIMIT_REASONS 0x0000064f
293 #define MSR_PM_ENABLE 0x00000770
294 #define MSR_HWP_CAPABILITIES 0x00000771
295 #define MSR_HWP_REQUEST_PKG 0x00000772
296 #define MSR_HWP_INTERRUPT 0x00000773
297 #define MSR_HWP_REQUEST 0x00000774
298 #define MSR_HWP_STATUS 0x00000777
301 #define HWP_BASE_BIT (1<<7)
302 #define HWP_NOTIFICATIONS_BIT (1<<8)
303 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
304 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
305 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
307 /* IA32_HWP_CAPABILITIES */
308 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
309 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
310 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
311 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
313 /* IA32_HWP_REQUEST */
314 #define HWP_MIN_PERF(x) (x & 0xff)
315 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
316 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
317 #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24)
318 #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32)
319 #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)
321 /* IA32_HWP_STATUS */
322 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
323 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
325 /* IA32_HWP_INTERRUPT */
326 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
327 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
329 #define MSR_AMD64_MC0_MASK 0xc0010044
331 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
332 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
333 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
334 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
336 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
338 /* These are consecutive and not in the normal 4er MCE bank block */
339 #define MSR_IA32_MC0_CTL2 0x00000280
340 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
342 #define MSR_P6_PERFCTR0 0x000000c1
343 #define MSR_P6_PERFCTR1 0x000000c2
344 #define MSR_P6_EVNTSEL0 0x00000186
345 #define MSR_P6_EVNTSEL1 0x00000187
347 #define MSR_KNC_PERFCTR0 0x00000020
348 #define MSR_KNC_PERFCTR1 0x00000021
349 #define MSR_KNC_EVNTSEL0 0x00000028
350 #define MSR_KNC_EVNTSEL1 0x00000029
352 /* Alternative perfctr range with full access. */
353 #define MSR_IA32_PMC0 0x000004c1
355 /* AMD64 MSRs. Not complete. See the architecture manual for a more
358 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
359 #define MSR_AMD64_TSC_RATIO 0xc0000104
360 #define MSR_AMD64_NB_CFG 0xc001001f
361 #define MSR_AMD64_CPUID_FN_1 0xc0011004
362 #define MSR_AMD64_PATCH_LOADER 0xc0010020
363 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
364 #define MSR_AMD64_OSVW_STATUS 0xc0010141
365 #define MSR_AMD64_LS_CFG 0xc0011020
366 #define MSR_AMD64_DC_CFG 0xc0011022
367 #define MSR_AMD64_BU_CFG2 0xc001102a
368 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
369 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
370 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
371 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
372 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
373 #define MSR_AMD64_IBSOPCTL 0xc0011033
374 #define MSR_AMD64_IBSOPRIP 0xc0011034
375 #define MSR_AMD64_IBSOPDATA 0xc0011035
376 #define MSR_AMD64_IBSOPDATA2 0xc0011036
377 #define MSR_AMD64_IBSOPDATA3 0xc0011037
378 #define MSR_AMD64_IBSDCLINAD 0xc0011038
379 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
380 #define MSR_AMD64_IBSOP_REG_COUNT 7
381 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
382 #define MSR_AMD64_IBSCTL 0xc001103a
383 #define MSR_AMD64_IBSBRTARGET 0xc001103b
384 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
385 #define MSR_AMD64_IBSOPDATA4 0xc001103d
386 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
388 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
391 #define MSR_F17H_IRPERF 0xc00000e9
394 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
395 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
396 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
397 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
398 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
399 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
402 #define MSR_F15H_PERF_CTL 0xc0010200
403 #define MSR_F15H_PERF_CTR 0xc0010201
404 #define MSR_F15H_NB_PERF_CTL 0xc0010240
405 #define MSR_F15H_NB_PERF_CTR 0xc0010241
406 #define MSR_F15H_PTSC 0xc0010280
407 #define MSR_F15H_IC_CFG 0xc0011021
410 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
411 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
412 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
413 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
414 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
415 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
416 #define MSR_FAM10H_NODE_ID 0xc001100c
417 #define MSR_F10H_DECFG 0xc0011029
418 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
419 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
422 #define MSR_K8_TOP_MEM1 0xc001001a
423 #define MSR_K8_TOP_MEM2 0xc001001d
424 #define MSR_K8_SYSCFG 0xc0010010
425 #define MSR_K8_INT_PENDING_MSG 0xc0010055
426 /* C1E active bits in int pending message */
427 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
428 #define MSR_K8_TSEG_ADDR 0xc0010112
429 #define MSR_K8_TSEG_MASK 0xc0010113
430 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
431 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
432 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
435 #define MSR_K7_EVNTSEL0 0xc0010000
436 #define MSR_K7_PERFCTR0 0xc0010004
437 #define MSR_K7_EVNTSEL1 0xc0010001
438 #define MSR_K7_PERFCTR1 0xc0010005
439 #define MSR_K7_EVNTSEL2 0xc0010002
440 #define MSR_K7_PERFCTR2 0xc0010006
441 #define MSR_K7_EVNTSEL3 0xc0010003
442 #define MSR_K7_PERFCTR3 0xc0010007
443 #define MSR_K7_CLK_CTL 0xc001001b
444 #define MSR_K7_HWCR 0xc0010015
445 #define MSR_K7_FID_VID_CTL 0xc0010041
446 #define MSR_K7_FID_VID_STATUS 0xc0010042
449 #define MSR_K6_WHCR 0xc0000082
450 #define MSR_K6_UWCCR 0xc0000085
451 #define MSR_K6_EPMR 0xc0000086
452 #define MSR_K6_PSOR 0xc0000087
453 #define MSR_K6_PFIR 0xc0000088
455 /* Centaur-Hauls/IDT defined MSRs. */
456 #define MSR_IDT_FCR1 0x00000107
457 #define MSR_IDT_FCR2 0x00000108
458 #define MSR_IDT_FCR3 0x00000109
459 #define MSR_IDT_FCR4 0x0000010a
461 #define MSR_IDT_MCR0 0x00000110
462 #define MSR_IDT_MCR1 0x00000111
463 #define MSR_IDT_MCR2 0x00000112
464 #define MSR_IDT_MCR3 0x00000113
465 #define MSR_IDT_MCR4 0x00000114
466 #define MSR_IDT_MCR5 0x00000115
467 #define MSR_IDT_MCR6 0x00000116
468 #define MSR_IDT_MCR7 0x00000117
469 #define MSR_IDT_MCR_CTRL 0x00000120
471 /* VIA Cyrix defined MSRs*/
472 #define MSR_VIA_FCR 0x00001107
473 #define MSR_VIA_LONGHAUL 0x0000110a
474 #define MSR_VIA_RNG 0x0000110b
475 #define MSR_VIA_BCR2 0x00001147
477 /* Transmeta defined MSRs */
478 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
479 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
480 #define MSR_TMTA_LRTI_READOUT 0x80868018
481 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
483 /* Intel defined MSRs. */
484 #define MSR_IA32_P5_MC_ADDR 0x00000000
485 #define MSR_IA32_P5_MC_TYPE 0x00000001
486 #define MSR_IA32_TSC 0x00000010
487 #define MSR_IA32_PLATFORM_ID 0x00000017
488 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
489 #define MSR_EBC_FREQUENCY_ID 0x0000002c
490 #define MSR_SMI_COUNT 0x00000034
491 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
492 #define MSR_IA32_TSC_ADJUST 0x0000003b
493 #define MSR_IA32_BNDCFGS 0x00000d90
495 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
497 #define MSR_IA32_XSS 0x00000da0
499 #define FEATURE_CONTROL_LOCKED (1<<0)
500 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
501 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
502 #define FEATURE_CONTROL_LMCE (1<<20)
504 #define MSR_IA32_APICBASE 0x0000001b
505 #define MSR_IA32_APICBASE_BSP (1<<8)
506 #define MSR_IA32_APICBASE_ENABLE (1<<11)
507 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
509 #define MSR_IA32_TSCDEADLINE 0x000006e0
511 #define MSR_IA32_UCODE_WRITE 0x00000079
512 #define MSR_IA32_UCODE_REV 0x0000008b
514 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
515 #define MSR_IA32_SMBASE 0x0000009e
517 #define MSR_IA32_PERF_STATUS 0x00000198
518 #define MSR_IA32_PERF_CTL 0x00000199
519 #define INTEL_PERF_CTL_MASK 0xffff
520 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
521 #define MSR_AMD_PERF_STATUS 0xc0010063
522 #define MSR_AMD_PERF_CTL 0xc0010062
524 #define MSR_IA32_MPERF 0x000000e7
525 #define MSR_IA32_APERF 0x000000e8
527 #define MSR_IA32_THERM_CONTROL 0x0000019a
528 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
530 #define THERM_INT_HIGH_ENABLE (1 << 0)
531 #define THERM_INT_LOW_ENABLE (1 << 1)
532 #define THERM_INT_PLN_ENABLE (1 << 24)
534 #define MSR_IA32_THERM_STATUS 0x0000019c
536 #define THERM_STATUS_PROCHOT (1 << 0)
537 #define THERM_STATUS_POWER_LIMIT (1 << 10)
539 #define MSR_THERM2_CTL 0x0000019d
541 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
543 #define MSR_IA32_MISC_ENABLE 0x000001a0
545 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
547 #define MSR_MISC_PWR_MGMT 0x000001aa
549 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
550 #define ENERGY_PERF_BIAS_PERFORMANCE 0
551 #define ENERGY_PERF_BIAS_NORMAL 6
552 #define ENERGY_PERF_BIAS_POWERSAVE 15
554 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
556 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
557 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
559 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
561 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
562 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
563 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
565 /* Thermal Thresholds Support */
566 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
567 #define THERM_SHIFT_THRESHOLD0 8
568 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
569 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
570 #define THERM_SHIFT_THRESHOLD1 16
571 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
572 #define THERM_STATUS_THRESHOLD0 (1 << 6)
573 #define THERM_LOG_THRESHOLD0 (1 << 7)
574 #define THERM_STATUS_THRESHOLD1 (1 << 8)
575 #define THERM_LOG_THRESHOLD1 (1 << 9)
577 /* MISC_ENABLE bits: architectural */
578 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
579 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
580 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
581 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
582 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
583 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
584 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
585 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
586 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
587 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
588 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
589 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
590 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
591 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
592 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
593 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
594 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
595 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
596 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
597 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
599 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
600 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
601 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
602 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
603 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
604 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
605 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
606 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
607 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
608 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
609 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
610 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
611 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
612 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
613 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
614 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
615 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
616 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
617 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
618 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
619 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
620 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
621 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
622 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
623 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
624 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
625 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
626 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
627 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
628 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
629 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
631 #define MSR_IA32_TSC_DEADLINE 0x000006E0
634 #define MSR_TSX_FORCE_ABORT 0x0000010F
636 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
637 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
639 /* P4/Xeon+ specific */
640 #define MSR_IA32_MCG_EAX 0x00000180
641 #define MSR_IA32_MCG_EBX 0x00000181
642 #define MSR_IA32_MCG_ECX 0x00000182
643 #define MSR_IA32_MCG_EDX 0x00000183
644 #define MSR_IA32_MCG_ESI 0x00000184
645 #define MSR_IA32_MCG_EDI 0x00000185
646 #define MSR_IA32_MCG_EBP 0x00000186
647 #define MSR_IA32_MCG_ESP 0x00000187
648 #define MSR_IA32_MCG_EFLAGS 0x00000188
649 #define MSR_IA32_MCG_EIP 0x00000189
650 #define MSR_IA32_MCG_RESERVED 0x0000018a
652 /* Pentium IV performance counter MSRs */
653 #define MSR_P4_BPU_PERFCTR0 0x00000300
654 #define MSR_P4_BPU_PERFCTR1 0x00000301
655 #define MSR_P4_BPU_PERFCTR2 0x00000302
656 #define MSR_P4_BPU_PERFCTR3 0x00000303
657 #define MSR_P4_MS_PERFCTR0 0x00000304
658 #define MSR_P4_MS_PERFCTR1 0x00000305
659 #define MSR_P4_MS_PERFCTR2 0x00000306
660 #define MSR_P4_MS_PERFCTR3 0x00000307
661 #define MSR_P4_FLAME_PERFCTR0 0x00000308
662 #define MSR_P4_FLAME_PERFCTR1 0x00000309
663 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
664 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
665 #define MSR_P4_IQ_PERFCTR0 0x0000030c
666 #define MSR_P4_IQ_PERFCTR1 0x0000030d
667 #define MSR_P4_IQ_PERFCTR2 0x0000030e
668 #define MSR_P4_IQ_PERFCTR3 0x0000030f
669 #define MSR_P4_IQ_PERFCTR4 0x00000310
670 #define MSR_P4_IQ_PERFCTR5 0x00000311
671 #define MSR_P4_BPU_CCCR0 0x00000360
672 #define MSR_P4_BPU_CCCR1 0x00000361
673 #define MSR_P4_BPU_CCCR2 0x00000362
674 #define MSR_P4_BPU_CCCR3 0x00000363
675 #define MSR_P4_MS_CCCR0 0x00000364
676 #define MSR_P4_MS_CCCR1 0x00000365
677 #define MSR_P4_MS_CCCR2 0x00000366
678 #define MSR_P4_MS_CCCR3 0x00000367
679 #define MSR_P4_FLAME_CCCR0 0x00000368
680 #define MSR_P4_FLAME_CCCR1 0x00000369
681 #define MSR_P4_FLAME_CCCR2 0x0000036a
682 #define MSR_P4_FLAME_CCCR3 0x0000036b
683 #define MSR_P4_IQ_CCCR0 0x0000036c
684 #define MSR_P4_IQ_CCCR1 0x0000036d
685 #define MSR_P4_IQ_CCCR2 0x0000036e
686 #define MSR_P4_IQ_CCCR3 0x0000036f
687 #define MSR_P4_IQ_CCCR4 0x00000370
688 #define MSR_P4_IQ_CCCR5 0x00000371
689 #define MSR_P4_ALF_ESCR0 0x000003ca
690 #define MSR_P4_ALF_ESCR1 0x000003cb
691 #define MSR_P4_BPU_ESCR0 0x000003b2
692 #define MSR_P4_BPU_ESCR1 0x000003b3
693 #define MSR_P4_BSU_ESCR0 0x000003a0
694 #define MSR_P4_BSU_ESCR1 0x000003a1
695 #define MSR_P4_CRU_ESCR0 0x000003b8
696 #define MSR_P4_CRU_ESCR1 0x000003b9
697 #define MSR_P4_CRU_ESCR2 0x000003cc
698 #define MSR_P4_CRU_ESCR3 0x000003cd
699 #define MSR_P4_CRU_ESCR4 0x000003e0
700 #define MSR_P4_CRU_ESCR5 0x000003e1
701 #define MSR_P4_DAC_ESCR0 0x000003a8
702 #define MSR_P4_DAC_ESCR1 0x000003a9
703 #define MSR_P4_FIRM_ESCR0 0x000003a4
704 #define MSR_P4_FIRM_ESCR1 0x000003a5
705 #define MSR_P4_FLAME_ESCR0 0x000003a6
706 #define MSR_P4_FLAME_ESCR1 0x000003a7
707 #define MSR_P4_FSB_ESCR0 0x000003a2
708 #define MSR_P4_FSB_ESCR1 0x000003a3
709 #define MSR_P4_IQ_ESCR0 0x000003ba
710 #define MSR_P4_IQ_ESCR1 0x000003bb
711 #define MSR_P4_IS_ESCR0 0x000003b4
712 #define MSR_P4_IS_ESCR1 0x000003b5
713 #define MSR_P4_ITLB_ESCR0 0x000003b6
714 #define MSR_P4_ITLB_ESCR1 0x000003b7
715 #define MSR_P4_IX_ESCR0 0x000003c8
716 #define MSR_P4_IX_ESCR1 0x000003c9
717 #define MSR_P4_MOB_ESCR0 0x000003aa
718 #define MSR_P4_MOB_ESCR1 0x000003ab
719 #define MSR_P4_MS_ESCR0 0x000003c0
720 #define MSR_P4_MS_ESCR1 0x000003c1
721 #define MSR_P4_PMH_ESCR0 0x000003ac
722 #define MSR_P4_PMH_ESCR1 0x000003ad
723 #define MSR_P4_RAT_ESCR0 0x000003bc
724 #define MSR_P4_RAT_ESCR1 0x000003bd
725 #define MSR_P4_SAAT_ESCR0 0x000003ae
726 #define MSR_P4_SAAT_ESCR1 0x000003af
727 #define MSR_P4_SSU_ESCR0 0x000003be
728 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
730 #define MSR_P4_TBPU_ESCR0 0x000003c2
731 #define MSR_P4_TBPU_ESCR1 0x000003c3
732 #define MSR_P4_TC_ESCR0 0x000003c4
733 #define MSR_P4_TC_ESCR1 0x000003c5
734 #define MSR_P4_U2L_ESCR0 0x000003b0
735 #define MSR_P4_U2L_ESCR1 0x000003b1
737 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
739 /* Intel Core-based CPU performance counters */
740 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
741 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
742 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
743 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
744 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
745 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
746 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
748 /* Geode defined MSRs */
749 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
752 #define MSR_IA32_VMX_BASIC 0x00000480
753 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
754 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
755 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
756 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
757 #define MSR_IA32_VMX_MISC 0x00000485
758 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
759 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
760 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
761 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
762 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
763 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
764 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
765 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
766 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
767 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
768 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
769 #define MSR_IA32_VMX_VMFUNC 0x00000491
771 /* VMX_BASIC bits and bitmasks */
772 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
773 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
774 #define VMX_BASIC_64 0x0001000000000000LLU
775 #define VMX_BASIC_MEM_TYPE_SHIFT 50
776 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
777 #define VMX_BASIC_MEM_TYPE_WB 6LLU
778 #define VMX_BASIC_INOUT 0x0040000000000000LLU
780 /* MSR_IA32_VMX_MISC bits */
781 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
782 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
785 #define MSR_VM_CR 0xc0010114
786 #define MSR_VM_IGNNE 0xc0010115
787 #define MSR_VM_HSAVE_PA 0xc0010117
789 #endif /* _ASM_X86_MSR_INDEX_H */