1 #ifndef _ASM_X86_MSR_INDEX_H
2 #define _ASM_X86_MSR_INDEX_H
4 #include <linux/bits.h>
7 * CPU model specific register (MSR) numbers.
9 * Do not add new entries to this file unless the definitions are shared
10 * between multiple compilation units.
13 /* x86-64 specific MSRs */
14 #define MSR_EFER 0xc0000080 /* extended feature register */
15 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
16 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
17 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
18 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
19 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
20 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
21 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
22 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
25 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
26 #define _EFER_LME 8 /* Long mode enable */
27 #define _EFER_LMA 10 /* Long mode active (read-only) */
28 #define _EFER_NX 11 /* No execute enable */
29 #define _EFER_SVME 12 /* Enable virtualization */
30 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
31 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
33 #define EFER_SCE (1<<_EFER_SCE)
34 #define EFER_LME (1<<_EFER_LME)
35 #define EFER_LMA (1<<_EFER_LMA)
36 #define EFER_NX (1<<_EFER_NX)
37 #define EFER_SVME (1<<_EFER_SVME)
38 #define EFER_LMSLE (1<<_EFER_LMSLE)
39 #define EFER_FFXSR (1<<_EFER_FFXSR)
41 /* Intel MSRs. Some also available on other CPUs */
42 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
43 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
44 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
45 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
46 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
47 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
49 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
50 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
52 #define MSR_IA32_PERFCTR0 0x000000c1
53 #define MSR_IA32_PERFCTR1 0x000000c2
54 #define MSR_FSB_FREQ 0x000000cd
55 #define MSR_PLATFORM_INFO 0x000000ce
57 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
58 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
59 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
60 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
61 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
62 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
64 #define MSR_MTRRcap 0x000000fe
66 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
67 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
68 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
69 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
70 #define ARCH_CAP_SSB_NO BIT(4) /*
71 * Not susceptible to Speculative Store Bypass
72 * attack, so no Speculative Store Bypass
75 #define ARCH_CAP_MDS_NO BIT(5) /*
77 * Microarchitectural Data
78 * Sampling (MDS) vulnerabilities.
80 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
81 * The processor is not susceptible to a
82 * machine check error due to modifying the
83 * code page size along with either the
84 * physical address or cache type
85 * without TLB invalidation.
87 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
88 #define ARCH_CAP_TAA_NO BIT(8) /*
90 * TSX Async Abort (TAA) vulnerabilities.
93 #define MSR_IA32_FLUSH_CMD 0x0000010b
94 #define L1D_FLUSH BIT(0) /*
95 * Writeback and invalidate the
99 #define MSR_IA32_BBL_CR_CTL 0x00000119
100 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
102 #define MSR_IA32_TSX_CTRL 0x00000122
103 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
104 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
107 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
108 #define RNGDS_MITG_DIS BIT(0)
110 #define MSR_IA32_SYSENTER_CS 0x00000174
111 #define MSR_IA32_SYSENTER_ESP 0x00000175
112 #define MSR_IA32_SYSENTER_EIP 0x00000176
114 #define MSR_IA32_MCG_CAP 0x00000179
115 #define MSR_IA32_MCG_STATUS 0x0000017a
116 #define MSR_IA32_MCG_CTL 0x0000017b
117 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
119 #define MSR_OFFCORE_RSP_0 0x000001a6
120 #define MSR_OFFCORE_RSP_1 0x000001a7
121 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
122 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
123 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
125 #define MSR_LBR_SELECT 0x000001c8
126 #define MSR_LBR_TOS 0x000001c9
127 #define MSR_LBR_NHM_FROM 0x00000680
128 #define MSR_LBR_NHM_TO 0x000006c0
129 #define MSR_LBR_CORE_FROM 0x00000040
130 #define MSR_LBR_CORE_TO 0x00000060
132 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
133 #define LBR_INFO_MISPRED BIT_ULL(63)
134 #define LBR_INFO_IN_TX BIT_ULL(62)
135 #define LBR_INFO_ABORT BIT_ULL(61)
136 #define LBR_INFO_CYCLES 0xffff
138 #define MSR_IA32_PEBS_ENABLE 0x000003f1
139 #define MSR_IA32_DS_AREA 0x00000600
140 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
141 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
143 #define MSR_IA32_RTIT_CTL 0x00000570
144 #define MSR_IA32_RTIT_STATUS 0x00000571
145 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
146 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
147 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
148 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
149 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
150 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
151 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
152 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
153 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
154 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
155 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
157 #define MSR_MTRRfix64K_00000 0x00000250
158 #define MSR_MTRRfix16K_80000 0x00000258
159 #define MSR_MTRRfix16K_A0000 0x00000259
160 #define MSR_MTRRfix4K_C0000 0x00000268
161 #define MSR_MTRRfix4K_C8000 0x00000269
162 #define MSR_MTRRfix4K_D0000 0x0000026a
163 #define MSR_MTRRfix4K_D8000 0x0000026b
164 #define MSR_MTRRfix4K_E0000 0x0000026c
165 #define MSR_MTRRfix4K_E8000 0x0000026d
166 #define MSR_MTRRfix4K_F0000 0x0000026e
167 #define MSR_MTRRfix4K_F8000 0x0000026f
168 #define MSR_MTRRdefType 0x000002ff
170 #define MSR_IA32_CR_PAT 0x00000277
172 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
173 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
174 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
175 #define MSR_IA32_LASTINTFROMIP 0x000001dd
176 #define MSR_IA32_LASTINTTOIP 0x000001de
178 /* DEBUGCTLMSR bits (others vary by model): */
179 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
180 #define DEBUGCTLMSR_BTF_SHIFT 1
181 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
182 #define DEBUGCTLMSR_TR (1UL << 6)
183 #define DEBUGCTLMSR_BTS (1UL << 7)
184 #define DEBUGCTLMSR_BTINT (1UL << 8)
185 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
186 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
187 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
189 #define MSR_PEBS_FRONTEND 0x000003f7
191 #define MSR_IA32_POWER_CTL 0x000001fc
193 #define MSR_IA32_MC0_CTL 0x00000400
194 #define MSR_IA32_MC0_STATUS 0x00000401
195 #define MSR_IA32_MC0_ADDR 0x00000402
196 #define MSR_IA32_MC0_MISC 0x00000403
198 /* C-state Residency Counters */
199 #define MSR_PKG_C3_RESIDENCY 0x000003f8
200 #define MSR_PKG_C6_RESIDENCY 0x000003f9
201 #define MSR_PKG_C7_RESIDENCY 0x000003fa
202 #define MSR_CORE_C3_RESIDENCY 0x000003fc
203 #define MSR_CORE_C6_RESIDENCY 0x000003fd
204 #define MSR_CORE_C7_RESIDENCY 0x000003fe
205 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
206 #define MSR_PKG_C2_RESIDENCY 0x0000060d
207 #define MSR_PKG_C8_RESIDENCY 0x00000630
208 #define MSR_PKG_C9_RESIDENCY 0x00000631
209 #define MSR_PKG_C10_RESIDENCY 0x00000632
211 /* Interrupt Response Limit */
212 #define MSR_PKGC3_IRTL 0x0000060a
213 #define MSR_PKGC6_IRTL 0x0000060b
214 #define MSR_PKGC7_IRTL 0x0000060c
215 #define MSR_PKGC8_IRTL 0x00000633
216 #define MSR_PKGC9_IRTL 0x00000634
217 #define MSR_PKGC10_IRTL 0x00000635
219 /* Run Time Average Power Limiting (RAPL) Interface */
221 #define MSR_RAPL_POWER_UNIT 0x00000606
223 #define MSR_PKG_POWER_LIMIT 0x00000610
224 #define MSR_PKG_ENERGY_STATUS 0x00000611
225 #define MSR_PKG_PERF_STATUS 0x00000613
226 #define MSR_PKG_POWER_INFO 0x00000614
228 #define MSR_DRAM_POWER_LIMIT 0x00000618
229 #define MSR_DRAM_ENERGY_STATUS 0x00000619
230 #define MSR_DRAM_PERF_STATUS 0x0000061b
231 #define MSR_DRAM_POWER_INFO 0x0000061c
233 #define MSR_PP0_POWER_LIMIT 0x00000638
234 #define MSR_PP0_ENERGY_STATUS 0x00000639
235 #define MSR_PP0_POLICY 0x0000063a
236 #define MSR_PP0_PERF_STATUS 0x0000063b
238 #define MSR_PP1_POWER_LIMIT 0x00000640
239 #define MSR_PP1_ENERGY_STATUS 0x00000641
240 #define MSR_PP1_POLICY 0x00000642
242 /* Config TDP MSRs */
243 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
244 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
245 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
246 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
247 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
249 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
251 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
252 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
253 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
254 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
256 #define MSR_CORE_C1_RES 0x00000660
258 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
259 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
261 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
262 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
263 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
265 /* Hardware P state interface */
266 #define MSR_PPERF 0x0000064e
267 #define MSR_PERF_LIMIT_REASONS 0x0000064f
268 #define MSR_PM_ENABLE 0x00000770
269 #define MSR_HWP_CAPABILITIES 0x00000771
270 #define MSR_HWP_REQUEST_PKG 0x00000772
271 #define MSR_HWP_INTERRUPT 0x00000773
272 #define MSR_HWP_REQUEST 0x00000774
273 #define MSR_HWP_STATUS 0x00000777
276 #define HWP_BASE_BIT (1<<7)
277 #define HWP_NOTIFICATIONS_BIT (1<<8)
278 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
279 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
280 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
282 /* IA32_HWP_CAPABILITIES */
283 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
284 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
285 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
286 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
288 /* IA32_HWP_REQUEST */
289 #define HWP_MIN_PERF(x) (x & 0xff)
290 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
291 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
292 #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24)
293 #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32)
294 #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)
296 /* IA32_HWP_STATUS */
297 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
298 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
300 /* IA32_HWP_INTERRUPT */
301 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
302 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
304 #define MSR_AMD64_MC0_MASK 0xc0010044
306 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
307 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
308 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
309 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
311 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
313 /* These are consecutive and not in the normal 4er MCE bank block */
314 #define MSR_IA32_MC0_CTL2 0x00000280
315 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
317 #define MSR_P6_PERFCTR0 0x000000c1
318 #define MSR_P6_PERFCTR1 0x000000c2
319 #define MSR_P6_EVNTSEL0 0x00000186
320 #define MSR_P6_EVNTSEL1 0x00000187
322 #define MSR_KNC_PERFCTR0 0x00000020
323 #define MSR_KNC_PERFCTR1 0x00000021
324 #define MSR_KNC_EVNTSEL0 0x00000028
325 #define MSR_KNC_EVNTSEL1 0x00000029
327 /* Alternative perfctr range with full access. */
328 #define MSR_IA32_PMC0 0x000004c1
330 /* AMD64 MSRs. Not complete. See the architecture manual for a more
333 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
334 #define MSR_AMD64_TSC_RATIO 0xc0000104
335 #define MSR_AMD64_NB_CFG 0xc001001f
336 #define MSR_AMD64_CPUID_FN_1 0xc0011004
337 #define MSR_AMD64_PATCH_LOADER 0xc0010020
338 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
339 #define MSR_AMD64_OSVW_STATUS 0xc0010141
340 #define MSR_AMD64_LS_CFG 0xc0011020
341 #define MSR_AMD64_DC_CFG 0xc0011022
342 #define MSR_AMD64_BU_CFG2 0xc001102a
343 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
344 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
345 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
346 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
347 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
348 #define MSR_AMD64_IBSOPCTL 0xc0011033
349 #define MSR_AMD64_IBSOPRIP 0xc0011034
350 #define MSR_AMD64_IBSOPDATA 0xc0011035
351 #define MSR_AMD64_IBSOPDATA2 0xc0011036
352 #define MSR_AMD64_IBSOPDATA3 0xc0011037
353 #define MSR_AMD64_IBSDCLINAD 0xc0011038
354 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
355 #define MSR_AMD64_IBSOP_REG_COUNT 7
356 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
357 #define MSR_AMD64_IBSCTL 0xc001103a
358 #define MSR_AMD64_IBSBRTARGET 0xc001103b
359 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
360 #define MSR_AMD64_IBSOPDATA4 0xc001103d
361 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
363 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
366 #define MSR_F17H_IRPERF 0xc00000e9
369 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
370 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
371 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
372 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
373 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
374 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
377 #define MSR_F15H_PERF_CTL 0xc0010200
378 #define MSR_F15H_PERF_CTR 0xc0010201
379 #define MSR_F15H_NB_PERF_CTL 0xc0010240
380 #define MSR_F15H_NB_PERF_CTR 0xc0010241
381 #define MSR_F15H_PTSC 0xc0010280
382 #define MSR_F15H_IC_CFG 0xc0011021
385 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
386 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
387 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
388 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
389 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
390 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
391 #define MSR_FAM10H_NODE_ID 0xc001100c
392 #define MSR_F10H_DECFG 0xc0011029
393 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
394 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
397 #define MSR_K8_TOP_MEM1 0xc001001a
398 #define MSR_K8_TOP_MEM2 0xc001001d
399 #define MSR_K8_SYSCFG 0xc0010010
400 #define MSR_K8_INT_PENDING_MSG 0xc0010055
401 /* C1E active bits in int pending message */
402 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
403 #define MSR_K8_TSEG_ADDR 0xc0010112
404 #define MSR_K8_TSEG_MASK 0xc0010113
405 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
406 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
407 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
410 #define MSR_K7_EVNTSEL0 0xc0010000
411 #define MSR_K7_PERFCTR0 0xc0010004
412 #define MSR_K7_EVNTSEL1 0xc0010001
413 #define MSR_K7_PERFCTR1 0xc0010005
414 #define MSR_K7_EVNTSEL2 0xc0010002
415 #define MSR_K7_PERFCTR2 0xc0010006
416 #define MSR_K7_EVNTSEL3 0xc0010003
417 #define MSR_K7_PERFCTR3 0xc0010007
418 #define MSR_K7_CLK_CTL 0xc001001b
419 #define MSR_K7_HWCR 0xc0010015
420 #define MSR_K7_FID_VID_CTL 0xc0010041
421 #define MSR_K7_FID_VID_STATUS 0xc0010042
424 #define MSR_K6_WHCR 0xc0000082
425 #define MSR_K6_UWCCR 0xc0000085
426 #define MSR_K6_EPMR 0xc0000086
427 #define MSR_K6_PSOR 0xc0000087
428 #define MSR_K6_PFIR 0xc0000088
430 /* Centaur-Hauls/IDT defined MSRs. */
431 #define MSR_IDT_FCR1 0x00000107
432 #define MSR_IDT_FCR2 0x00000108
433 #define MSR_IDT_FCR3 0x00000109
434 #define MSR_IDT_FCR4 0x0000010a
436 #define MSR_IDT_MCR0 0x00000110
437 #define MSR_IDT_MCR1 0x00000111
438 #define MSR_IDT_MCR2 0x00000112
439 #define MSR_IDT_MCR3 0x00000113
440 #define MSR_IDT_MCR4 0x00000114
441 #define MSR_IDT_MCR5 0x00000115
442 #define MSR_IDT_MCR6 0x00000116
443 #define MSR_IDT_MCR7 0x00000117
444 #define MSR_IDT_MCR_CTRL 0x00000120
446 /* VIA Cyrix defined MSRs*/
447 #define MSR_VIA_FCR 0x00001107
448 #define MSR_VIA_LONGHAUL 0x0000110a
449 #define MSR_VIA_RNG 0x0000110b
450 #define MSR_VIA_BCR2 0x00001147
452 /* Transmeta defined MSRs */
453 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
454 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
455 #define MSR_TMTA_LRTI_READOUT 0x80868018
456 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
458 /* Intel defined MSRs. */
459 #define MSR_IA32_P5_MC_ADDR 0x00000000
460 #define MSR_IA32_P5_MC_TYPE 0x00000001
461 #define MSR_IA32_TSC 0x00000010
462 #define MSR_IA32_PLATFORM_ID 0x00000017
463 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
464 #define MSR_EBC_FREQUENCY_ID 0x0000002c
465 #define MSR_SMI_COUNT 0x00000034
466 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
467 #define MSR_IA32_TSC_ADJUST 0x0000003b
468 #define MSR_IA32_BNDCFGS 0x00000d90
470 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
472 #define MSR_IA32_XSS 0x00000da0
474 #define FEATURE_CONTROL_LOCKED (1<<0)
475 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
476 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
477 #define FEATURE_CONTROL_LMCE (1<<20)
479 #define MSR_IA32_APICBASE 0x0000001b
480 #define MSR_IA32_APICBASE_BSP (1<<8)
481 #define MSR_IA32_APICBASE_ENABLE (1<<11)
482 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
484 #define MSR_IA32_TSCDEADLINE 0x000006e0
486 #define MSR_IA32_UCODE_WRITE 0x00000079
487 #define MSR_IA32_UCODE_REV 0x0000008b
489 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
490 #define MSR_IA32_SMBASE 0x0000009e
492 #define MSR_IA32_PERF_STATUS 0x00000198
493 #define MSR_IA32_PERF_CTL 0x00000199
494 #define INTEL_PERF_CTL_MASK 0xffff
495 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
496 #define MSR_AMD_PERF_STATUS 0xc0010063
497 #define MSR_AMD_PERF_CTL 0xc0010062
499 #define MSR_IA32_MPERF 0x000000e7
500 #define MSR_IA32_APERF 0x000000e8
502 #define MSR_IA32_THERM_CONTROL 0x0000019a
503 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
505 #define THERM_INT_HIGH_ENABLE (1 << 0)
506 #define THERM_INT_LOW_ENABLE (1 << 1)
507 #define THERM_INT_PLN_ENABLE (1 << 24)
509 #define MSR_IA32_THERM_STATUS 0x0000019c
511 #define THERM_STATUS_PROCHOT (1 << 0)
512 #define THERM_STATUS_POWER_LIMIT (1 << 10)
514 #define MSR_THERM2_CTL 0x0000019d
516 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
518 #define MSR_IA32_MISC_ENABLE 0x000001a0
520 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
522 #define MSR_MISC_PWR_MGMT 0x000001aa
524 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
525 #define ENERGY_PERF_BIAS_PERFORMANCE 0
526 #define ENERGY_PERF_BIAS_NORMAL 6
527 #define ENERGY_PERF_BIAS_POWERSAVE 15
529 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
531 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
532 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
534 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
536 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
537 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
538 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
540 /* Thermal Thresholds Support */
541 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
542 #define THERM_SHIFT_THRESHOLD0 8
543 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
544 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
545 #define THERM_SHIFT_THRESHOLD1 16
546 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
547 #define THERM_STATUS_THRESHOLD0 (1 << 6)
548 #define THERM_LOG_THRESHOLD0 (1 << 7)
549 #define THERM_STATUS_THRESHOLD1 (1 << 8)
550 #define THERM_LOG_THRESHOLD1 (1 << 9)
552 /* MISC_ENABLE bits: architectural */
553 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
554 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
555 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
556 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
557 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
558 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
559 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
560 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
561 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
562 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
563 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
564 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
565 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
566 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
567 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
568 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
569 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
570 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
571 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
572 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
574 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
575 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
576 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
577 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
578 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
579 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
580 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
581 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
582 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
583 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
584 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
585 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
586 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
587 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
588 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
589 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
590 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
591 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
592 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
593 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
594 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
595 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
596 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
597 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
598 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
599 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
600 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
601 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
602 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
603 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
604 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
606 #define MSR_IA32_TSC_DEADLINE 0x000006E0
609 #define MSR_TSX_FORCE_ABORT 0x0000010F
611 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
612 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
614 /* P4/Xeon+ specific */
615 #define MSR_IA32_MCG_EAX 0x00000180
616 #define MSR_IA32_MCG_EBX 0x00000181
617 #define MSR_IA32_MCG_ECX 0x00000182
618 #define MSR_IA32_MCG_EDX 0x00000183
619 #define MSR_IA32_MCG_ESI 0x00000184
620 #define MSR_IA32_MCG_EDI 0x00000185
621 #define MSR_IA32_MCG_EBP 0x00000186
622 #define MSR_IA32_MCG_ESP 0x00000187
623 #define MSR_IA32_MCG_EFLAGS 0x00000188
624 #define MSR_IA32_MCG_EIP 0x00000189
625 #define MSR_IA32_MCG_RESERVED 0x0000018a
627 /* Pentium IV performance counter MSRs */
628 #define MSR_P4_BPU_PERFCTR0 0x00000300
629 #define MSR_P4_BPU_PERFCTR1 0x00000301
630 #define MSR_P4_BPU_PERFCTR2 0x00000302
631 #define MSR_P4_BPU_PERFCTR3 0x00000303
632 #define MSR_P4_MS_PERFCTR0 0x00000304
633 #define MSR_P4_MS_PERFCTR1 0x00000305
634 #define MSR_P4_MS_PERFCTR2 0x00000306
635 #define MSR_P4_MS_PERFCTR3 0x00000307
636 #define MSR_P4_FLAME_PERFCTR0 0x00000308
637 #define MSR_P4_FLAME_PERFCTR1 0x00000309
638 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
639 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
640 #define MSR_P4_IQ_PERFCTR0 0x0000030c
641 #define MSR_P4_IQ_PERFCTR1 0x0000030d
642 #define MSR_P4_IQ_PERFCTR2 0x0000030e
643 #define MSR_P4_IQ_PERFCTR3 0x0000030f
644 #define MSR_P4_IQ_PERFCTR4 0x00000310
645 #define MSR_P4_IQ_PERFCTR5 0x00000311
646 #define MSR_P4_BPU_CCCR0 0x00000360
647 #define MSR_P4_BPU_CCCR1 0x00000361
648 #define MSR_P4_BPU_CCCR2 0x00000362
649 #define MSR_P4_BPU_CCCR3 0x00000363
650 #define MSR_P4_MS_CCCR0 0x00000364
651 #define MSR_P4_MS_CCCR1 0x00000365
652 #define MSR_P4_MS_CCCR2 0x00000366
653 #define MSR_P4_MS_CCCR3 0x00000367
654 #define MSR_P4_FLAME_CCCR0 0x00000368
655 #define MSR_P4_FLAME_CCCR1 0x00000369
656 #define MSR_P4_FLAME_CCCR2 0x0000036a
657 #define MSR_P4_FLAME_CCCR3 0x0000036b
658 #define MSR_P4_IQ_CCCR0 0x0000036c
659 #define MSR_P4_IQ_CCCR1 0x0000036d
660 #define MSR_P4_IQ_CCCR2 0x0000036e
661 #define MSR_P4_IQ_CCCR3 0x0000036f
662 #define MSR_P4_IQ_CCCR4 0x00000370
663 #define MSR_P4_IQ_CCCR5 0x00000371
664 #define MSR_P4_ALF_ESCR0 0x000003ca
665 #define MSR_P4_ALF_ESCR1 0x000003cb
666 #define MSR_P4_BPU_ESCR0 0x000003b2
667 #define MSR_P4_BPU_ESCR1 0x000003b3
668 #define MSR_P4_BSU_ESCR0 0x000003a0
669 #define MSR_P4_BSU_ESCR1 0x000003a1
670 #define MSR_P4_CRU_ESCR0 0x000003b8
671 #define MSR_P4_CRU_ESCR1 0x000003b9
672 #define MSR_P4_CRU_ESCR2 0x000003cc
673 #define MSR_P4_CRU_ESCR3 0x000003cd
674 #define MSR_P4_CRU_ESCR4 0x000003e0
675 #define MSR_P4_CRU_ESCR5 0x000003e1
676 #define MSR_P4_DAC_ESCR0 0x000003a8
677 #define MSR_P4_DAC_ESCR1 0x000003a9
678 #define MSR_P4_FIRM_ESCR0 0x000003a4
679 #define MSR_P4_FIRM_ESCR1 0x000003a5
680 #define MSR_P4_FLAME_ESCR0 0x000003a6
681 #define MSR_P4_FLAME_ESCR1 0x000003a7
682 #define MSR_P4_FSB_ESCR0 0x000003a2
683 #define MSR_P4_FSB_ESCR1 0x000003a3
684 #define MSR_P4_IQ_ESCR0 0x000003ba
685 #define MSR_P4_IQ_ESCR1 0x000003bb
686 #define MSR_P4_IS_ESCR0 0x000003b4
687 #define MSR_P4_IS_ESCR1 0x000003b5
688 #define MSR_P4_ITLB_ESCR0 0x000003b6
689 #define MSR_P4_ITLB_ESCR1 0x000003b7
690 #define MSR_P4_IX_ESCR0 0x000003c8
691 #define MSR_P4_IX_ESCR1 0x000003c9
692 #define MSR_P4_MOB_ESCR0 0x000003aa
693 #define MSR_P4_MOB_ESCR1 0x000003ab
694 #define MSR_P4_MS_ESCR0 0x000003c0
695 #define MSR_P4_MS_ESCR1 0x000003c1
696 #define MSR_P4_PMH_ESCR0 0x000003ac
697 #define MSR_P4_PMH_ESCR1 0x000003ad
698 #define MSR_P4_RAT_ESCR0 0x000003bc
699 #define MSR_P4_RAT_ESCR1 0x000003bd
700 #define MSR_P4_SAAT_ESCR0 0x000003ae
701 #define MSR_P4_SAAT_ESCR1 0x000003af
702 #define MSR_P4_SSU_ESCR0 0x000003be
703 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
705 #define MSR_P4_TBPU_ESCR0 0x000003c2
706 #define MSR_P4_TBPU_ESCR1 0x000003c3
707 #define MSR_P4_TC_ESCR0 0x000003c4
708 #define MSR_P4_TC_ESCR1 0x000003c5
709 #define MSR_P4_U2L_ESCR0 0x000003b0
710 #define MSR_P4_U2L_ESCR1 0x000003b1
712 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
714 /* Intel Core-based CPU performance counters */
715 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
716 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
717 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
718 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
719 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
720 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
721 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
723 /* Geode defined MSRs */
724 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
727 #define MSR_IA32_VMX_BASIC 0x00000480
728 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
729 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
730 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
731 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
732 #define MSR_IA32_VMX_MISC 0x00000485
733 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
734 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
735 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
736 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
737 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
738 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
739 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
740 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
741 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
742 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
743 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
744 #define MSR_IA32_VMX_VMFUNC 0x00000491
746 /* VMX_BASIC bits and bitmasks */
747 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
748 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
749 #define VMX_BASIC_64 0x0001000000000000LLU
750 #define VMX_BASIC_MEM_TYPE_SHIFT 50
751 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
752 #define VMX_BASIC_MEM_TYPE_WB 6LLU
753 #define VMX_BASIC_INOUT 0x0040000000000000LLU
755 /* MSR_IA32_VMX_MISC bits */
756 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
757 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
760 #define MSR_VM_CR 0xc0010114
761 #define MSR_VM_IGNNE 0xc0010115
762 #define MSR_VM_HSAVE_PA 0xc0010117
764 #endif /* _ASM_X86_MSR_INDEX_H */