1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_INTEL_FAMILY_H
3 #define _ASM_X86_INTEL_FAMILY_H
6 * "Big Core" Processors (Branded as Core, Xeon, etc...)
8 * The "_X" parts are generally the EP and EX Xeons, or the
9 * "Extreme" ones, like Broadwell-E, or Atom microserver.
11 * Things ending in "2" are usually because we have no better
12 * name for them. There's no processor called "SILVERMONT2".
14 * While adding a new CPUID for a new microarchitecture, add a new
15 * group to keep logically sorted out in chronological order. Within
16 * that group keep the CPUID for the variants sorted by model number.
19 /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
20 #define INTEL_FAM6_ANY X86_MODEL_ANY
22 #define INTEL_FAM6_CORE_YONAH 0x0E
24 #define INTEL_FAM6_CORE2_MEROM 0x0F
25 #define INTEL_FAM6_CORE2_MEROM_L 0x16
26 #define INTEL_FAM6_CORE2_PENRYN 0x17
27 #define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
29 #define INTEL_FAM6_NEHALEM 0x1E
30 #define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
31 #define INTEL_FAM6_NEHALEM_EP 0x1A
32 #define INTEL_FAM6_NEHALEM_EX 0x2E
34 #define INTEL_FAM6_WESTMERE 0x25
35 #define INTEL_FAM6_WESTMERE_EP 0x2C
36 #define INTEL_FAM6_WESTMERE_EX 0x2F
38 #define INTEL_FAM6_SANDYBRIDGE 0x2A
39 #define INTEL_FAM6_SANDYBRIDGE_X 0x2D
40 #define INTEL_FAM6_IVYBRIDGE 0x3A
41 #define INTEL_FAM6_IVYBRIDGE_X 0x3E
43 #define INTEL_FAM6_HASWELL_CORE 0x3C
44 #define INTEL_FAM6_HASWELL_X 0x3F
45 #define INTEL_FAM6_HASWELL_ULT 0x45
46 #define INTEL_FAM6_HASWELL_GT3E 0x46
48 #define INTEL_FAM6_BROADWELL_CORE 0x3D
49 #define INTEL_FAM6_BROADWELL_GT3E 0x47
50 #define INTEL_FAM6_BROADWELL_X 0x4F
51 #define INTEL_FAM6_BROADWELL_XEON_D 0x56
53 #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
54 #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
55 #define INTEL_FAM6_SKYLAKE_X 0x55
56 #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
57 #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
59 #define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
61 #define INTEL_FAM6_ICELAKE_X 0x6A
62 #define INTEL_FAM6_ICELAKE_XEON_D 0x6C
63 #define INTEL_FAM6_ICELAKE_DESKTOP 0x7D
64 #define INTEL_FAM6_ICELAKE_MOBILE 0x7E
66 #define INTEL_FAM6_COMETLAKE 0xA5
67 #define INTEL_FAM6_COMETLAKE_L 0xA6
69 #define INTEL_FAM6_ROCKETLAKE 0xA7
71 /* Hybrid Core/Atom Processors */
73 #define INTEL_FAM6_LAKEFIELD 0x8A
74 #define INTEL_FAM6_ALDERLAKE 0x97
75 #define INTEL_FAM6_ALDERLAKE_L 0x9A
76 #define INTEL_FAM6_ALDERLAKE_N 0xBE
78 #define INTEL_FAM6_RAPTORLAKE 0xB7
79 #define INTEL_FAM6_RAPTORLAKE_P 0xBA
80 #define INTEL_FAM6_RAPTORLAKE_S 0xBF
82 #define INTEL_FAM6_TIGERLAKE_L 0x8C
83 #define INTEL_FAM6_TIGERLAKE 0x8D
85 /* "Small Core" Processors (Atom) */
87 #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
88 #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
90 #define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
91 #define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
92 #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
94 #define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
95 #define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
96 #define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
98 #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
99 #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
101 #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
102 #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
103 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
105 #define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */
106 #define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
107 #define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
111 #define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
112 #define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
115 #define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */
117 #endif /* _ASM_X86_INTEL_FAMILY_H */