arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14 /*
  15  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  16  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  17  */
  18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  19 #define HYPERV_CPUID_INTERFACE                  0x40000001
  20 #define HYPERV_CPUID_VERSION                    0x40000002
  21 #define HYPERV_CPUID_FEATURES                   0x40000003
  22 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  23 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES    0x40000007
  25 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  26 #define HYPERV_CPUID_ISOLATION_CONFIG           0x4000000C
  27
  28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE       0x40000081
  29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE       0x31235356  /* "VS#1" */
  30
  31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES      0x40000082
  32 /* Support for the extended IOAPIC RTE format */
  33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE    BIT(2)
  34
  35 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  36 #define HYPERV_CPUID_MIN                        0x40000005
  37 #define HYPERV_CPUID_MAX                        0x4000ffff
  38
  39 /*
  40  * Group D Features.  The bit assignments are custom to each architecture.
  41  * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits.
  42  */
  43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
  44 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
  45 /* Guest debugging support is available */
  46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
  47 /* Performance Monitor support is available*/
  48 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
  49 /* Support for physical CPU dynamic partitioning events is available*/
  50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
  51 /*
  52  * Support for passing hypercall input parameter block via XMM
  53  * registers is available
  54  */
  55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE            BIT(4)
  56 /* Support for a virtual guest idle state is available */
  57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
  58 /* Frequency MSRs available */
  59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
  60 /* Crash MSR available */
  61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
  62 /* Support for debug MSRs available */
  63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE                 BIT(11)
  64 /*
  65  * Support for returning hypercall output block via XMM
  66  * registers is available
  67  */
  68 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE           BIT(15)
  69 /* stimer Direct Mode is available */
  70 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
  71
  72 /*
  73  * Implementation recommendations. Indicates which behaviors the hypervisor
  74  * recommends the OS implement for optimal performance.
  75  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
  76  */
  77 /*
  78  * Recommend using hypercall for address space switches rather
  79  * than MOV to CR3 instruction
  80  */
  81 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
  82 /* Recommend using hypercall for local TLB flushes rather
  83  * than INVLPG or MOV to CR3 instructions */
  84 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
  85 /*
  86  * Recommend using hypercall for remote TLB flushes rather
  87  * than inter-processor interrupts
  88  */
  89 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
  90 /*
  91  * Recommend using MSRs for accessing APIC registers
  92  * EOI, ICR and TPR rather than their memory-mapped counterparts
  93  */
  94 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
  95 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
  96 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
  97 /*
  98  * Recommend using relaxed timing for this partition. If used,
  99  * the VM should disable any watchdog timeouts that rely on the
 100  * timely delivery of external interrupts
 101  */
 102 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 103
 104 /*
 105  * Recommend not using Auto End-Of-Interrupt feature
 106  */
 107 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 108
 109 /*
 110  * Recommend using cluster IPI hypercalls.
 111  */
 112 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 113
 114 /* Recommend using the newer ExProcessorMasks interface */
 115 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 116
 117 /* Recommend using enlightened VMCS */
 118 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 119
 120 /*
 121  * CPU management features identification.
 122  * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits.
 123  */
 124 #define HV_X64_START_LOGICAL_PROCESSOR                  BIT(0)
 125 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR            BIT(1)
 126 #define HV_X64_PERFORMANCE_COUNTER_SYNC                 BIT(2)
 127 #define HV_X64_RESERVED_IDENTITY_BIT                    BIT(31)
 128
 129 /*
 130  * Virtual processor will never share a physical core with another virtual
 131  * processor, except for virtual processors that are reported as sibling SMT
 132  * threads.
 133  */
 134 #define HV_X64_NO_NONARCH_CORESHARING                   BIT(18)
 135
 136 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 137 #define HV_X64_NESTED_DIRECT_FLUSH                      BIT(17)
 138 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 139 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 140
 141 /*
 142  * This is specific to AMD and specifies that enlightened TLB flush is
 143  * supported. If guest opts in to this feature, ASID invalidations only
 144  * flushes gva -> hpa mapping entries. To flush the TLB entries derived
 145  * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
 146  * or HvFlushGuestPhysicalAddressList).
 147  */
 148 #define HV_X64_NESTED_ENLIGHTENED_TLB                   BIT(22)
 149
 150 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
 151 #define HV_PARAVISOR_PRESENT                            BIT(0)
 152
 153 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */
 154 #define HV_ISOLATION_TYPE                               GENMASK(3, 0)
 155 #define HV_SHARED_GPA_BOUNDARY_ACTIVE                   BIT(5)
 156 #define HV_SHARED_GPA_BOUNDARY_BITS                     GENMASK(11, 6)
 157
 158 enum hv_isolation_type {
 159         HV_ISOLATION_TYPE_NONE  = 0,
 160         HV_ISOLATION_TYPE_VBS   = 1,
 161         HV_ISOLATION_TYPE_SNP   = 2
 162 };
 163
 164 /* Hyper-V specific model specific registers (MSRs) */
 165
 166 /* MSR used to identify the guest OS. */
 167 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 168
 169 /* MSR used to setup pages used to communicate with the hypervisor. */
 170 #define HV_X64_MSR_HYPERCALL                    0x40000001
 171
 172 /* MSR used to provide vcpu index */
 173 #define HV_REGISTER_VP_INDEX                    0x40000002
 174
 175 /* MSR used to reset the guest OS. */
 176 #define HV_X64_MSR_RESET                        0x40000003
 177
 178 /* MSR used to provide vcpu runtime in 100ns units */
 179 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 180
 181 /* MSR used to read the per-partition time reference counter */
 182 #define HV_REGISTER_TIME_REF_COUNT              0x40000020
 183
 184 /* A partition's reference time stamp counter (TSC) page */
 185 #define HV_REGISTER_REFERENCE_TSC               0x40000021
 186
 187 /* MSR used to retrieve the TSC frequency */
 188 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 189
 190 /* MSR used to retrieve the local APIC timer frequency */
 191 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 192
 193 /* Define the virtual APIC registers */
 194 #define HV_X64_MSR_EOI                          0x40000070
 195 #define HV_X64_MSR_ICR                          0x40000071
 196 #define HV_X64_MSR_TPR                          0x40000072
 197 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 198
 199 /* Define synthetic interrupt controller model specific registers. */
 200 #define HV_REGISTER_SCONTROL                    0x40000080
 201 #define HV_REGISTER_SVERSION                    0x40000081
 202 #define HV_REGISTER_SIEFP                       0x40000082
 203 #define HV_REGISTER_SIMP                        0x40000083
 204 #define HV_REGISTER_EOM                         0x40000084
 205 #define HV_REGISTER_SINT0                       0x40000090
 206 #define HV_REGISTER_SINT1                       0x40000091
 207 #define HV_REGISTER_SINT2                       0x40000092
 208 #define HV_REGISTER_SINT3                       0x40000093
 209 #define HV_REGISTER_SINT4                       0x40000094
 210 #define HV_REGISTER_SINT5                       0x40000095
 211 #define HV_REGISTER_SINT6                       0x40000096
 212 #define HV_REGISTER_SINT7                       0x40000097
 213 #define HV_REGISTER_SINT8                       0x40000098
 214 #define HV_REGISTER_SINT9                       0x40000099
 215 #define HV_REGISTER_SINT10                      0x4000009A
 216 #define HV_REGISTER_SINT11                      0x4000009B
 217 #define HV_REGISTER_SINT12                      0x4000009C
 218 #define HV_REGISTER_SINT13                      0x4000009D
 219 #define HV_REGISTER_SINT14                      0x4000009E
 220 #define HV_REGISTER_SINT15                      0x4000009F
 221
 222 /*
 223  * Synthetic Timer MSRs. Four timers per vcpu.
 224  */
 225 #define HV_REGISTER_STIMER0_CONFIG              0x400000B0
 226 #define HV_REGISTER_STIMER0_COUNT               0x400000B1
 227 #define HV_REGISTER_STIMER1_CONFIG              0x400000B2
 228 #define HV_REGISTER_STIMER1_COUNT               0x400000B3
 229 #define HV_REGISTER_STIMER2_CONFIG              0x400000B4
 230 #define HV_REGISTER_STIMER2_COUNT               0x400000B5
 231 #define HV_REGISTER_STIMER3_CONFIG              0x400000B6
 232 #define HV_REGISTER_STIMER3_COUNT               0x400000B7
 233
 234 /* Hyper-V guest idle MSR */
 235 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 236
 237 /* Hyper-V guest crash notification MSR's */
 238 #define HV_REGISTER_CRASH_P0                    0x40000100
 239 #define HV_REGISTER_CRASH_P1                    0x40000101
 240 #define HV_REGISTER_CRASH_P2                    0x40000102
 241 #define HV_REGISTER_CRASH_P3                    0x40000103
 242 #define HV_REGISTER_CRASH_P4                    0x40000104
 243 #define HV_REGISTER_CRASH_CTL                   0x40000105
 244
 245 /* TSC emulation after migration */
 246 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 247 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 248 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 249
 250 /* TSC invariant control */
 251 #define HV_X64_MSR_TSC_INVARIANT_CONTROL        0x40000118
 252
 253 /* Register name aliases for temporary compatibility */
 254 #define HV_X64_MSR_STIMER0_COUNT        HV_REGISTER_STIMER0_COUNT
 255 #define HV_X64_MSR_STIMER0_CONFIG       HV_REGISTER_STIMER0_CONFIG
 256 #define HV_X64_MSR_STIMER1_COUNT        HV_REGISTER_STIMER1_COUNT
 257 #define HV_X64_MSR_STIMER1_CONFIG       HV_REGISTER_STIMER1_CONFIG
 258 #define HV_X64_MSR_STIMER2_COUNT        HV_REGISTER_STIMER2_COUNT
 259 #define HV_X64_MSR_STIMER2_CONFIG       HV_REGISTER_STIMER2_CONFIG
 260 #define HV_X64_MSR_STIMER3_COUNT        HV_REGISTER_STIMER3_COUNT
 261 #define HV_X64_MSR_STIMER3_CONFIG       HV_REGISTER_STIMER3_CONFIG
 262 #define HV_X64_MSR_SCONTROL             HV_REGISTER_SCONTROL
 263 #define HV_X64_MSR_SVERSION             HV_REGISTER_SVERSION
 264 #define HV_X64_MSR_SIMP                 HV_REGISTER_SIMP
 265 #define HV_X64_MSR_SIEFP                HV_REGISTER_SIEFP
 266 #define HV_X64_MSR_VP_INDEX             HV_REGISTER_VP_INDEX
 267 #define HV_X64_MSR_EOM                  HV_REGISTER_EOM
 268 #define HV_X64_MSR_SINT0                HV_REGISTER_SINT0
 269 #define HV_X64_MSR_SINT15               HV_REGISTER_SINT15
 270 #define HV_X64_MSR_CRASH_P0             HV_REGISTER_CRASH_P0
 271 #define HV_X64_MSR_CRASH_P1             HV_REGISTER_CRASH_P1
 272 #define HV_X64_MSR_CRASH_P2             HV_REGISTER_CRASH_P2
 273 #define HV_X64_MSR_CRASH_P3             HV_REGISTER_CRASH_P3
 274 #define HV_X64_MSR_CRASH_P4             HV_REGISTER_CRASH_P4
 275 #define HV_X64_MSR_CRASH_CTL            HV_REGISTER_CRASH_CTL
 276 #define HV_X64_MSR_TIME_REF_COUNT       HV_REGISTER_TIME_REF_COUNT
 277 #define HV_X64_MSR_REFERENCE_TSC        HV_REGISTER_REFERENCE_TSC
 278
 279 /*
 280  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 281  */
 282 union hv_x64_msr_hypercall_contents {
 283         u64 as_uint64;
 284         struct {
 285                 u64 enable:1;
 286                 u64 reserved:11;
 287                 u64 guest_physical_address:52;
 288         } __packed;
 289 };
 290
 291 union hv_vp_assist_msr_contents {
 292         u64 as_uint64;
 293         struct {
 294                 u64 enable:1;
 295                 u64 reserved:11;
 296                 u64 pfn:52;
 297         } __packed;
 298 };
 299
 300 struct hv_reenlightenment_control {
 301         __u64 vector:8;
 302         __u64 reserved1:8;
 303         __u64 enabled:1;
 304         __u64 reserved2:15;
 305         __u64 target_vp:32;
 306 }  __packed;
 307
 308 struct hv_tsc_emulation_control {
 309         __u64 enabled:1;
 310         __u64 reserved:63;
 311 } __packed;
 312
 313 struct hv_tsc_emulation_status {
 314         __u64 inprogress:1;
 315         __u64 reserved:63;
 316 } __packed;
 317
 318 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 319 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 320 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 321                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 322
 323 #define HV_X64_MSR_CRASH_PARAMS         \
 324                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 325
 326 #define HV_IPI_LOW_VECTOR       0x10
 327 #define HV_IPI_HIGH_VECTOR      0xff
 328
 329 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 330 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 331 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 332                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 333
 334 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 335 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 336
 337 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 338 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 339
 340 /* Number of XMM registers used in hypercall input/output */
 341 #define HV_HYPERCALL_MAX_XMM_REGISTERS          6
 342
 343 struct hv_nested_enlightenments_control {
 344         struct {
 345                 __u32 directhypercall:1;
 346                 __u32 reserved:31;
 347         } features;
 348         struct {
 349                 __u32 reserved;
 350         } hypercallControls;
 351 } __packed;
 352
 353 /* Define virtual processor assist page structure. */
 354 struct hv_vp_assist_page {
 355         __u32 apic_assist;
 356         __u32 reserved1;
 357         __u64 vtl_control[3];
 358         struct hv_nested_enlightenments_control nested_control;
 359         __u8 enlighten_vmentry;
 360         __u8 reserved2[7];
 361         __u64 current_nested_vmcs;
 362 } __packed;
 363
 364 struct hv_enlightened_vmcs {
 365         u32 revision_id;
 366         u32 abort;
 367
 368         u16 host_es_selector;
 369         u16 host_cs_selector;
 370         u16 host_ss_selector;
 371         u16 host_ds_selector;
 372         u16 host_fs_selector;
 373         u16 host_gs_selector;
 374         u16 host_tr_selector;
 375
 376         u16 padding16_1;
 377
 378         u64 host_ia32_pat;
 379         u64 host_ia32_efer;
 380
 381         u64 host_cr0;
 382         u64 host_cr3;
 383         u64 host_cr4;
 384
 385         u64 host_ia32_sysenter_esp;
 386         u64 host_ia32_sysenter_eip;
 387         u64 host_rip;
 388         u32 host_ia32_sysenter_cs;
 389
 390         u32 pin_based_vm_exec_control;
 391         u32 vm_exit_controls;
 392         u32 secondary_vm_exec_control;
 393
 394         u64 io_bitmap_a;
 395         u64 io_bitmap_b;
 396         u64 msr_bitmap;
 397
 398         u16 guest_es_selector;
 399         u16 guest_cs_selector;
 400         u16 guest_ss_selector;
 401         u16 guest_ds_selector;
 402         u16 guest_fs_selector;
 403         u16 guest_gs_selector;
 404         u16 guest_ldtr_selector;
 405         u16 guest_tr_selector;
 406
 407         u32 guest_es_limit;
 408         u32 guest_cs_limit;
 409         u32 guest_ss_limit;
 410         u32 guest_ds_limit;
 411         u32 guest_fs_limit;
 412         u32 guest_gs_limit;
 413         u32 guest_ldtr_limit;
 414         u32 guest_tr_limit;
 415         u32 guest_gdtr_limit;
 416         u32 guest_idtr_limit;
 417
 418         u32 guest_es_ar_bytes;
 419         u32 guest_cs_ar_bytes;
 420         u32 guest_ss_ar_bytes;
 421         u32 guest_ds_ar_bytes;
 422         u32 guest_fs_ar_bytes;
 423         u32 guest_gs_ar_bytes;
 424         u32 guest_ldtr_ar_bytes;
 425         u32 guest_tr_ar_bytes;
 426
 427         u64 guest_es_base;
 428         u64 guest_cs_base;
 429         u64 guest_ss_base;
 430         u64 guest_ds_base;
 431         u64 guest_fs_base;
 432         u64 guest_gs_base;
 433         u64 guest_ldtr_base;
 434         u64 guest_tr_base;
 435         u64 guest_gdtr_base;
 436         u64 guest_idtr_base;
 437
 438         u64 padding64_1[3];
 439
 440         u64 vm_exit_msr_store_addr;
 441         u64 vm_exit_msr_load_addr;
 442         u64 vm_entry_msr_load_addr;
 443
 444         u64 cr3_target_value0;
 445         u64 cr3_target_value1;
 446         u64 cr3_target_value2;
 447         u64 cr3_target_value3;
 448
 449         u32 page_fault_error_code_mask;
 450         u32 page_fault_error_code_match;
 451
 452         u32 cr3_target_count;
 453         u32 vm_exit_msr_store_count;
 454         u32 vm_exit_msr_load_count;
 455         u32 vm_entry_msr_load_count;
 456
 457         u64 tsc_offset;
 458         u64 virtual_apic_page_addr;
 459         u64 vmcs_link_pointer;
 460
 461         u64 guest_ia32_debugctl;
 462         u64 guest_ia32_pat;
 463         u64 guest_ia32_efer;
 464
 465         u64 guest_pdptr0;
 466         u64 guest_pdptr1;
 467         u64 guest_pdptr2;
 468         u64 guest_pdptr3;
 469
 470         u64 guest_pending_dbg_exceptions;
 471         u64 guest_sysenter_esp;
 472         u64 guest_sysenter_eip;
 473
 474         u32 guest_activity_state;
 475         u32 guest_sysenter_cs;
 476
 477         u64 cr0_guest_host_mask;
 478         u64 cr4_guest_host_mask;
 479         u64 cr0_read_shadow;
 480         u64 cr4_read_shadow;
 481         u64 guest_cr0;
 482         u64 guest_cr3;
 483         u64 guest_cr4;
 484         u64 guest_dr7;
 485
 486         u64 host_fs_base;
 487         u64 host_gs_base;
 488         u64 host_tr_base;
 489         u64 host_gdtr_base;
 490         u64 host_idtr_base;
 491         u64 host_rsp;
 492
 493         u64 ept_pointer;
 494
 495         u16 virtual_processor_id;
 496         u16 padding16_2[3];
 497
 498         u64 padding64_2[5];
 499         u64 guest_physical_address;
 500
 501         u32 vm_instruction_error;
 502         u32 vm_exit_reason;
 503         u32 vm_exit_intr_info;
 504         u32 vm_exit_intr_error_code;
 505         u32 idt_vectoring_info_field;
 506         u32 idt_vectoring_error_code;
 507         u32 vm_exit_instruction_len;
 508         u32 vmx_instruction_info;
 509
 510         u64 exit_qualification;
 511         u64 exit_io_instruction_ecx;
 512         u64 exit_io_instruction_esi;
 513         u64 exit_io_instruction_edi;
 514         u64 exit_io_instruction_eip;
 515
 516         u64 guest_linear_address;
 517         u64 guest_rsp;
 518         u64 guest_rflags;
 519
 520         u32 guest_interruptibility_info;
 521         u32 cpu_based_vm_exec_control;
 522         u32 exception_bitmap;
 523         u32 vm_entry_controls;
 524         u32 vm_entry_intr_info_field;
 525         u32 vm_entry_exception_error_code;
 526         u32 vm_entry_instruction_len;
 527         u32 tpr_threshold;
 528
 529         u64 guest_rip;
 530
 531         u32 hv_clean_fields;
 532         u32 padding32_1;
 533         u32 hv_synthetic_controls;
 534         struct {
 535                 u32 nested_flush_hypercall:1;
 536                 u32 msr_bitmap:1;
 537                 u32 reserved:30;
 538         }  __packed hv_enlightenments_control;
 539         u32 hv_vp_id;
 540         u32 padding32_2;
 541         u64 hv_vm_id;
 542         u64 partition_assist_page;
 543         u64 padding64_4[4];
 544         u64 guest_bndcfgs;
 545         u64 padding64_5[7];
 546         u64 xss_exit_bitmap;
 547         u64 padding64_6[7];
 548 } __packed;
 549
 550 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 551 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 552 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 553 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 554 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 555 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 556 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 557 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 558 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 559 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 560 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 561 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 562 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 563 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 564 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 565 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 566 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 567
 568 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 569
 570 struct hv_partition_assist_pg {
 571         u32 tlb_lock_count;
 572 };
 573
 574 enum hv_interrupt_type {
 575         HV_X64_INTERRUPT_TYPE_FIXED             = 0x0000,
 576         HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY    = 0x0001,
 577         HV_X64_INTERRUPT_TYPE_SMI               = 0x0002,
 578         HV_X64_INTERRUPT_TYPE_REMOTEREAD        = 0x0003,
 579         HV_X64_INTERRUPT_TYPE_NMI               = 0x0004,
 580         HV_X64_INTERRUPT_TYPE_INIT              = 0x0005,
 581         HV_X64_INTERRUPT_TYPE_SIPI              = 0x0006,
 582         HV_X64_INTERRUPT_TYPE_EXTINT            = 0x0007,
 583         HV_X64_INTERRUPT_TYPE_LOCALINT0         = 0x0008,
 584         HV_X64_INTERRUPT_TYPE_LOCALINT1         = 0x0009,
 585         HV_X64_INTERRUPT_TYPE_MAXIMUM           = 0x000A,
 586 };
 587
 588 #include <asm-generic/hyperv-tlfs.h>
 589
 590 #endif