8 * The legacy x87 FPU state format, as saved by FSAVE and
9 * restored by the FRSTOR instructions:
12 u32 cwd; /* FPU Control Word */
13 u32 swd; /* FPU Status Word */
14 u32 twd; /* FPU Tag Word */
15 u32 fip; /* FPU IP Offset */
16 u32 fcs; /* FPU IP Selector */
17 u32 foo; /* FPU Operand Pointer Offset */
18 u32 fos; /* FPU Operand Pointer Selector */
20 /* 8*10 bytes for each FP-reg = 80 bytes: */
23 /* Software status information [not touched by FSAVE]: */
28 * The legacy fx SSE/MMX FPU state format, as saved by FXSAVE and
29 * restored by the FXRSTOR instructions. It's similar to the FSAVE
30 * format, but differs in some areas, plus has extensions at
31 * the end for the XMM registers.
34 u16 cwd; /* Control Word */
35 u16 swd; /* Status Word */
36 u16 twd; /* Tag Word */
37 u16 fop; /* Last Instruction Opcode */
40 u64 rip; /* Instruction Pointer */
41 u64 rdp; /* Data Pointer */
44 u32 fip; /* FPU IP Offset */
45 u32 fcs; /* FPU IP Selector */
46 u32 foo; /* FPU Operand Offset */
47 u32 fos; /* FPU Operand Selector */
50 u32 mxcsr; /* MXCSR Register State */
51 u32 mxcsr_mask; /* MXCSR Mask */
53 /* 8*16 bytes for each FP-reg = 128 bytes: */
56 /* 16*16 bytes for each XMM-reg = 256 bytes: */
66 } __attribute__((aligned(16)));
68 /* Default value for fxregs_state.mxcsr: */
69 #define MXCSR_DEFAULT 0x1f80
72 * Software based FPU emulation state. This is arbitrary really,
73 * it matches the x87 format to make it easier to understand:
83 /* 8*10 bytes for each FP-reg = 80 bytes: */
91 struct math_emu_info *info;
96 * List of XSAVE features Linux knows about:
102 * Values above here are "legacy states".
103 * Those below are "extended states".
115 #define XFEATURE_MASK_FP (1 << XFEATURE_FP)
116 #define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
117 #define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
118 #define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
119 #define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
120 #define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
121 #define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
122 #define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
124 #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
125 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \
126 | XFEATURE_MASK_ZMM_Hi256 \
127 | XFEATURE_MASK_Hi16_ZMM)
129 #define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
144 * There are 16x 256-bit AVX registers named YMM0-YMM15.
145 * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
146 * and are stored in 'struct fxregs_state::xmm_space[]' in the
149 * The high 128 bits are stored here.
152 struct reg_128_bit hi_ymm[16];
155 /* Intel MPX support: */
162 * State component 3 is used for the 4 128-bit bounds registers
164 struct mpx_bndreg_state {
165 struct mpx_bndreg bndreg[4];
169 * State component 4 is used for the 64-bit user-mode MPX
170 * configuration register BNDCFGU and the 64-bit MPX status
171 * register BNDSTATUS. We call the pair "BNDCSR".
179 * The BNDCSR state is padded out to be 64-bytes in size.
181 struct mpx_bndcsr_state {
183 struct mpx_bndcsr bndcsr;
184 u8 pad_to_64_bytes[64];
188 /* AVX-512 Components: */
191 * State component 5 is used for the 8 64-bit opmask registers
192 * k0-k7 (opmask state).
194 struct avx_512_opmask_state {
199 * State component 6 is used for the upper 256 bits of the
200 * registers ZMM0-ZMM15. These 16 256-bit values are denoted
201 * ZMM0_H-ZMM15_H (ZMM_Hi256 state).
203 struct avx_512_zmm_uppers_state {
204 struct reg_256_bit zmm_upper[16];
208 * State component 7 is used for the 16 512-bit registers
209 * ZMM16-ZMM31 (Hi16_ZMM state).
211 struct avx_512_hi16_state {
212 struct reg_512_bit hi16_zmm[16];
215 struct xstate_header {
219 } __attribute__((packed));
222 * This is our most modern FPU state format, as saved by the XSAVE
223 * and restored by the XRSTOR instructions.
225 * It consists of a legacy fxregs portion, an xstate header and
226 * subsequent areas as defined by the xstate header. Not all CPUs
227 * support all the extensions, so the size of the extended area
228 * can vary quite a bit between CPUs.
231 struct fxregs_state i387;
232 struct xstate_header header;
233 u8 extended_state_area[0];
234 } __attribute__ ((packed, aligned (64)));
237 * This is a union of all the possible FPU state formats
238 * put together, so that we can pick the right one runtime.
240 * The size of the structure is determined by the largest
241 * member - which is the xsave area. The padding is there
242 * to ensure that statically-allocated task_structs (just
243 * the init_task today) have enough space.
246 struct fregs_state fsave;
247 struct fxregs_state fxsave;
248 struct swregs_state soft;
249 struct xregs_state xsave;
250 u8 __padding[PAGE_SIZE];
254 * Highest level per task FPU state data structure that
255 * contains the FPU register state plus various FPU
262 * Records the last CPU on which this context was loaded into
263 * FPU registers. (In the lazy-restore case we might be
264 * able to reuse FPU registers across multiple context switches
265 * this way, if no intermediate task used the FPU.)
267 * A value of -1 is used to indicate that the FPU state in context
268 * memory is newer than the FPU state in registers, and that the
269 * FPU state should be reloaded next time the task is run.
271 unsigned int last_cpu;
276 * This flag indicates whether this context is active: if the task
277 * is not running then we can restore from this context, if the task
278 * is running then we should save into this context.
280 unsigned char fpstate_active;
285 * This flag determines whether a given context is actively
286 * loaded into the FPU's registers and that those registers
287 * represent the task's current FPU state.
289 * Note the interaction with fpstate_active:
291 * # task does not use the FPU:
292 * fpstate_active == 0
294 * # task uses the FPU and regs are active:
295 * fpstate_active == 1 && fpregs_active == 1
297 * # the regs are inactive but still match fpstate:
298 * fpstate_active == 1 && fpregs_active == 0 && fpregs_owner == fpu
300 * The third state is what we use for the lazy restore optimization
301 * on lazy-switching CPUs.
303 unsigned char fpregs_active;
308 * In-memory copy of all FPU registers that we save/restore
309 * over context switches. If the task is using the FPU then
310 * the registers in the FPU are more recent than this state
311 * copy. If the task context-switches away then they get
312 * saved here and represent the FPU state.
314 union fpregs_state state;
316 * WARNING: 'state' is dynamically-sized. Do not put
317 * anything after it here.
321 #endif /* _ASM_X86_FPU_H */