1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_DESC_H
3 #define _ASM_X86_DESC_H
5 #include <asm/desc_defs.h>
8 #include <asm/fixmap.h>
9 #include <asm/irq_vectors.h>
10 #include <asm/cpu_entry_area.h>
12 #include <linux/debug_locks.h>
13 #include <linux/smp.h>
14 #include <linux/percpu.h>
16 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
18 desc->limit0 = info->limit & 0x0ffff;
20 desc->base0 = (info->base_addr & 0x0000ffff);
21 desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
23 desc->type = (info->read_exec_only ^ 1) << 1;
24 desc->type |= info->contents << 2;
25 /* Set the ACCESS bit so it can be mapped RO */
30 desc->p = info->seg_not_present ^ 1;
31 desc->limit1 = (info->limit & 0xf0000) >> 16;
32 desc->avl = info->useable;
33 desc->d = info->seg_32bit;
34 desc->g = info->limit_in_pages;
36 desc->base2 = (info->base_addr & 0xff000000) >> 24;
38 * Don't allow setting of the lm bit. It would confuse
39 * user_64bit_mode and would get overridden by sysret anyway.
45 struct desc_struct gdt[GDT_ENTRIES];
46 } __attribute__((aligned(PAGE_SIZE)));
48 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
50 /* Provide the original GDT */
51 static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
53 return per_cpu(gdt_page, cpu).gdt;
56 /* Provide the current original GDT */
57 static inline struct desc_struct *get_current_gdt_rw(void)
59 return this_cpu_ptr(&gdt_page)->gdt;
62 /* Provide the fixmap address of the remapped GDT */
63 static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
65 return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt;
68 /* Provide the current read-only GDT */
69 static inline struct desc_struct *get_current_gdt_ro(void)
71 return get_cpu_gdt_ro(smp_processor_id());
74 /* Provide the physical address of the GDT page. */
75 static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
77 return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
80 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
81 unsigned dpl, unsigned ist, unsigned seg)
83 gate->offset_low = (u16) func;
87 gate->bits.type = type;
88 gate->offset_middle = (u16) (func >> 16);
90 gate->segment = __KERNEL_CS;
93 gate->offset_high = (u32) (func >> 32);
100 static inline int desc_empty(const void *ptr)
102 const u32 *desc = ptr;
104 return !(desc[0] | desc[1]);
107 #ifdef CONFIG_PARAVIRT_XXL
108 #include <asm/paravirt.h>
110 #define load_TR_desc() native_load_tr_desc()
111 #define load_gdt(dtr) native_load_gdt(dtr)
112 #define load_idt(dtr) native_load_idt(dtr)
113 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
114 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
116 #define store_gdt(dtr) native_store_gdt(dtr)
117 #define store_tr(tr) (tr = native_store_tr())
119 #define load_TLS(t, cpu) native_load_tls(t, cpu)
120 #define set_ldt native_set_ldt
122 #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
123 #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
124 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
126 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
130 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
133 #endif /* CONFIG_PARAVIRT_XXL */
135 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
137 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
139 memcpy(&idt[entry], gate, sizeof(*gate));
142 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
144 memcpy(&ldt[entry], desc, 8);
148 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
153 case DESC_TSS: size = sizeof(tss_desc); break;
154 case DESC_LDT: size = sizeof(ldt_desc); break;
155 default: size = sizeof(*gdt); break;
158 memcpy(&gdt[entry], desc, size);
161 static inline void set_tssldt_descriptor(void *d, unsigned long addr,
162 unsigned type, unsigned size)
164 struct ldttss_desc *desc = d;
166 memset(desc, 0, sizeof(*desc));
168 desc->limit0 = (u16) size;
169 desc->base0 = (u16) addr;
170 desc->base1 = (addr >> 16) & 0xFF;
173 desc->limit1 = (size >> 16) & 0xF;
174 desc->base2 = (addr >> 24) & 0xFF;
176 desc->base3 = (u32) (addr >> 32);
180 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
182 struct desc_struct *d = get_cpu_gdt_rw(cpu);
185 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
187 write_gdt_entry(d, entry, &tss, DESC_TSS);
190 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
192 static inline void native_set_ldt(const void *addr, unsigned int entries)
194 if (likely(entries == 0))
195 asm volatile("lldt %w0"::"q" (0));
197 unsigned cpu = smp_processor_id();
200 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
201 entries * LDT_ENTRY_SIZE - 1);
202 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
204 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
208 static inline void native_load_gdt(const struct desc_ptr *dtr)
210 asm volatile("lgdt %0"::"m" (*dtr));
213 static __always_inline void native_load_idt(const struct desc_ptr *dtr)
215 asm volatile("lidt %0"::"m" (*dtr));
218 static inline void native_store_gdt(struct desc_ptr *dtr)
220 asm volatile("sgdt %0":"=m" (*dtr));
223 static inline void store_idt(struct desc_ptr *dtr)
225 asm volatile("sidt %0":"=m" (*dtr));
228 static inline void native_gdt_invalidate(void)
230 const struct desc_ptr invalid_gdt = {
235 native_load_gdt(&invalid_gdt);
238 static inline void native_idt_invalidate(void)
240 const struct desc_ptr invalid_idt = {
245 native_load_idt(&invalid_idt);
249 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
250 * a read-only remapping. To prevent a page fault, the GDT is switched to the
251 * original writeable version when needed.
254 static inline void native_load_tr_desc(void)
257 int cpu = raw_smp_processor_id();
259 struct desc_struct *fixmap_gdt;
261 native_store_gdt(&gdt);
262 fixmap_gdt = get_cpu_gdt_ro(cpu);
265 * If the current GDT is the read-only fixmap, swap to the original
266 * writeable version. Swap back at the end.
268 if (gdt.address == (unsigned long)fixmap_gdt) {
269 load_direct_gdt(cpu);
272 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
274 load_fixmap_gdt(cpu);
277 static inline void native_load_tr_desc(void)
279 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
283 static inline unsigned long native_store_tr(void)
287 asm volatile("str %0":"=r" (tr));
292 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
294 struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
297 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
298 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
301 DECLARE_PER_CPU(bool, __tss_limit_invalid);
303 static inline void force_reload_TR(void)
305 struct desc_struct *d = get_current_gdt_rw();
308 memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
311 * LTR requires an available TSS, and the TSS is currently
312 * busy. Make it be available so that LTR will work.
315 write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
318 this_cpu_write(__tss_limit_invalid, false);
322 * Call this if you need the TSS limit to be correct, which should be the case
323 * if and only if you have TIF_IO_BITMAP set or you're switching to a task
324 * with TIF_IO_BITMAP set.
326 static inline void refresh_tss_limit(void)
328 DEBUG_LOCKS_WARN_ON(preemptible());
330 if (unlikely(this_cpu_read(__tss_limit_invalid)))
335 * If you do something evil that corrupts the cached TSS limit (I'm looking
336 * at you, VMX exits), call this function.
338 * The optimization here is that the TSS limit only matters for Linux if the
339 * IO bitmap is in use. If the TSS limit gets forced to its minimum value,
340 * everything works except that IO bitmap will be ignored and all CPL 3 IO
341 * instructions will #GP, which is exactly what we want for normal tasks.
343 static inline void invalidate_tss_limit(void)
345 DEBUG_LOCKS_WARN_ON(preemptible());
347 if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
350 this_cpu_write(__tss_limit_invalid, true);
353 /* This intentionally ignores lm, since 32-bit apps don't have that field. */
354 #define LDT_empty(info) \
355 ((info)->base_addr == 0 && \
356 (info)->limit == 0 && \
357 (info)->contents == 0 && \
358 (info)->read_exec_only == 1 && \
359 (info)->seg_32bit == 0 && \
360 (info)->limit_in_pages == 0 && \
361 (info)->seg_not_present == 1 && \
362 (info)->useable == 0)
364 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
365 static inline bool LDT_zero(const struct user_desc *info)
367 return (info->base_addr == 0 &&
369 info->contents == 0 &&
370 info->read_exec_only == 0 &&
371 info->seg_32bit == 0 &&
372 info->limit_in_pages == 0 &&
373 info->seg_not_present == 0 &&
377 static inline void clear_LDT(void)
382 static inline unsigned long get_desc_base(const struct desc_struct *desc)
384 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
387 static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
389 desc->base0 = base & 0xffff;
390 desc->base1 = (base >> 16) & 0xff;
391 desc->base2 = (base >> 24) & 0xff;
394 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
396 return desc->limit0 | (desc->limit1 << 16);
399 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
401 desc->limit0 = limit & 0xffff;
402 desc->limit1 = (limit >> 16) & 0xf;
405 void alloc_intr_gate(unsigned int n, const void *addr);
407 static inline void init_idt_data(struct idt_data *data, unsigned int n,
412 memset(data, 0, sizeof(*data));
415 data->segment = __KERNEL_CS;
416 data->bits.type = GATE_INTERRUPT;
420 static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
422 unsigned long addr = (unsigned long) d->addr;
424 gate->offset_low = (u16) addr;
425 gate->segment = (u16) d->segment;
426 gate->bits = d->bits;
427 gate->offset_middle = (u16) (addr >> 16);
429 gate->offset_high = (u32) (addr >> 32);
434 extern unsigned long system_vectors[];
436 extern void load_current_idt(void);
437 extern void idt_setup_early_handler(void);
438 extern void idt_setup_early_traps(void);
439 extern void idt_setup_traps(void);
440 extern void idt_setup_apic_and_irq_gates(void);
441 extern bool idt_is_f00f_address(unsigned long address);
444 extern void idt_setup_early_pf(void);
446 static inline void idt_setup_early_pf(void) { }
449 extern void idt_invalidate(void);
451 #endif /* _ASM_X86_DESC_H */