1 #ifndef _ASM_X86_BARRIER_H
2 #define _ASM_X86_BARRIER_H
4 #include <asm/alternative.h>
8 * Force strict CPU ordering.
9 * And yes, this is required on UP too when we're talking
15 * Some non-Intel clones support out of order store. wmb() ceases to be a
18 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
19 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
20 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
22 #define mb() asm volatile("mfence":::"memory")
23 #define rmb() asm volatile("lfence":::"memory")
24 #define wmb() asm volatile("sfence" ::: "memory")
28 * array_index_mask_nospec() - generate a mask that is ~0UL when the
29 * bounds check succeeds and 0 otherwise
30 * @index: array element index
31 * @size: number of elements in array
36 static inline unsigned long array_index_mask_nospec(unsigned long index,
41 asm volatile ("cmp %1,%2; sbb %0,%0;"
43 :"g"(size),"r" (index)
48 /* Override the default implementation from linux/nospec.h. */
49 #define array_index_mask_nospec array_index_mask_nospec
51 /* Prevent speculative execution past this barrier. */
52 #define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
53 "lfence", X86_FEATURE_LFENCE_RDTSC)
55 #ifdef CONFIG_X86_PPRO_FENCE
56 #define dma_rmb() rmb()
58 #define dma_rmb() barrier()
60 #define dma_wmb() barrier()
64 #define smp_rmb() dma_rmb()
65 #define smp_wmb() barrier()
66 #define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
68 #define smp_mb() barrier()
69 #define smp_rmb() barrier()
70 #define smp_wmb() barrier()
71 #define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
74 #define read_barrier_depends() do { } while (0)
75 #define smp_read_barrier_depends() do { } while (0)
77 #if defined(CONFIG_X86_PPRO_FENCE)
80 * For this option x86 doesn't have a strong TSO memory
81 * model and we should fall back to full barriers.
84 #define smp_store_release(p, v) \
86 compiletime_assert_atomic_type(*p); \
91 #define smp_load_acquire(p) \
93 typeof(*p) ___p1 = READ_ONCE(*p); \
94 compiletime_assert_atomic_type(*p); \
99 #else /* regular x86 TSO memory ordering */
101 #define smp_store_release(p, v) \
103 compiletime_assert_atomic_type(*p); \
108 #define smp_load_acquire(p) \
110 typeof(*p) ___p1 = READ_ONCE(*p); \
111 compiletime_assert_atomic_type(*p); \
118 /* Atomic operations are already serializing on x86 */
119 #define smp_mb__before_atomic() do { } while (0)
120 #define smp_mb__after_atomic() do { } while (0)
123 * Make previous memory operations globally visible before
126 * MFENCE makes writes visible, but only affects load/store
127 * instructions. WRMSR is unfortunately not a load/store
128 * instruction and is unaffected by MFENCE. The LFENCE ensures
129 * that the WRMSR is not reordered.
131 * Most WRMSRs are full serializing instructions themselves and
132 * do not require this barrier. This is only required for the
133 * IA32_TSC_DEADLINE and X2APIC MSRs.
135 static inline void weak_wrmsr_fence(void)
137 asm volatile("mfence; lfence" : : : "memory");
140 #endif /* _ASM_X86_BARRIER_H */