1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
5 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
14 #include <asm/hardirq.h>
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
22 #define APIC_VERBOSE 1
25 /* Macros for apic_extnmi which controls external NMI masking */
26 #define APIC_EXTNMI_BSP 0 /* Default */
27 #define APIC_EXTNMI_ALL 1
28 #define APIC_EXTNMI_NONE 2
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
36 #define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43 extern void generic_apic_probe(void);
45 static inline void generic_apic_probe(void)
50 #ifdef CONFIG_X86_LOCAL_APIC
52 extern int apic_verbosity;
53 extern int local_apic_timer_c2_ok;
55 extern int disable_apic;
56 extern unsigned int lapic_timer_period;
58 extern enum apic_intr_mode_id apic_intr_mode;
59 enum apic_intr_mode_id {
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
64 APIC_SYMMETRIC_IO_NO_ROUTING
68 extern void __inquire_remote_apic(int apicid);
69 #else /* CONFIG_SMP */
70 static inline void __inquire_remote_apic(int apicid)
73 #endif /* CONFIG_SMP */
75 static inline void default_inquire_remote_apic(int apicid)
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
82 * With 82489DX we can't rely on apic feature bit
83 * retrieved via cpuid but still have to deal with
84 * such an apic chip so we assume that SMP configuration
85 * is found from MP table (64bit case uses ACPI mostly
86 * which set smp presence flag as well so we are safe
87 * to use this helper too).
89 static inline bool apic_from_smp_config(void)
91 return smp_found_config && !disable_apic;
95 * Basic functions accessing APICs.
97 #ifdef CONFIG_PARAVIRT
98 #include <asm/paravirt.h>
101 extern int setup_profiling_timer(unsigned int);
103 static inline void native_apic_mem_write(u32 reg, u32 v)
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
112 static inline u32 native_apic_mem_read(u32 reg)
114 return *((volatile u32 *)(APIC_BASE + reg));
117 extern void native_apic_wait_icr_idle(void);
118 extern u32 native_safe_apic_wait_icr_idle(void);
119 extern void native_apic_icr_write(u32 low, u32 id);
120 extern u64 native_apic_icr_read(void);
122 static inline bool apic_is_x2apic_enabled(void)
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
128 return msr & X2APIC_ENABLE;
131 extern void enable_IR_x2apic(void);
133 extern int get_physical_broadcast(void);
135 extern int lapic_get_maxlvt(void);
136 extern void clear_local_APIC(void);
137 extern void disconnect_bsp_APIC(int virt_wire_setup);
138 extern void disable_local_APIC(void);
139 extern void apic_soft_disable(void);
140 extern void lapic_shutdown(void);
141 extern void sync_Arb_IDs(void);
142 extern void init_bsp_APIC(void);
143 extern void apic_intr_mode_select(void);
144 extern void apic_intr_mode_init(void);
145 extern void init_apic_mappings(void);
146 void register_lapic_address(unsigned long address);
147 extern void setup_boot_APIC_clock(void);
148 extern void setup_secondary_APIC_clock(void);
149 extern void lapic_update_tsc_freq(void);
152 static inline int apic_force_enable(unsigned long addr)
157 extern int apic_force_enable(unsigned long addr);
160 extern void apic_ap_setup(void);
163 * On 32bit this is mach-xxx local
166 extern int apic_is_clustered_box(void);
168 static inline int apic_is_clustered_box(void)
174 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
175 extern void lapic_assign_system_vectors(void);
176 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
177 extern void lapic_update_legacy_vectors(void);
178 extern void lapic_online(void);
179 extern void lapic_offline(void);
180 extern bool apic_needs_pit(void);
182 extern void apic_send_IPI_allbutself(unsigned int vector);
184 #else /* !CONFIG_X86_LOCAL_APIC */
185 static inline void lapic_shutdown(void) { }
186 #define local_apic_timer_c2_ok 1
187 static inline void init_apic_mappings(void) { }
188 static inline void disable_local_APIC(void) { }
189 # define setup_boot_APIC_clock x86_init_noop
190 # define setup_secondary_APIC_clock x86_init_noop
191 static inline void lapic_update_tsc_freq(void) { }
192 static inline void init_bsp_APIC(void) { }
193 static inline void apic_intr_mode_select(void) { }
194 static inline void apic_intr_mode_init(void) { }
195 static inline void lapic_assign_system_vectors(void) { }
196 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
197 static inline bool apic_needs_pit(void) { return true; }
198 #endif /* !CONFIG_X86_LOCAL_APIC */
200 #ifdef CONFIG_X86_X2APIC
201 static inline void native_apic_msr_write(u32 reg, u32 v)
203 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
207 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
210 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
212 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
215 static inline u32 native_apic_msr_read(u32 reg)
222 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
226 static inline void native_x2apic_wait_icr_idle(void)
228 /* no need to wait for icr idle in x2apic */
232 static inline u32 native_safe_x2apic_wait_icr_idle(void)
234 /* no need to wait for icr idle in x2apic */
238 static inline void native_x2apic_icr_write(u32 low, u32 id)
240 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
243 static inline u64 native_x2apic_icr_read(void)
247 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
251 extern int x2apic_mode;
252 extern int x2apic_phys;
253 extern void __init x2apic_set_max_apicid(u32 apicid);
254 extern void __init check_x2apic(void);
255 extern void x2apic_setup(void);
256 static inline int x2apic_enabled(void)
258 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
261 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
262 #else /* !CONFIG_X86_X2APIC */
263 static inline void check_x2apic(void) { }
264 static inline void x2apic_setup(void) { }
265 static inline int x2apic_enabled(void) { return 0; }
267 #define x2apic_mode (0)
268 #define x2apic_supported() (0)
269 #endif /* !CONFIG_X86_X2APIC */
274 * Copyright 2004 James Cleverdon, IBM.
276 * Generic APIC sub-arch data struct.
278 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
279 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
283 /* Hotpath functions first */
284 void (*eoi_write)(u32 reg, u32 v);
285 void (*native_eoi_write)(u32 reg, u32 v);
286 void (*write)(u32 reg, u32 v);
287 u32 (*read)(u32 reg);
289 /* IPI related functions */
290 void (*wait_icr_idle)(void);
291 u32 (*safe_wait_icr_idle)(void);
293 void (*send_IPI)(int cpu, int vector);
294 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
295 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
296 void (*send_IPI_allbutself)(int vector);
297 void (*send_IPI_all)(int vector);
298 void (*send_IPI_self)(int vector);
300 /* dest_logical is used by the IPI functions */
303 u32 irq_delivery_mode;
306 u32 (*calc_dest_apicid)(unsigned int cpu);
308 /* ICR related functions */
309 u64 (*icr_read)(void);
310 void (*icr_write)(u32 low, u32 high);
312 /* Probe, setup and smpboot functions */
314 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
315 int (*apic_id_valid)(u32 apicid);
316 int (*apic_id_registered)(void);
318 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
319 void (*init_apic_ldr)(void);
320 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
321 void (*setup_apic_routing)(void);
322 int (*cpu_present_to_apicid)(int mps_cpu);
323 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
324 int (*check_phys_apicid_present)(int phys_apicid);
325 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
327 u32 (*get_apic_id)(unsigned long x);
328 u32 (*set_apic_id)(unsigned int id);
330 /* wakeup_secondary_cpu */
331 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
333 void (*inquire_remote_apic)(int apicid);
337 * Called very early during boot from get_smp_config(). It should
338 * return the logical apicid. x86_[bios]_cpu_to_apicid is
339 * initialized before this function is called.
341 * If logical apicid can't be determined that early, the function
342 * may return BAD_APICID. Logical apicid will be configured after
343 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
344 * won't be applied properly during early boot in this case.
346 int (*x86_32_early_logical_apicid)(int cpu);
352 * Pointer to the local APIC driver in use on this system (there's
353 * always just one such driver in use - the kernel decides via an
354 * early probing process which one it picks - and then sticks to it):
356 extern struct apic *apic;
359 * APIC drivers are probed based on how they are listed in the .apicdrivers
360 * section. So the order is important and enforced by the ordering
361 * of different apic driver files in the Makefile.
363 * For the files having two apic drivers, we use apic_drivers()
364 * to enforce the order with in them.
366 #define apic_driver(sym) \
367 static const struct apic *__apicdrivers_##sym __used \
368 __aligned(sizeof(struct apic *)) \
369 __section(.apicdrivers) = { &sym }
371 #define apic_drivers(sym1, sym2) \
372 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
373 __aligned(sizeof(struct apic *)) \
374 __section(.apicdrivers) = { &sym1, &sym2 }
376 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
379 * APIC functionality to boot other CPUs - only used on SMP:
382 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
383 extern int lapic_can_unplug_cpu(void);
386 #ifdef CONFIG_X86_LOCAL_APIC
388 static inline u32 apic_read(u32 reg)
390 return apic->read(reg);
393 static inline void apic_write(u32 reg, u32 val)
395 apic->write(reg, val);
398 static inline void apic_eoi(void)
400 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
403 static inline u64 apic_icr_read(void)
405 return apic->icr_read();
408 static inline void apic_icr_write(u32 low, u32 high)
410 apic->icr_write(low, high);
413 static inline void apic_wait_icr_idle(void)
415 apic->wait_icr_idle();
418 static inline u32 safe_apic_wait_icr_idle(void)
420 return apic->safe_wait_icr_idle();
423 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
425 #else /* CONFIG_X86_LOCAL_APIC */
427 static inline u32 apic_read(u32 reg) { return 0; }
428 static inline void apic_write(u32 reg, u32 val) { }
429 static inline void apic_eoi(void) { }
430 static inline u64 apic_icr_read(void) { return 0; }
431 static inline void apic_icr_write(u32 low, u32 high) { }
432 static inline void apic_wait_icr_idle(void) { }
433 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
434 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
436 #endif /* CONFIG_X86_LOCAL_APIC */
438 extern void apic_ack_irq(struct irq_data *data);
440 static inline void ack_APIC_irq(void)
443 * ack_APIC_irq() actually gets compiled as a single instruction
450 static inline bool lapic_vector_set_in_irr(unsigned int vector)
452 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
454 return !!(irr & (1U << (vector % 32)));
457 static inline unsigned default_get_apic_id(unsigned long x)
459 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
461 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
462 return (x >> 24) & 0xFF;
464 return (x >> 24) & 0x0F;
468 * Warm reset vector position:
470 #define TRAMPOLINE_PHYS_LOW 0x467
471 #define TRAMPOLINE_PHYS_HIGH 0x469
473 extern void generic_bigsmp_probe(void);
475 #ifdef CONFIG_X86_LOCAL_APIC
479 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
481 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
483 extern struct apic apic_noop;
485 static inline unsigned int read_apic_id(void)
487 unsigned int reg = apic_read(APIC_ID);
489 return apic->get_apic_id(reg);
492 extern int default_apic_id_valid(u32 apicid);
493 extern int default_acpi_madt_oem_check(char *, char *);
494 extern void default_setup_apic_routing(void);
496 extern u32 apic_default_calc_apicid(unsigned int cpu);
497 extern u32 apic_flat_calc_apicid(unsigned int cpu);
499 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
500 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
501 extern int default_cpu_present_to_apicid(int mps_cpu);
502 extern int default_check_phys_apicid_present(int phys_apicid);
504 #endif /* CONFIG_X86_LOCAL_APIC */
507 bool apic_id_is_primary_thread(unsigned int id);
508 void apic_smt_update(void);
510 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
511 static inline void apic_smt_update(void) { }
514 extern void irq_enter(void);
515 extern void irq_exit(void);
517 static inline void entering_irq(void)
520 kvm_set_cpu_l1tf_flush_l1d();
523 static inline void entering_ack_irq(void)
529 static inline void ipi_entering_ack_irq(void)
533 kvm_set_cpu_l1tf_flush_l1d();
536 static inline void exiting_irq(void)
541 static inline void exiting_ack_irq(void)
547 extern void ioapic_zap_locks(void);
549 #endif /* _ASM_X86_APIC_H */