1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
6 #include <asm/alternative.h>
7 #include <asm/cpufeature.h>
8 #include <asm/apicdef.h>
9 #include <linux/atomic.h>
10 #include <asm/fixmap.h>
11 #include <asm/mpspec.h>
13 #include <asm/hardirq.h>
15 #define ARCH_APICTIMER_STOPS_ON_C3 1
21 #define APIC_VERBOSE 1
24 /* Macros for apic_extnmi which controls external NMI masking */
25 #define APIC_EXTNMI_BSP 0 /* Default */
26 #define APIC_EXTNMI_ALL 1
27 #define APIC_EXTNMI_NONE 2
30 * Define the default level of output to be very little
31 * This can be turned up by using apic=verbose for more
32 * information and apic=debug for _lots_ of information.
33 * apic_verbosity is defined in apic.c
35 #define apic_printk(v, s, a...) do { \
36 if ((v) <= apic_verbosity) \
41 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
42 extern void generic_apic_probe(void);
44 static inline void generic_apic_probe(void)
49 #ifdef CONFIG_X86_LOCAL_APIC
51 extern int apic_verbosity;
52 extern int local_apic_timer_c2_ok;
54 extern int disable_apic;
55 extern unsigned int lapic_timer_frequency;
58 extern void __inquire_remote_apic(int apicid);
59 #else /* CONFIG_SMP */
60 static inline void __inquire_remote_apic(int apicid)
63 #endif /* CONFIG_SMP */
65 static inline void default_inquire_remote_apic(int apicid)
67 if (apic_verbosity >= APIC_DEBUG)
68 __inquire_remote_apic(apicid);
72 * With 82489DX we can't rely on apic feature bit
73 * retrieved via cpuid but still have to deal with
74 * such an apic chip so we assume that SMP configuration
75 * is found from MP table (64bit case uses ACPI mostly
76 * which set smp presence flag as well so we are safe
77 * to use this helper too).
79 static inline bool apic_from_smp_config(void)
81 return smp_found_config && !disable_apic;
85 * Basic functions accessing APICs.
87 #ifdef CONFIG_PARAVIRT
88 #include <asm/paravirt.h>
91 extern int setup_profiling_timer(unsigned int);
93 static inline void native_apic_mem_write(u32 reg, u32 v)
95 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
97 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
98 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
99 ASM_OUTPUT2("0" (v), "m" (*addr)));
102 static inline u32 native_apic_mem_read(u32 reg)
104 return *((volatile u32 *)(APIC_BASE + reg));
107 extern void native_apic_wait_icr_idle(void);
108 extern u32 native_safe_apic_wait_icr_idle(void);
109 extern void native_apic_icr_write(u32 low, u32 id);
110 extern u64 native_apic_icr_read(void);
112 static inline bool apic_is_x2apic_enabled(void)
116 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
118 return msr & X2APIC_ENABLE;
121 extern void enable_IR_x2apic(void);
123 extern int get_physical_broadcast(void);
125 extern int lapic_get_maxlvt(void);
126 extern void clear_local_APIC(void);
127 extern void disconnect_bsp_APIC(int virt_wire_setup);
128 extern void disable_local_APIC(void);
129 extern void lapic_shutdown(void);
130 extern void sync_Arb_IDs(void);
131 extern void init_bsp_APIC(void);
132 extern void setup_local_APIC(void);
133 extern void init_apic_mappings(void);
134 void register_lapic_address(unsigned long address);
135 extern void setup_boot_APIC_clock(void);
136 extern void setup_secondary_APIC_clock(void);
137 extern void lapic_update_tsc_freq(void);
138 extern int APIC_init_uniprocessor(void);
141 static inline int apic_force_enable(unsigned long addr)
146 extern int apic_force_enable(unsigned long addr);
149 extern int apic_bsp_setup(bool upmode);
150 extern void apic_ap_setup(void);
153 * On 32bit this is mach-xxx local
156 extern int apic_is_clustered_box(void);
158 static inline int apic_is_clustered_box(void)
164 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
166 #else /* !CONFIG_X86_LOCAL_APIC */
167 static inline void lapic_shutdown(void) { }
168 #define local_apic_timer_c2_ok 1
169 static inline void init_apic_mappings(void) { }
170 static inline void disable_local_APIC(void) { }
171 # define setup_boot_APIC_clock x86_init_noop
172 # define setup_secondary_APIC_clock x86_init_noop
173 static inline void lapic_update_tsc_freq(void) { }
174 #endif /* !CONFIG_X86_LOCAL_APIC */
176 #ifdef CONFIG_X86_X2APIC
177 static inline void native_apic_msr_write(u32 reg, u32 v)
179 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
183 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
186 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
188 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
191 static inline u32 native_apic_msr_read(u32 reg)
198 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
202 static inline void native_x2apic_wait_icr_idle(void)
204 /* no need to wait for icr idle in x2apic */
208 static inline u32 native_safe_x2apic_wait_icr_idle(void)
210 /* no need to wait for icr idle in x2apic */
214 static inline void native_x2apic_icr_write(u32 low, u32 id)
216 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
219 static inline u64 native_x2apic_icr_read(void)
223 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
227 extern int x2apic_mode;
228 extern int x2apic_phys;
229 extern void __init check_x2apic(void);
230 extern void x2apic_setup(void);
231 static inline int x2apic_enabled(void)
233 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
236 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
237 #else /* !CONFIG_X86_X2APIC */
238 static inline void check_x2apic(void) { }
239 static inline void x2apic_setup(void) { }
240 static inline int x2apic_enabled(void) { return 0; }
242 #define x2apic_mode (0)
243 #define x2apic_supported() (0)
244 #endif /* !CONFIG_X86_X2APIC */
249 * Copyright 2004 James Cleverdon, IBM.
250 * Subject to the GNU Public License, v.2
252 * Generic APIC sub-arch data struct.
254 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
255 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
262 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
263 int (*apic_id_valid)(int apicid);
264 int (*apic_id_registered)(void);
266 u32 irq_delivery_mode;
269 const struct cpumask *(*target_cpus)(void);
274 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
276 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
277 const struct cpumask *mask);
278 void (*init_apic_ldr)(void);
280 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
282 void (*setup_apic_routing)(void);
283 int (*cpu_present_to_apicid)(int mps_cpu);
284 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
285 int (*check_phys_apicid_present)(int phys_apicid);
286 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
288 unsigned int (*get_apic_id)(unsigned long x);
289 /* Can't be NULL on 64-bit */
290 unsigned long (*set_apic_id)(unsigned int id);
292 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask,
293 struct irq_data *irqdata,
294 unsigned int *apicid);
297 void (*send_IPI)(int cpu, int vector);
298 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
299 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
301 void (*send_IPI_allbutself)(int vector);
302 void (*send_IPI_all)(int vector);
303 void (*send_IPI_self)(int vector);
305 /* wakeup_secondary_cpu */
306 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
308 void (*inquire_remote_apic)(int apicid);
311 u32 (*read)(u32 reg);
312 void (*write)(u32 reg, u32 v);
314 * ->eoi_write() has the same signature as ->write().
316 * Drivers can support both ->eoi_write() and ->write() by passing the same
317 * callback value. Kernel can override ->eoi_write() and fall back
320 void (*eoi_write)(u32 reg, u32 v);
321 void (*native_eoi_write)(u32 reg, u32 v);
322 u64 (*icr_read)(void);
323 void (*icr_write)(u32 low, u32 high);
324 void (*wait_icr_idle)(void);
325 u32 (*safe_wait_icr_idle)(void);
329 * Called very early during boot from get_smp_config(). It should
330 * return the logical apicid. x86_[bios]_cpu_to_apicid is
331 * initialized before this function is called.
333 * If logical apicid can't be determined that early, the function
334 * may return BAD_APICID. Logical apicid will be configured after
335 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
336 * won't be applied properly during early boot in this case.
338 int (*x86_32_early_logical_apicid)(int cpu);
343 * Pointer to the local APIC driver in use on this system (there's
344 * always just one such driver in use - the kernel decides via an
345 * early probing process which one it picks - and then sticks to it):
347 extern struct apic *apic;
350 * APIC drivers are probed based on how they are listed in the .apicdrivers
351 * section. So the order is important and enforced by the ordering
352 * of different apic driver files in the Makefile.
354 * For the files having two apic drivers, we use apic_drivers()
355 * to enforce the order with in them.
357 #define apic_driver(sym) \
358 static const struct apic *__apicdrivers_##sym __used \
359 __aligned(sizeof(struct apic *)) \
360 __section(.apicdrivers) = { &sym }
362 #define apic_drivers(sym1, sym2) \
363 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
364 __aligned(sizeof(struct apic *)) \
365 __section(.apicdrivers) = { &sym1, &sym2 }
367 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
370 * APIC functionality to boot other CPUs - only used on SMP:
373 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
376 #ifdef CONFIG_X86_LOCAL_APIC
378 static inline u32 apic_read(u32 reg)
380 return apic->read(reg);
383 static inline void apic_write(u32 reg, u32 val)
385 apic->write(reg, val);
388 static inline void apic_eoi(void)
390 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
393 static inline u64 apic_icr_read(void)
395 return apic->icr_read();
398 static inline void apic_icr_write(u32 low, u32 high)
400 apic->icr_write(low, high);
403 static inline void apic_wait_icr_idle(void)
405 apic->wait_icr_idle();
408 static inline u32 safe_apic_wait_icr_idle(void)
410 return apic->safe_wait_icr_idle();
413 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
415 #else /* CONFIG_X86_LOCAL_APIC */
417 static inline u32 apic_read(u32 reg) { return 0; }
418 static inline void apic_write(u32 reg, u32 val) { }
419 static inline void apic_eoi(void) { }
420 static inline u64 apic_icr_read(void) { return 0; }
421 static inline void apic_icr_write(u32 low, u32 high) { }
422 static inline void apic_wait_icr_idle(void) { }
423 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
424 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
426 #endif /* CONFIG_X86_LOCAL_APIC */
428 static inline void ack_APIC_irq(void)
431 * ack_APIC_irq() actually gets compiled as a single instruction
437 static inline unsigned default_get_apic_id(unsigned long x)
439 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
441 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
442 return (x >> 24) & 0xFF;
444 return (x >> 24) & 0x0F;
448 * Warm reset vector position:
450 #define TRAMPOLINE_PHYS_LOW 0x467
451 #define TRAMPOLINE_PHYS_HIGH 0x469
454 extern void apic_send_IPI_self(int vector);
456 DECLARE_PER_CPU(int, x2apic_extra_bits);
458 extern int default_cpu_present_to_apicid(int mps_cpu);
459 extern int default_check_phys_apicid_present(int phys_apicid);
462 extern void generic_bigsmp_probe(void);
465 #ifdef CONFIG_X86_LOCAL_APIC
469 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
471 static inline const struct cpumask *default_target_cpus(void)
474 return cpu_online_mask;
476 return cpumask_of(0);
480 static inline const struct cpumask *online_target_cpus(void)
482 return cpu_online_mask;
485 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
488 static inline unsigned int read_apic_id(void)
492 reg = apic_read(APIC_ID);
494 return apic->get_apic_id(reg);
497 static inline int default_apic_id_valid(int apicid)
499 return (apicid < 255);
502 extern int default_acpi_madt_oem_check(char *, char *);
504 extern void default_setup_apic_routing(void);
506 extern struct apic apic_noop;
510 static inline int noop_x86_32_early_logical_apicid(int cpu)
516 * Set up the logical destination ID.
518 * Intel recommends to set DFR, LDR and TPR before enabling
519 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
520 * document number 292116). So here it goes...
522 extern void default_init_apic_ldr(void);
524 static inline int default_apic_id_registered(void)
526 return physid_isset(read_apic_id(), phys_cpu_present_map);
529 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
531 return cpuid_apic >> index_msb;
536 extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask,
537 struct irq_data *irqdata,
538 unsigned int *apicid);
539 extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask,
540 struct irq_data *irqdata,
541 unsigned int *apicid);
544 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
545 const struct cpumask *mask)
547 /* Careful. Some cpus do not strictly honor the set of cpus
548 * specified in the interrupt destination when using lowest
549 * priority interrupt delivery mode.
551 * In particular there was a hyperthreading cpu observed to
552 * deliver interrupts to the wrong hyperthread when only one
553 * hyperthread was specified in the interrupt desitination.
555 cpumask_clear(retmask);
556 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
560 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
561 const struct cpumask *mask)
563 cpumask_copy(retmask, cpumask_of(cpu));
566 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
568 return physid_isset(apicid, *map);
571 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
576 static inline int __default_cpu_present_to_apicid(int mps_cpu)
578 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
579 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
585 __default_check_phys_apicid_present(int phys_apicid)
587 return physid_isset(phys_apicid, phys_cpu_present_map);
591 static inline int default_cpu_present_to_apicid(int mps_cpu)
593 return __default_cpu_present_to_apicid(mps_cpu);
597 default_check_phys_apicid_present(int phys_apicid)
599 return __default_check_phys_apicid_present(phys_apicid);
602 extern int default_cpu_present_to_apicid(int mps_cpu);
603 extern int default_check_phys_apicid_present(int phys_apicid);
606 #endif /* CONFIG_X86_LOCAL_APIC */
609 bool apic_id_is_primary_thread(unsigned int id);
611 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
614 extern void irq_enter(void);
615 extern void irq_exit(void);
617 static inline void entering_irq(void)
620 kvm_set_cpu_l1tf_flush_l1d();
623 static inline void entering_ack_irq(void)
629 static inline void ipi_entering_ack_irq(void)
633 kvm_set_cpu_l1tf_flush_l1d();
636 static inline void exiting_irq(void)
641 static inline void exiting_ack_irq(void)
647 extern void ioapic_zap_locks(void);
649 #endif /* _ASM_X86_APIC_H */