1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V specific APIC code.
6 * Copyright (C) 2018, Microsoft, Inc.
8 * Author : K. Y. Srinivasan <kys@microsoft.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17 * NON INFRINGEMENT. See the GNU General Public License for more
22 #include <linux/types.h>
23 #include <linux/version.h>
24 #include <linux/vmalloc.h>
26 #include <linux/clockchips.h>
27 #include <linux/hyperv.h>
28 #include <linux/slab.h>
29 #include <linux/cpuhotplug.h>
30 #include <asm/hypervisor.h>
31 #include <asm/mshyperv.h>
34 #include <asm/trace/hyperv.h>
36 static struct apic orig_apic;
38 static u64 hv_apic_icr_read(void)
42 rdmsrl(HV_X64_MSR_ICR, reg_val);
46 static void hv_apic_icr_write(u32 low, u32 id)
50 reg_val = SET_APIC_DEST_FIELD(id);
51 reg_val = reg_val << 32;
54 wrmsrl(HV_X64_MSR_ICR, reg_val);
57 static u32 hv_apic_read(u32 reg)
63 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
66 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
70 return native_apic_mem_read(reg);
74 static void hv_apic_write(u32 reg, u32 val)
78 wrmsr(HV_X64_MSR_EOI, val, 0);
81 wrmsr(HV_X64_MSR_TPR, val, 0);
84 native_apic_mem_write(reg, val);
88 static void hv_apic_eoi_write(u32 reg, u32 val)
90 wrmsr(HV_X64_MSR_EOI, val, 0);
94 * IPI implementation on Hyper-V.
96 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
98 struct hv_send_ipi_ex **arg;
99 struct hv_send_ipi_ex *ipi_arg;
104 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
107 local_irq_save(flags);
108 arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
111 if (unlikely(!ipi_arg))
112 goto ipi_mask_ex_done;
114 ipi_arg->vector = vector;
115 ipi_arg->reserved = 0;
116 ipi_arg->vp_set.valid_bank_mask = 0;
118 if (!cpumask_equal(mask, cpu_present_mask)) {
119 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
120 nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
123 goto ipi_mask_ex_done;
125 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
127 ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
131 local_irq_restore(flags);
132 return ((ret == 0) ? true : false);
135 static bool __send_ipi_mask(const struct cpumask *mask, int vector)
138 struct hv_send_ipi ipi_arg;
141 trace_hyperv_send_ipi_mask(mask, vector);
143 if (cpumask_empty(mask))
146 if (!hv_hypercall_pg)
149 if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
153 * From the supplied CPU set we need to figure out if we can get away
154 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
155 * highest VP number in the set is < 64. As VP numbers are usually in
156 * ascending order and match Linux CPU ids, here is an optimization:
157 * we check the VP number for the highest bit in the supplied set first
158 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
159 * a must. We will also check all VP numbers when walking the supplied
160 * CPU set to remain correct in all cases.
162 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
163 goto do_ex_hypercall;
165 ipi_arg.vector = vector;
166 ipi_arg.cpu_mask = 0;
168 for_each_cpu(cur_cpu, mask) {
169 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
170 if (vcpu == VP_INVAL)
174 * This particular version of the IPI hypercall can
175 * only target upto 64 CPUs.
178 goto do_ex_hypercall;
180 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
183 ret = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
185 return ((ret == 0) ? true : false);
188 return __send_ipi_mask_ex(mask, vector);
191 static bool __send_ipi_one(int cpu, int vector)
193 struct cpumask mask = CPU_MASK_NONE;
195 cpumask_set_cpu(cpu, &mask);
196 return __send_ipi_mask(&mask, vector);
199 static void hv_send_ipi(int cpu, int vector)
201 if (!__send_ipi_one(cpu, vector))
202 orig_apic.send_IPI(cpu, vector);
205 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
207 if (!__send_ipi_mask(mask, vector))
208 orig_apic.send_IPI_mask(mask, vector);
211 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
213 unsigned int this_cpu = smp_processor_id();
214 struct cpumask new_mask;
215 const struct cpumask *local_mask;
217 cpumask_copy(&new_mask, mask);
218 cpumask_clear_cpu(this_cpu, &new_mask);
219 local_mask = &new_mask;
220 if (!__send_ipi_mask(local_mask, vector))
221 orig_apic.send_IPI_mask_allbutself(mask, vector);
224 static void hv_send_ipi_allbutself(int vector)
226 hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
229 static void hv_send_ipi_all(int vector)
231 if (!__send_ipi_mask(cpu_online_mask, vector))
232 orig_apic.send_IPI_all(vector);
235 static void hv_send_ipi_self(int vector)
237 if (!__send_ipi_one(smp_processor_id(), vector))
238 orig_apic.send_IPI_self(vector);
241 void __init hv_apic_init(void)
243 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
244 pr_info("Hyper-V: Using IPI hypercalls\n");
246 * Set the IPI entry points.
250 apic->send_IPI = hv_send_ipi;
251 apic->send_IPI_mask = hv_send_ipi_mask;
252 apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
253 apic->send_IPI_allbutself = hv_send_ipi_allbutself;
254 apic->send_IPI_all = hv_send_ipi_all;
255 apic->send_IPI_self = hv_send_ipi_self;
258 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
259 pr_info("Hyper-V: Using MSR based APIC access\n");
260 apic_set_eoi_write(hv_apic_eoi_write);
261 apic->read = hv_apic_read;
262 apic->write = hv_apic_write;
263 apic->icr_write = hv_apic_icr_write;
264 apic->icr_read = hv_apic_icr_read;