2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
17 #include <asm/fpu/xstate.h>
18 #include <asm/intel_ds.h>
21 /* To enable MSR tracing please use the generic trace points. */
25 * register -------------------------------
26 * | HT | no HT | HT | no HT |
27 *-----------------------------------------
28 * offcore | core | core | cpu | core |
29 * lbr_sel | core | core | cpu | core |
30 * ld_lat | cpu | core | cpu | core |
31 *-----------------------------------------
33 * Given that there is a small number of shared regs,
34 * we can pre-allocate their slot in the per-cpu
35 * per-core reg tables.
38 EXTRA_REG_NONE = -1, /* not used */
40 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
41 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
42 EXTRA_REG_LBR = 2, /* lbr_select */
43 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
44 EXTRA_REG_FE = 4, /* fe_* */
46 EXTRA_REG_MAX /* number of entries needed */
49 struct event_constraint {
51 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
62 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
64 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
68 * struct hw_perf_event.flags flags
70 #define PERF_X86_EVENT_PEBS_LDLAT 0x00001 /* ld+ldlat data address sampling */
71 #define PERF_X86_EVENT_PEBS_ST 0x00002 /* st data address sampling */
72 #define PERF_X86_EVENT_PEBS_ST_HSW 0x00004 /* haswell style datala, store */
73 #define PERF_X86_EVENT_PEBS_LD_HSW 0x00008 /* haswell style datala, load */
74 #define PERF_X86_EVENT_PEBS_NA_HSW 0x00010 /* haswell style datala, unknown */
75 #define PERF_X86_EVENT_EXCL 0x00020 /* HT exclusivity on counter */
76 #define PERF_X86_EVENT_DYNAMIC 0x00040 /* dynamic alloc'd constraint */
78 #define PERF_X86_EVENT_EXCL_ACCT 0x00100 /* accounted EXCL event */
79 #define PERF_X86_EVENT_AUTO_RELOAD 0x00200 /* use PEBS auto-reload */
80 #define PERF_X86_EVENT_LARGE_PEBS 0x00400 /* use large PEBS */
81 #define PERF_X86_EVENT_PEBS_VIA_PT 0x00800 /* use PT buffer for PEBS */
82 #define PERF_X86_EVENT_PAIR 0x01000 /* Large Increment per Cycle */
83 #define PERF_X86_EVENT_LBR_SELECT 0x02000 /* Save/Restore MSR_LBR_SELECT */
84 #define PERF_X86_EVENT_TOPDOWN 0x04000 /* Count Topdown slots/metrics events */
85 #define PERF_X86_EVENT_PEBS_STLAT 0x08000 /* st+stlat data address sampling */
86 #define PERF_X86_EVENT_AMD_BRS 0x10000 /* AMD Branch Sampling */
88 static inline bool is_topdown_count(struct perf_event *event)
90 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
93 static inline bool is_metric_event(struct perf_event *event)
95 u64 config = event->attr.config;
97 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
98 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
99 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
102 static inline bool is_slots_event(struct perf_event *event)
104 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
107 static inline bool is_topdown_event(struct perf_event *event)
109 return is_metric_event(event) || is_slots_event(event);
113 int nb_id; /* NorthBridge id */
114 int refcnt; /* reference count */
115 struct perf_event *owners[X86_PMC_IDX_MAX];
116 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
119 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
120 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
121 #define PEBS_OUTPUT_OFFSET 61
122 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
123 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
124 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
127 * Flags PEBS can handle without an PMI.
129 * TID can only be handled by flushing at context switch.
130 * REGS_USER can be handled for events limited to ring 3.
133 #define LARGE_PEBS_FLAGS \
134 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
135 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
136 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
137 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
138 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
139 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
141 #define PEBS_GP_REGS \
142 ((1ULL << PERF_REG_X86_AX) | \
143 (1ULL << PERF_REG_X86_BX) | \
144 (1ULL << PERF_REG_X86_CX) | \
145 (1ULL << PERF_REG_X86_DX) | \
146 (1ULL << PERF_REG_X86_DI) | \
147 (1ULL << PERF_REG_X86_SI) | \
148 (1ULL << PERF_REG_X86_SP) | \
149 (1ULL << PERF_REG_X86_BP) | \
150 (1ULL << PERF_REG_X86_IP) | \
151 (1ULL << PERF_REG_X86_FLAGS) | \
152 (1ULL << PERF_REG_X86_R8) | \
153 (1ULL << PERF_REG_X86_R9) | \
154 (1ULL << PERF_REG_X86_R10) | \
155 (1ULL << PERF_REG_X86_R11) | \
156 (1ULL << PERF_REG_X86_R12) | \
157 (1ULL << PERF_REG_X86_R13) | \
158 (1ULL << PERF_REG_X86_R14) | \
159 (1ULL << PERF_REG_X86_R15))
162 * Per register state.
165 raw_spinlock_t lock; /* per-core: protect structure */
166 u64 config; /* extra MSR config */
167 u64 reg; /* extra MSR number */
168 atomic_t ref; /* reference count */
174 * Used to coordinate shared registers between HT threads or
175 * among events on a single PMU.
177 struct intel_shared_regs {
178 struct er_account regs[EXTRA_REG_MAX];
179 int refcnt; /* per-core: #HT threads */
180 unsigned core_id; /* per-core: core id */
183 enum intel_excl_state_type {
184 INTEL_EXCL_UNUSED = 0, /* counter is unused */
185 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
186 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
189 struct intel_excl_states {
190 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
191 bool sched_started; /* true if scheduling has started */
194 struct intel_excl_cntrs {
197 struct intel_excl_states states[2];
200 u16 has_exclusive[2];
201 u32 exclusive_present;
204 int refcnt; /* per-core: #HT threads */
205 unsigned core_id; /* per-core: core id */
208 struct x86_perf_task_context;
209 #define MAX_LBR_ENTRIES 32
212 LBR_FORMAT_32 = 0x00,
213 LBR_FORMAT_LIP = 0x01,
214 LBR_FORMAT_EIP = 0x02,
215 LBR_FORMAT_EIP_FLAGS = 0x03,
216 LBR_FORMAT_EIP_FLAGS2 = 0x04,
217 LBR_FORMAT_INFO = 0x05,
218 LBR_FORMAT_TIME = 0x06,
219 LBR_FORMAT_INFO2 = 0x07,
220 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2,
224 X86_PERF_KFREE_SHARED = 0,
225 X86_PERF_KFREE_EXCL = 1,
229 struct cpu_hw_events {
231 * Generic x86 PMC bits
233 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
234 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
235 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
238 int n_events; /* the # of events in the below arrays */
239 int n_added; /* the # last events in the below arrays;
240 they've never been enabled yet */
241 int n_txn; /* the # last events in the below arrays;
242 added in the current transaction */
245 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
246 u64 tags[X86_PMC_IDX_MAX];
248 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
249 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
251 int n_excl; /* the number of exclusive events */
253 unsigned int txn_flags;
257 * Intel DebugStore bits
259 struct debug_store *ds;
268 /* Current super set of events hardware configuration */
270 u64 active_pebs_data_cfg;
271 int pebs_record_size;
278 struct perf_branch_stack lbr_stack;
279 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
281 struct er_account *lbr_sel;
282 struct er_account *lbr_ctl;
291 * Intel host/guest exclude bits
293 u64 intel_ctrl_guest_mask;
294 u64 intel_ctrl_host_mask;
295 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
298 * Intel checkpoint mask
303 * manage shared (per-core, per-cpu) registers
304 * used on Intel NHM/WSM/SNB
306 struct intel_shared_regs *shared_regs;
308 * manage exclusive counter access between hyperthread
310 struct event_constraint *constraint_list; /* in enable order */
311 struct intel_excl_cntrs *excl_cntrs;
312 int excl_thread_id; /* 0 or 1 */
315 * SKL TSX_FORCE_ABORT shadow
322 /* number of accepted metrics events */
328 struct amd_nb *amd_nb;
329 int brs_active; /* BRS is enabled */
331 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
332 u64 perf_ctr_virt_mask;
333 int n_pair; /* Large increment events */
335 void *kfree_on_online[X86_PERF_KFREE_MAX];
340 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
341 { .idxmsk64 = (n) }, \
350 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
351 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
353 #define EVENT_CONSTRAINT(c, n, m) \
354 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
357 * The constraint_match() function only works for 'simple' event codes
358 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
360 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
361 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
363 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
364 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
365 0, PERF_X86_EVENT_EXCL)
368 * The overlap flag marks event constraints with overlapping counter
369 * masks. This is the case if the counter mask of such an event is not
370 * a subset of any other counter mask of a constraint with an equal or
371 * higher weight, e.g.:
373 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
374 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
375 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
377 * The event scheduler may not select the correct counter in the first
378 * cycle because it needs to know which subsequent events will be
379 * scheduled. It may fail to schedule the events then. So we set the
380 * overlap flag for such constraints to give the scheduler a hint which
381 * events to select for counter rescheduling.
383 * Care must be taken as the rescheduling algorithm is O(n!) which
384 * will increase scheduling cycles for an over-committed system
385 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
386 * and its counter masks must be kept at a minimum.
388 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
389 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
392 * Constraint on the Event code.
394 #define INTEL_EVENT_CONSTRAINT(c, n) \
395 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
398 * Constraint on a range of Event codes
400 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
401 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
404 * Constraint on the Event code + UMask + fixed-mask
406 * filter mask to validate fixed counter events.
407 * the following filters disqualify for fixed counters:
412 * - in_tx_checkpointed
413 * The other filters are supported by fixed counters.
414 * The any-thread option is supported starting with v3.
416 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
417 #define FIXED_EVENT_CONSTRAINT(c, n) \
418 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
421 * The special metric counters do not actually exist. They are calculated from
422 * the combination of the FxCtr3 + MSR_PERF_METRICS.
424 * The special metric counters are mapped to a dummy offset for the scheduler.
425 * The sharing between multiple users of the same metric without multiplexing
426 * is not allowed, even though the hardware supports that in principle.
429 #define METRIC_EVENT_CONSTRAINT(c, n) \
430 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
431 INTEL_ARCH_EVENT_MASK)
434 * Constraint on the Event code + UMask
436 #define INTEL_UEVENT_CONSTRAINT(c, n) \
437 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
439 /* Constraint on specific umask bit only + event */
440 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
441 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
443 /* Like UEVENT_CONSTRAINT, but match flags too */
444 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
445 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
447 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
448 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
449 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
451 #define INTEL_PLD_CONSTRAINT(c, n) \
452 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
453 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
455 #define INTEL_PSD_CONSTRAINT(c, n) \
456 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
457 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
459 #define INTEL_PST_CONSTRAINT(c, n) \
460 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
461 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
463 /* Event constraint, but match on all event flags too. */
464 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
465 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
467 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
468 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
470 /* Check only flags, but allow all event/umask */
471 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
472 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
474 /* Check flags and event code, and set the HSW store flag */
475 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
476 __EVENT_CONSTRAINT(code, n, \
477 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
478 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
480 /* Check flags and event code, and set the HSW load flag */
481 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
482 __EVENT_CONSTRAINT(code, n, \
483 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
484 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
486 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
487 __EVENT_CONSTRAINT_RANGE(code, end, n, \
488 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
489 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
491 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
492 __EVENT_CONSTRAINT(code, n, \
493 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
495 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
497 /* Check flags and event code/umask, and set the HSW store flag */
498 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
499 __EVENT_CONSTRAINT(code, n, \
500 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
501 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
503 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
504 __EVENT_CONSTRAINT(code, n, \
505 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
507 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
509 /* Check flags and event code/umask, and set the HSW load flag */
510 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
511 __EVENT_CONSTRAINT(code, n, \
512 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
513 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
515 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
516 __EVENT_CONSTRAINT(code, n, \
517 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
519 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
521 /* Check flags and event code/umask, and set the HSW N/A flag */
522 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
523 __EVENT_CONSTRAINT(code, n, \
524 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
525 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
529 * We define the end marker as having a weight of -1
530 * to enable blacklisting of events using a counter bitmask
531 * of zero and thus a weight of zero.
532 * The end marker has a weight that cannot possibly be
533 * obtained from counting the bits in the bitmask.
535 #define EVENT_CONSTRAINT_END { .weight = -1 }
538 * Check for end marker with weight == -1
540 #define for_each_event_constraint(e, c) \
541 for ((e) = (c); (e)->weight != -1; (e)++)
544 * Extra registers for specific events.
546 * Some events need large masks and require external MSRs.
547 * Those extra MSRs end up being shared for all events on
548 * a PMU and sometimes between PMU of sibling HT threads.
549 * In either case, the kernel needs to handle conflicting
550 * accesses to those extra, shared, regs. The data structure
551 * to manage those registers is stored in cpu_hw_event.
558 int idx; /* per_xxx->regs[] reg index */
559 bool extra_msr_access;
562 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
565 .config_mask = (m), \
566 .valid_mask = (vm), \
567 .idx = EXTRA_REG_##i, \
568 .extra_msr_access = true, \
571 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
572 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
574 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
575 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
576 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
578 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
579 INTEL_UEVENT_EXTRA_REG(c, \
580 MSR_PEBS_LD_LAT_THRESHOLD, \
584 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
586 union perf_capabilities {
594 * PMU supports separate counter range for writing
597 u64 full_width_write:1;
600 u64 pebs_output_pt_available:1;
601 u64 anythread_deprecated:1;
606 struct x86_pmu_quirk {
607 struct x86_pmu_quirk *next;
611 union x86_pmu_config {
632 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
635 x86_lbr_exclusive_lbr,
636 x86_lbr_exclusive_bts,
637 x86_lbr_exclusive_pt,
638 x86_lbr_exclusive_max,
641 struct x86_hybrid_pmu {
645 cpumask_t supported_cpus;
646 union perf_capabilities intel_cap;
650 int num_counters_fixed;
651 struct event_constraint unconstrained;
653 u64 hw_cache_event_ids
654 [PERF_COUNT_HW_CACHE_MAX]
655 [PERF_COUNT_HW_CACHE_OP_MAX]
656 [PERF_COUNT_HW_CACHE_RESULT_MAX];
657 u64 hw_cache_extra_regs
658 [PERF_COUNT_HW_CACHE_MAX]
659 [PERF_COUNT_HW_CACHE_OP_MAX]
660 [PERF_COUNT_HW_CACHE_RESULT_MAX];
661 struct event_constraint *event_constraints;
662 struct event_constraint *pebs_constraints;
663 struct extra_reg *extra_regs;
665 unsigned int late_ack :1,
670 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)
672 return container_of(pmu, struct x86_hybrid_pmu, pmu);
675 extern struct static_key_false perf_is_hybrid;
676 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid)
678 #define hybrid(_pmu, _field) \
680 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
682 if (is_hybrid() && (_pmu)) \
683 __Fp = &hybrid_pmu(_pmu)->_field; \
688 #define hybrid_var(_pmu, _var) \
690 typeof(&_var) __Fp = &_var; \
692 if (is_hybrid() && (_pmu)) \
693 __Fp = &hybrid_pmu(_pmu)->_var; \
698 #define hybrid_bit(_pmu, _field) \
700 bool __Fp = x86_pmu._field; \
702 if (is_hybrid() && (_pmu)) \
703 __Fp = hybrid_pmu(_pmu)->_field; \
708 enum hybrid_pmu_type {
712 hybrid_big_small = hybrid_big | hybrid_small,
715 #define X86_HYBRID_PMU_ATOM_IDX 0
716 #define X86_HYBRID_PMU_CORE_IDX 1
718 #define X86_HYBRID_NUM_PMUS 2
721 * struct x86_pmu - generic x86 pmu
725 * Generic x86 PMC bits
729 int (*handle_irq)(struct pt_regs *);
730 void (*disable_all)(void);
731 void (*enable_all)(int added);
732 void (*enable)(struct perf_event *);
733 void (*disable)(struct perf_event *);
734 void (*assign)(struct perf_event *event, int idx);
735 void (*add)(struct perf_event *);
736 void (*del)(struct perf_event *);
737 void (*read)(struct perf_event *event);
738 int (*hw_config)(struct perf_event *event);
739 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
742 int (*addr_offset)(int index, bool eventsel);
743 int (*rdpmc_index)(int index);
744 u64 (*event_map)(int);
747 int num_counters_fixed;
751 unsigned long events_maskl;
752 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
757 struct event_constraint *
758 (*get_event_constraints)(struct cpu_hw_events *cpuc,
760 struct perf_event *event);
762 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
763 struct perf_event *event);
765 void (*start_scheduling)(struct cpu_hw_events *cpuc);
767 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
769 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
771 struct event_constraint *event_constraints;
772 struct x86_pmu_quirk *quirks;
773 int perfctr_second_write;
774 u64 (*limit_period)(struct perf_event *event, u64 l);
776 /* PMI handler bits */
777 unsigned int late_ack :1,
783 int attr_rdpmc_broken;
785 struct attribute **format_attrs;
787 ssize_t (*events_sysfs_show)(char *page, u64 config);
788 const struct attribute_group **attr_update;
790 unsigned long attr_freeze_on_smi;
795 int (*cpu_prepare)(int cpu);
796 void (*cpu_starting)(int cpu);
797 void (*cpu_dying)(int cpu);
798 void (*cpu_dead)(int cpu);
800 void (*check_microcode)(void);
801 void (*sched_task)(struct perf_event_context *ctx,
805 * Intel Arch Perfmon v2+
808 union perf_capabilities intel_cap;
811 * Intel DebugStore bits
820 pebs_no_isolation :1,
822 int pebs_record_size;
823 int pebs_buffer_size;
825 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
826 struct event_constraint *pebs_constraints;
827 void (*pebs_aliases)(struct perf_event *event);
828 unsigned long large_pebs_flags;
834 unsigned int lbr_tos, lbr_from, lbr_to,
835 lbr_info, lbr_nr; /* LBR base regs and size */
837 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
838 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
841 const int *lbr_sel_map; /* lbr_select mappings */
842 int *lbr_ctl_map; /* LBR_CTL mappings */
844 bool lbr_double_abort; /* duplicated lbr aborts */
845 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
847 unsigned int lbr_has_info:1;
848 unsigned int lbr_has_tsx:1;
849 unsigned int lbr_from_flags:1;
850 unsigned int lbr_to_cycles:1;
853 * Intel Architectural LBR CPUID Enumeration
855 unsigned int lbr_depth_mask:8;
856 unsigned int lbr_deep_c_reset:1;
857 unsigned int lbr_lip:1;
858 unsigned int lbr_cpl:1;
859 unsigned int lbr_filter:1;
860 unsigned int lbr_call_stack:1;
861 unsigned int lbr_mispred:1;
862 unsigned int lbr_timed_lbr:1;
863 unsigned int lbr_br_type:1;
865 void (*lbr_reset)(void);
866 void (*lbr_read)(struct cpu_hw_events *cpuc);
867 void (*lbr_save)(void *ctx);
868 void (*lbr_restore)(void *ctx);
871 * Intel PT/LBR/BTS are exclusive
873 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
878 int num_topdown_events;
879 u64 (*update_topdown_event)(struct perf_event *event);
880 int (*set_topdown_event_period)(struct perf_event *event);
883 * perf task context (i.e. struct perf_event_context::task_ctx_data)
884 * switch helper to bridge calls from perf/core to perf/x86.
885 * See struct pmu::swap_task_ctx() usage for examples;
887 void (*swap_task_ctx)(struct perf_event_context *prev,
888 struct perf_event_context *next);
893 unsigned int amd_nb_constraints : 1;
894 u64 perf_ctr_pair_en;
897 * Extra registers for events
899 struct extra_reg *extra_regs;
903 * Intel host/guest support (KVM)
905 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
908 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
910 int (*check_period) (struct perf_event *event, u64 period);
912 int (*aux_output_match) (struct perf_event *event);
914 int (*filter_match)(struct perf_event *event);
918 * Most PMU capabilities are the same among different hybrid PMUs.
919 * The global x86_pmu saves the architecture capabilities, which
920 * are available for all PMUs. The hybrid_pmu only includes the
921 * unique capabilities.
924 struct x86_hybrid_pmu *hybrid_pmu;
925 u8 (*get_hybrid_cpu_type) (void);
928 struct x86_perf_task_context_opt {
929 int lbr_callstack_users;
934 struct x86_perf_task_context {
938 struct x86_perf_task_context_opt opt;
939 struct lbr_entry lbr[MAX_LBR_ENTRIES];
942 struct x86_perf_task_context_arch_lbr {
943 struct x86_perf_task_context_opt opt;
944 struct lbr_entry entries[];
948 * Add padding to guarantee the 64-byte alignment of the state buffer.
950 * The structure is dynamically allocated. The size of the LBR state may vary
951 * based on the number of LBR registers.
953 * Do not put anything after the LBR state.
955 struct x86_perf_task_context_arch_lbr_xsave {
956 struct x86_perf_task_context_opt opt;
959 struct xregs_state xsave;
961 struct fxregs_state i387;
962 struct xstate_header header;
963 struct arch_lbr_state lbr;
964 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
968 #define x86_add_quirk(func_) \
970 static struct x86_pmu_quirk __quirk __initdata = { \
973 __quirk.next = x86_pmu.quirks; \
974 x86_pmu.quirks = &__quirk; \
980 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
981 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
982 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
983 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
984 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
985 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
986 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
987 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
988 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
990 #define EVENT_VAR(_id) event_attr_##_id
991 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
993 #define EVENT_ATTR(_name, _id) \
994 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
995 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
996 .id = PERF_COUNT_HW_##_id, \
1000 #define EVENT_ATTR_STR(_name, v, str) \
1001 static struct perf_pmu_events_attr event_attr_##v = { \
1002 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1007 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
1008 static struct perf_pmu_events_ht_attr event_attr_##v = { \
1009 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
1011 .event_str_noht = noht, \
1012 .event_str_ht = ht, \
1015 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \
1016 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \
1017 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\
1023 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr)
1025 #define FORMAT_ATTR_HYBRID(_name, _pmu) \
1026 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
1027 .attr = __ATTR_RO(_name), \
1031 struct pmu *x86_get_pmu(unsigned int cpu);
1032 extern struct x86_pmu x86_pmu __read_mostly;
1034 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
1036 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
1037 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
1039 return &((struct x86_perf_task_context *)ctx)->opt;
1042 static inline bool x86_pmu_has_lbr_callstack(void)
1044 return x86_pmu.lbr_sel_map &&
1045 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
1048 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
1050 int x86_perf_event_set_period(struct perf_event *event);
1053 * Generalized hw caching related hw_event table, filled
1054 * in on a per model basis. A value of 0 means
1055 * 'not supported', -1 means 'hw_event makes no sense on
1056 * this CPU', any other value means the raw hw_event
1060 #define C(x) PERF_COUNT_HW_CACHE_##x
1062 extern u64 __read_mostly hw_cache_event_ids
1063 [PERF_COUNT_HW_CACHE_MAX]
1064 [PERF_COUNT_HW_CACHE_OP_MAX]
1065 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1066 extern u64 __read_mostly hw_cache_extra_regs
1067 [PERF_COUNT_HW_CACHE_MAX]
1068 [PERF_COUNT_HW_CACHE_OP_MAX]
1069 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1071 u64 x86_perf_event_update(struct perf_event *event);
1073 static inline unsigned int x86_pmu_config_addr(int index)
1075 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
1076 x86_pmu.addr_offset(index, true) : index);
1079 static inline unsigned int x86_pmu_event_addr(int index)
1081 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
1082 x86_pmu.addr_offset(index, false) : index);
1085 static inline int x86_pmu_rdpmc_index(int index)
1087 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
1090 bool check_hw_exists(struct pmu *pmu, int num_counters,
1091 int num_counters_fixed);
1093 int x86_add_exclusive(unsigned int what);
1095 void x86_del_exclusive(unsigned int what);
1097 int x86_reserve_hardware(void);
1099 void x86_release_hardware(void);
1101 int x86_pmu_max_precise(void);
1103 void hw_perf_lbr_event_destroy(struct perf_event *event);
1105 int x86_setup_perfctr(struct perf_event *event);
1107 int x86_pmu_hw_config(struct perf_event *event);
1109 void x86_pmu_disable_all(void);
1111 static inline bool has_amd_brs(struct hw_perf_event *hwc)
1113 return hwc->flags & PERF_X86_EVENT_AMD_BRS;
1116 static inline bool is_counter_pair(struct hw_perf_event *hwc)
1118 return hwc->flags & PERF_X86_EVENT_PAIR;
1121 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
1124 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1126 if (hwc->extra_reg.reg)
1127 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
1130 * Add enabled Merge event on next counter
1131 * if large increment event being enabled on this counter
1133 if (is_counter_pair(hwc))
1134 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1136 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1139 void x86_pmu_enable_all(int added);
1141 int perf_assign_events(struct event_constraint **constraints, int n,
1142 int wmin, int wmax, int gpmax, int *assign);
1143 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1145 void x86_pmu_stop(struct perf_event *event, int flags);
1147 static inline void x86_pmu_disable_event(struct perf_event *event)
1149 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1150 struct hw_perf_event *hwc = &event->hw;
1152 wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
1154 if (is_counter_pair(hwc))
1155 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
1158 void x86_pmu_enable_event(struct perf_event *event);
1160 int x86_pmu_handle_irq(struct pt_regs *regs);
1162 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
1165 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu);
1167 extern struct event_constraint emptyconstraint;
1169 extern struct event_constraint unconstrained;
1171 static inline bool kernel_ip(unsigned long ip)
1173 #ifdef CONFIG_X86_32
1174 return ip > PAGE_OFFSET;
1176 return (long)ip < 0;
1181 * Not all PMUs provide the right context information to place the reported IP
1182 * into full context. Specifically segment registers are typically not
1185 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1186 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1189 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1190 * much we can do about that but pray and treat it like a linear address.
1192 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1194 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1195 if (regs->flags & X86_VM_MASK)
1196 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1200 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1201 ssize_t intel_event_sysfs_show(char *page, u64 config);
1203 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1205 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1207 ssize_t events_hybrid_sysfs_show(struct device *dev,
1208 struct device_attribute *attr,
1211 static inline bool fixed_counter_disabled(int i, struct pmu *pmu)
1213 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
1215 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));
1218 #ifdef CONFIG_CPU_SUP_AMD
1220 int amd_pmu_init(void);
1222 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1223 int amd_brs_init(void);
1224 void amd_brs_disable(void);
1225 void amd_brs_enable(void);
1226 void amd_brs_enable_all(void);
1227 void amd_brs_disable_all(void);
1228 void amd_brs_drain(void);
1229 void amd_brs_lopwr_init(void);
1230 void amd_brs_disable_all(void);
1231 int amd_brs_setup_filter(struct perf_event *event);
1232 void amd_brs_reset(void);
1234 static inline void amd_pmu_brs_add(struct perf_event *event)
1236 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1238 perf_sched_cb_inc(event->ctx->pmu);
1241 * No need to reset BRS because it is reset
1242 * on brs_enable() and it is saturating
1246 static inline void amd_pmu_brs_del(struct perf_event *event)
1248 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1251 WARN_ON_ONCE(cpuc->lbr_users < 0);
1253 perf_sched_cb_dec(event->ctx->pmu);
1256 void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in);
1258 static inline int amd_brs_init(void)
1262 static inline void amd_brs_disable(void) {}
1263 static inline void amd_brs_enable(void) {}
1264 static inline void amd_brs_drain(void) {}
1265 static inline void amd_brs_lopwr_init(void) {}
1266 static inline void amd_brs_disable_all(void) {}
1267 static inline int amd_brs_setup_filter(struct perf_event *event)
1271 static inline void amd_brs_reset(void) {}
1273 static inline void amd_pmu_brs_add(struct perf_event *event)
1277 static inline void amd_pmu_brs_del(struct perf_event *event)
1281 static inline void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in)
1285 static inline void amd_brs_enable_all(void)
1291 #else /* CONFIG_CPU_SUP_AMD */
1293 static inline int amd_pmu_init(void)
1298 static inline int amd_brs_init(void)
1303 static inline void amd_brs_drain(void)
1307 static inline void amd_brs_enable_all(void)
1311 static inline void amd_brs_disable_all(void)
1314 #endif /* CONFIG_CPU_SUP_AMD */
1316 static inline int is_pebs_pt(struct perf_event *event)
1318 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1321 #ifdef CONFIG_CPU_SUP_INTEL
1323 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1325 struct hw_perf_event *hwc = &event->hw;
1326 unsigned int hw_event, bts_event;
1328 if (event->attr.freq)
1331 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1332 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1334 return hw_event == bts_event && period == 1;
1337 static inline bool intel_pmu_has_bts(struct perf_event *event)
1339 struct hw_perf_event *hwc = &event->hw;
1341 return intel_pmu_has_bts_period(event, hwc->sample_period);
1344 static __always_inline void __intel_pmu_pebs_disable_all(void)
1346 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1349 static __always_inline void __intel_pmu_arch_lbr_disable(void)
1351 wrmsrl(MSR_ARCH_LBR_CTL, 0);
1354 static __always_inline void __intel_pmu_lbr_disable(void)
1358 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1359 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1360 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1363 int intel_pmu_save_and_restart(struct perf_event *event);
1365 struct event_constraint *
1366 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1367 struct perf_event *event);
1369 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1370 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1372 int intel_pmu_init(void);
1374 void init_debug_store_on_cpu(int cpu);
1376 void fini_debug_store_on_cpu(int cpu);
1378 void release_ds_buffers(void);
1380 void reserve_ds_buffers(void);
1382 void release_lbr_buffers(void);
1384 void reserve_lbr_buffers(void);
1386 extern struct event_constraint bts_constraint;
1387 extern struct event_constraint vlbr_constraint;
1389 void intel_pmu_enable_bts(u64 config);
1391 void intel_pmu_disable_bts(void);
1393 int intel_pmu_drain_bts_buffer(void);
1395 extern struct event_constraint intel_core2_pebs_event_constraints[];
1397 extern struct event_constraint intel_atom_pebs_event_constraints[];
1399 extern struct event_constraint intel_slm_pebs_event_constraints[];
1401 extern struct event_constraint intel_glm_pebs_event_constraints[];
1403 extern struct event_constraint intel_glp_pebs_event_constraints[];
1405 extern struct event_constraint intel_grt_pebs_event_constraints[];
1407 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1409 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1411 extern struct event_constraint intel_snb_pebs_event_constraints[];
1413 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1415 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1417 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1419 extern struct event_constraint intel_skl_pebs_event_constraints[];
1421 extern struct event_constraint intel_icl_pebs_event_constraints[];
1423 extern struct event_constraint intel_spr_pebs_event_constraints[];
1425 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1427 void intel_pmu_pebs_add(struct perf_event *event);
1429 void intel_pmu_pebs_del(struct perf_event *event);
1431 void intel_pmu_pebs_enable(struct perf_event *event);
1433 void intel_pmu_pebs_disable(struct perf_event *event);
1435 void intel_pmu_pebs_enable_all(void);
1437 void intel_pmu_pebs_disable_all(void);
1439 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1441 void intel_pmu_auto_reload_read(struct perf_event *event);
1443 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1445 void intel_ds_init(void);
1447 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
1448 struct perf_event_context *next);
1450 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1452 u64 lbr_from_signext_quirk_wr(u64 val);
1454 void intel_pmu_lbr_reset(void);
1456 void intel_pmu_lbr_reset_32(void);
1458 void intel_pmu_lbr_reset_64(void);
1460 void intel_pmu_lbr_add(struct perf_event *event);
1462 void intel_pmu_lbr_del(struct perf_event *event);
1464 void intel_pmu_lbr_enable_all(bool pmi);
1466 void intel_pmu_lbr_disable_all(void);
1468 void intel_pmu_lbr_read(void);
1470 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1472 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1474 void intel_pmu_lbr_save(void *ctx);
1476 void intel_pmu_lbr_restore(void *ctx);
1478 void intel_pmu_lbr_init_core(void);
1480 void intel_pmu_lbr_init_nhm(void);
1482 void intel_pmu_lbr_init_atom(void);
1484 void intel_pmu_lbr_init_slm(void);
1486 void intel_pmu_lbr_init_snb(void);
1488 void intel_pmu_lbr_init_hsw(void);
1490 void intel_pmu_lbr_init_skl(void);
1492 void intel_pmu_lbr_init_knl(void);
1494 void intel_pmu_lbr_init(void);
1496 void intel_pmu_arch_lbr_init(void);
1498 void intel_pmu_pebs_data_source_nhm(void);
1500 void intel_pmu_pebs_data_source_skl(bool pmem);
1502 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1504 void intel_pt_interrupt(void);
1506 int intel_bts_interrupt(void);
1508 void intel_bts_enable_local(void);
1510 void intel_bts_disable_local(void);
1512 int p4_pmu_init(void);
1514 int p6_pmu_init(void);
1516 int knc_pmu_init(void);
1518 static inline int is_ht_workaround_enabled(void)
1520 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1523 #else /* CONFIG_CPU_SUP_INTEL */
1525 static inline void reserve_ds_buffers(void)
1529 static inline void release_ds_buffers(void)
1533 static inline void release_lbr_buffers(void)
1537 static inline void reserve_lbr_buffers(void)
1541 static inline int intel_pmu_init(void)
1546 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1551 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1555 static inline int is_ht_workaround_enabled(void)
1559 #endif /* CONFIG_CPU_SUP_INTEL */
1561 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1562 int zhaoxin_pmu_init(void);
1564 static inline int zhaoxin_pmu_init(void)
1568 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/