1 #include <linux/perf_event.h>
2 #include <linux/nospec.h>
3 #include <asm/intel-family.h>
17 static bool test_aperfmperf(int idx)
19 return boot_cpu_has(X86_FEATURE_APERFMPERF);
22 static bool test_ptsc(int idx)
24 return boot_cpu_has(X86_FEATURE_PTSC);
27 static bool test_irperf(int idx)
29 return boot_cpu_has(X86_FEATURE_IRPERF);
32 static bool test_intel(int idx)
34 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
35 boot_cpu_data.x86 != 6)
38 switch (boot_cpu_data.x86_model) {
39 case INTEL_FAM6_NEHALEM:
40 case INTEL_FAM6_NEHALEM_G:
41 case INTEL_FAM6_NEHALEM_EP:
42 case INTEL_FAM6_NEHALEM_EX:
44 case INTEL_FAM6_WESTMERE:
45 case INTEL_FAM6_WESTMERE_EP:
46 case INTEL_FAM6_WESTMERE_EX:
48 case INTEL_FAM6_SANDYBRIDGE:
49 case INTEL_FAM6_SANDYBRIDGE_X:
51 case INTEL_FAM6_IVYBRIDGE:
52 case INTEL_FAM6_IVYBRIDGE_X:
54 case INTEL_FAM6_HASWELL_CORE:
55 case INTEL_FAM6_HASWELL_X:
56 case INTEL_FAM6_HASWELL_ULT:
57 case INTEL_FAM6_HASWELL_GT3E:
59 case INTEL_FAM6_BROADWELL_CORE:
60 case INTEL_FAM6_BROADWELL_XEON_D:
61 case INTEL_FAM6_BROADWELL_GT3E:
62 case INTEL_FAM6_BROADWELL_X:
64 case INTEL_FAM6_ATOM_SILVERMONT:
65 case INTEL_FAM6_ATOM_SILVERMONT_X:
66 case INTEL_FAM6_ATOM_AIRMONT:
67 if (idx == PERF_MSR_SMI)
71 case INTEL_FAM6_SKYLAKE_MOBILE:
72 case INTEL_FAM6_SKYLAKE_DESKTOP:
73 case INTEL_FAM6_SKYLAKE_X:
74 case INTEL_FAM6_KABYLAKE_MOBILE:
75 case INTEL_FAM6_KABYLAKE_DESKTOP:
76 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
86 struct perf_pmu_events_attr *attr;
87 bool (*test)(int idx);
90 PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00");
91 PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
92 PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
93 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
94 PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04");
95 PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05");
96 PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");
98 static struct perf_msr msr[] = {
99 [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, },
100 [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, },
101 [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, },
102 [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, },
103 [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, },
104 [PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, },
105 [PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, },
108 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
112 static struct attribute_group events_attr_group = {
114 .attrs = events_attrs,
117 PMU_FORMAT_ATTR(event, "config:0-63");
118 static struct attribute *format_attrs[] = {
119 &format_attr_event.attr,
122 static struct attribute_group format_attr_group = {
124 .attrs = format_attrs,
127 static const struct attribute_group *attr_groups[] = {
133 static int msr_event_init(struct perf_event *event)
135 u64 cfg = event->attr.config;
137 if (event->attr.type != event->pmu->type)
140 /* unsupported modes and filters */
141 if (event->attr.exclude_user ||
142 event->attr.exclude_kernel ||
143 event->attr.exclude_hv ||
144 event->attr.exclude_idle ||
145 event->attr.exclude_host ||
146 event->attr.exclude_guest ||
147 event->attr.sample_period) /* no sampling */
150 if (cfg >= PERF_MSR_EVENT_MAX)
153 cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
159 event->hw.event_base = msr[cfg].msr;
160 event->hw.config = cfg;
165 static inline u64 msr_read_counter(struct perf_event *event)
169 if (event->hw.event_base)
170 rdmsrl(event->hw.event_base, now);
176 static void msr_event_update(struct perf_event *event)
181 /* Careful, an NMI might modify the previous event value. */
183 prev = local64_read(&event->hw.prev_count);
184 now = msr_read_counter(event);
186 if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
190 if (unlikely(event->hw.event_base == MSR_SMI_COUNT))
191 delta = sign_extend64(delta, 31);
193 local64_add(delta, &event->count);
196 static void msr_event_start(struct perf_event *event, int flags)
200 now = msr_read_counter(event);
201 local64_set(&event->hw.prev_count, now);
204 static void msr_event_stop(struct perf_event *event, int flags)
206 msr_event_update(event);
209 static void msr_event_del(struct perf_event *event, int flags)
211 msr_event_stop(event, PERF_EF_UPDATE);
214 static int msr_event_add(struct perf_event *event, int flags)
216 if (flags & PERF_EF_START)
217 msr_event_start(event, flags);
222 static struct pmu pmu_msr = {
223 .task_ctx_nr = perf_sw_context,
224 .attr_groups = attr_groups,
225 .event_init = msr_event_init,
226 .add = msr_event_add,
227 .del = msr_event_del,
228 .start = msr_event_start,
229 .stop = msr_event_stop,
230 .read = msr_event_update,
231 .capabilities = PERF_PMU_CAP_NO_INTERRUPT,
234 static int __init msr_init(void)
238 if (!boot_cpu_has(X86_FEATURE_TSC)) {
239 pr_cont("no MSR PMU driver.\n");
243 /* Probe the MSRs. */
244 for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
248 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
250 if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
254 /* List remaining MSRs in the sysfs attrs. */
255 for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
257 events_attrs[j++] = &msr[i].attr->attr.attr;
259 events_attrs[j] = NULL;
261 perf_pmu_register(&pmu_msr, "msr", -1);
265 device_initcall(msr_init);