1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* Generic device ID of a discovery table device */
4 #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
5 /* Capability ID for a discovery table device */
6 #define UNCORE_EXT_CAP_ID_DISCOVERY 0x23
7 /* First DVSEC offset */
8 #define UNCORE_DISCOVERY_DVSEC_OFFSET 0x8
9 /* Mask of the supported discovery entry type */
10 #define UNCORE_DISCOVERY_DVSEC_ID_MASK 0xffff
11 /* PMON discovery entry type ID */
12 #define UNCORE_DISCOVERY_DVSEC_ID_PMON 0x1
13 /* Second DVSEC offset */
14 #define UNCORE_DISCOVERY_DVSEC2_OFFSET 0xc
15 /* Mask of the discovery table BAR offset */
16 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK 0x7
17 /* Discovery table BAR base offset */
18 #define UNCORE_DISCOVERY_BIR_BASE 0x10
19 /* Discovery table BAR step */
20 #define UNCORE_DISCOVERY_BIR_STEP 0x4
21 /* Global discovery table size */
22 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20
24 #define UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET 28
25 #define UNCORE_DISCOVERY_PCI_DOMAIN(data) \
26 ((data >> UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET) & 0x7)
27 #define UNCORE_DISCOVERY_PCI_BUS_OFFSET 20
28 #define UNCORE_DISCOVERY_PCI_BUS(data) \
29 ((data >> UNCORE_DISCOVERY_PCI_BUS_OFFSET) & 0xff)
30 #define UNCORE_DISCOVERY_PCI_DEVFN_OFFSET 12
31 #define UNCORE_DISCOVERY_PCI_DEVFN(data) \
32 ((data >> UNCORE_DISCOVERY_PCI_DEVFN_OFFSET) & 0xff)
33 #define UNCORE_DISCOVERY_PCI_BOX_CTRL(data) (data & 0xfff)
36 #define uncore_discovery_invalid_unit(unit) \
37 (!unit.table1 || !unit.ctl || \
38 unit.table1 == -1ULL || unit.ctl == -1ULL || \
41 #define GENERIC_PMON_CTL_EV_SEL_MASK 0x000000ff
42 #define GENERIC_PMON_CTL_UMASK_MASK 0x0000ff00
43 #define GENERIC_PMON_CTL_EDGE_DET (1 << 18)
44 #define GENERIC_PMON_CTL_INVERT (1 << 23)
45 #define GENERIC_PMON_CTL_TRESH_MASK 0xff000000
46 #define GENERIC_PMON_RAW_EVENT_MASK (GENERIC_PMON_CTL_EV_SEL_MASK | \
47 GENERIC_PMON_CTL_UMASK_MASK | \
48 GENERIC_PMON_CTL_EDGE_DET | \
49 GENERIC_PMON_CTL_INVERT | \
50 GENERIC_PMON_CTL_TRESH_MASK)
52 #define GENERIC_PMON_BOX_CTL_FRZ (1 << 0)
53 #define GENERIC_PMON_BOX_CTL_RST_CTRL (1 << 8)
54 #define GENERIC_PMON_BOX_CTL_RST_CTRS (1 << 9)
55 #define GENERIC_PMON_BOX_CTL_INT (GENERIC_PMON_BOX_CTL_RST_CTRL | \
56 GENERIC_PMON_BOX_CTL_RST_CTRS)
58 enum uncore_access_type {
59 UNCORE_ACCESS_MSR = 0,
66 struct uncore_global_discovery {
78 u64 ctl; /* Global Control Address */
83 u64 status_offset : 8,
90 struct uncore_unit_discovery {
104 u64 ctl; /* Unit Control Address */
116 struct intel_uncore_discovery_type {
118 enum uncore_access_type access_type;
119 u64 box_ctrl; /* Unit ctrl addr of the first box */
120 u64 *box_ctrl_die; /* Unit ctrl addr of the first box of each die */
121 u16 type; /* Type ID of the uncore block */
124 u8 ctl_offset; /* Counter Control 0 offset */
125 u8 ctr_offset; /* Counter 0 offset */
126 u16 num_boxes; /* number of boxes for the uncore block */
127 unsigned int *ids; /* Box IDs */
128 unsigned int *box_offset; /* Box offset */
131 bool intel_uncore_has_discovery_tables(int *ignore);
132 void intel_uncore_clear_discovery_tables(void);
133 void intel_uncore_generic_uncore_cpu_init(void);
134 int intel_uncore_generic_uncore_pci_init(void);
135 void intel_uncore_generic_uncore_mmio_init(void);
137 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);
138 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);
139 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);
141 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box);
142 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box);
143 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
144 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
145 struct perf_event *event);
146 void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box,
147 struct perf_event *event);
149 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
150 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
151 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
152 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
153 struct perf_event *event);
154 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
155 struct perf_event *event);
157 struct intel_uncore_type **
158 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra);