2 * Intel(R) Processor Trace PMU driver for perf
3 * Copyright (c) 2013-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
15 * Programming Reference:
16 * http://software.intel.com/en-us/intel-isa-extensions
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/types.h>
24 #include <linux/slab.h>
25 #include <linux/device.h>
27 #include <asm/perf_event.h>
30 #include <asm/intel_pt.h>
32 #include "../perf_event.h"
35 static DEFINE_PER_CPU(struct pt, pt_ctx);
37 static struct pt_pmu pt_pmu;
47 * Capabilities of Intel PT hardware, such as number of address bits or
48 * supported output schemes, are cached and exported to userspace as "caps"
49 * attribute group of pt pmu device
50 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store
51 * relevant bits together with intel_pt traces.
53 * These are necessary for both trace decoding (payloads_lip, contains address
54 * width encoded in IP-related packets), and event configuration (bitmasks with
55 * permitted values for certain bit fields).
57 #define PT_CAP(_n, _l, _r, _m) \
58 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \
59 .reg = _r, .mask = _m }
61 static struct pt_cap_desc {
67 PT_CAP(max_subleaf, 0, CR_EAX, 0xffffffff),
68 PT_CAP(cr3_filtering, 0, CR_EBX, BIT(0)),
69 PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)),
70 PT_CAP(ip_filtering, 0, CR_EBX, BIT(2)),
71 PT_CAP(mtc, 0, CR_EBX, BIT(3)),
72 PT_CAP(ptwrite, 0, CR_EBX, BIT(4)),
73 PT_CAP(power_event_trace, 0, CR_EBX, BIT(5)),
74 PT_CAP(topa_output, 0, CR_ECX, BIT(0)),
75 PT_CAP(topa_multiple_entries, 0, CR_ECX, BIT(1)),
76 PT_CAP(single_range_output, 0, CR_ECX, BIT(2)),
77 PT_CAP(payloads_lip, 0, CR_ECX, BIT(31)),
78 PT_CAP(num_address_ranges, 1, CR_EAX, 0x3),
79 PT_CAP(mtc_periods, 1, CR_EAX, 0xffff0000),
80 PT_CAP(cycle_thresholds, 1, CR_EBX, 0xffff),
81 PT_CAP(psb_periods, 1, CR_EBX, 0xffff0000),
84 static u32 pt_cap_get(enum pt_capabilities cap)
86 struct pt_cap_desc *cd = &pt_caps[cap];
87 u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
88 unsigned int shift = __ffs(cd->mask);
90 return (c & cd->mask) >> shift;
93 static ssize_t pt_cap_show(struct device *cdev,
94 struct device_attribute *attr,
97 struct dev_ext_attribute *ea =
98 container_of(attr, struct dev_ext_attribute, attr);
99 enum pt_capabilities cap = (long)ea->var;
101 return snprintf(buf, PAGE_SIZE, "%x\n", pt_cap_get(cap));
104 static struct attribute_group pt_cap_group = {
108 PMU_FORMAT_ATTR(cyc, "config:1" );
109 PMU_FORMAT_ATTR(pwr_evt, "config:4" );
110 PMU_FORMAT_ATTR(fup_on_ptw, "config:5" );
111 PMU_FORMAT_ATTR(mtc, "config:9" );
112 PMU_FORMAT_ATTR(tsc, "config:10" );
113 PMU_FORMAT_ATTR(noretcomp, "config:11" );
114 PMU_FORMAT_ATTR(ptw, "config:12" );
115 PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
116 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
117 PMU_FORMAT_ATTR(psb_period, "config:24-27" );
119 static struct attribute *pt_formats_attr[] = {
120 &format_attr_cyc.attr,
121 &format_attr_pwr_evt.attr,
122 &format_attr_fup_on_ptw.attr,
123 &format_attr_mtc.attr,
124 &format_attr_tsc.attr,
125 &format_attr_noretcomp.attr,
126 &format_attr_ptw.attr,
127 &format_attr_mtc_period.attr,
128 &format_attr_cyc_thresh.attr,
129 &format_attr_psb_period.attr,
133 static struct attribute_group pt_format_group = {
135 .attrs = pt_formats_attr,
139 pt_timing_attr_show(struct device *dev, struct device_attribute *attr,
142 struct perf_pmu_events_attr *pmu_attr =
143 container_of(attr, struct perf_pmu_events_attr, attr);
145 switch (pmu_attr->id) {
147 return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio);
149 return sprintf(page, "%u:%u\n",
159 PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0,
160 pt_timing_attr_show);
161 PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1,
162 pt_timing_attr_show);
164 static struct attribute *pt_timing_attr[] = {
165 &timing_attr_max_nonturbo_ratio.attr.attr,
166 &timing_attr_tsc_art_ratio.attr.attr,
170 static struct attribute_group pt_timing_group = {
171 .attrs = pt_timing_attr,
174 static const struct attribute_group *pt_attr_groups[] = {
181 static int __init pt_pmu_hw_init(void)
183 struct dev_ext_attribute *de_attrs;
184 struct attribute **attrs;
190 rdmsrl(MSR_PLATFORM_INFO, reg);
191 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
194 * if available, read in TSC to core crystal clock ratio,
195 * otherwise, zero for numerator stands for "not enumerated"
198 if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {
199 u32 eax, ebx, ecx, edx;
201 cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);
203 pt_pmu.tsc_art_num = ebx;
204 pt_pmu.tsc_art_den = eax;
207 if (boot_cpu_has(X86_FEATURE_VMX)) {
209 * Intel SDM, 36.5 "Tracing post-VMXON" says that
210 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
213 rdmsrl(MSR_IA32_VMX_MISC, reg);
220 for (i = 0; i < PT_CPUID_LEAVES; i++) {
222 &pt_pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM],
223 &pt_pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM],
224 &pt_pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM],
225 &pt_pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]);
229 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1);
230 attrs = kzalloc(size, GFP_KERNEL);
234 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1);
235 de_attrs = kzalloc(size, GFP_KERNEL);
239 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) {
240 struct dev_ext_attribute *de_attr = de_attrs + i;
242 de_attr->attr.attr.name = pt_caps[i].name;
244 sysfs_attr_init(&de_attr->attr.attr);
246 de_attr->attr.attr.mode = S_IRUGO;
247 de_attr->attr.show = pt_cap_show;
248 de_attr->var = (void *)i;
250 attrs[i] = &de_attr->attr.attr;
253 pt_cap_group.attrs = attrs;
263 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \
264 RTIT_CTL_CYC_THRESH | \
267 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
270 #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \
273 #define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \
277 RTIT_CTL_PWR_EVT_EN | \
278 RTIT_CTL_FUP_ON_PTW | \
281 static bool pt_event_valid(struct perf_event *event)
283 u64 config = event->attr.config;
284 u64 allowed, requested;
286 if ((config & PT_CONFIG_MASK) != config)
289 if (config & RTIT_CTL_CYC_PSB) {
290 if (!pt_cap_get(PT_CAP_psb_cyc))
293 allowed = pt_cap_get(PT_CAP_psb_periods);
294 requested = (config & RTIT_CTL_PSB_FREQ) >>
295 RTIT_CTL_PSB_FREQ_OFFSET;
296 if (requested && (!(allowed & BIT(requested))))
299 allowed = pt_cap_get(PT_CAP_cycle_thresholds);
300 requested = (config & RTIT_CTL_CYC_THRESH) >>
301 RTIT_CTL_CYC_THRESH_OFFSET;
302 if (requested && (!(allowed & BIT(requested))))
306 if (config & RTIT_CTL_MTC) {
308 * In the unlikely case that CPUID lists valid mtc periods,
309 * but not the mtc capability, drop out here.
311 * Spec says that setting mtc period bits while mtc bit in
312 * CPUID is 0 will #GP, so better safe than sorry.
314 if (!pt_cap_get(PT_CAP_mtc))
317 allowed = pt_cap_get(PT_CAP_mtc_periods);
321 requested = (config & RTIT_CTL_MTC_RANGE) >>
322 RTIT_CTL_MTC_RANGE_OFFSET;
324 if (!(allowed & BIT(requested)))
328 if (config & RTIT_CTL_PWR_EVT_EN &&
329 !pt_cap_get(PT_CAP_power_event_trace))
332 if (config & RTIT_CTL_PTW) {
333 if (!pt_cap_get(PT_CAP_ptwrite))
336 /* FUPonPTW without PTW doesn't make sense */
337 if ((config & RTIT_CTL_FUP_ON_PTW) &&
338 !(config & RTIT_CTL_PTW_EN))
346 * PT configuration helpers
347 * These all are cpu affine and operate on a local PT
350 /* Address ranges and their corresponding msr configuration registers */
351 static const struct pt_address_range {
354 unsigned int reg_off;
355 } pt_address_ranges[] = {
357 .msr_a = MSR_IA32_RTIT_ADDR0_A,
358 .msr_b = MSR_IA32_RTIT_ADDR0_B,
359 .reg_off = RTIT_CTL_ADDR0_OFFSET,
362 .msr_a = MSR_IA32_RTIT_ADDR1_A,
363 .msr_b = MSR_IA32_RTIT_ADDR1_B,
364 .reg_off = RTIT_CTL_ADDR1_OFFSET,
367 .msr_a = MSR_IA32_RTIT_ADDR2_A,
368 .msr_b = MSR_IA32_RTIT_ADDR2_B,
369 .reg_off = RTIT_CTL_ADDR2_OFFSET,
372 .msr_a = MSR_IA32_RTIT_ADDR3_A,
373 .msr_b = MSR_IA32_RTIT_ADDR3_B,
374 .reg_off = RTIT_CTL_ADDR3_OFFSET,
378 static u64 pt_config_filters(struct perf_event *event)
380 struct pt_filters *filters = event->hw.addr_filters;
381 struct pt *pt = this_cpu_ptr(&pt_ctx);
382 unsigned int range = 0;
388 perf_event_addr_filters_sync(event);
390 for (range = 0; range < filters->nr_filters; range++) {
391 struct pt_filter *filter = &filters->filter[range];
394 * Note, if the range has zero start/end addresses due
395 * to its dynamic object not being loaded yet, we just
396 * go ahead and program zeroed range, which will simply
397 * produce no data. Note^2: if executable code at 0x0
398 * is a concern, we can set up an "invalid" configuration
399 * such as msr_b < msr_a.
402 /* avoid redundant msr writes */
403 if (pt->filters.filter[range].msr_a != filter->msr_a) {
404 wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a);
405 pt->filters.filter[range].msr_a = filter->msr_a;
408 if (pt->filters.filter[range].msr_b != filter->msr_b) {
409 wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b);
410 pt->filters.filter[range].msr_b = filter->msr_b;
413 rtit_ctl |= (u64)filter->config << pt_address_ranges[range].reg_off;
419 static void pt_config(struct perf_event *event)
423 if (!event->hw.itrace_started) {
424 event->hw.itrace_started = 1;
425 wrmsrl(MSR_IA32_RTIT_STATUS, 0);
428 reg = pt_config_filters(event);
429 reg |= RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN | RTIT_CTL_TRACEEN;
431 if (!event->attr.exclude_kernel)
433 if (!event->attr.exclude_user)
436 reg |= (event->attr.config & PT_CONFIG_MASK);
438 event->hw.config = reg;
439 wrmsrl(MSR_IA32_RTIT_CTL, reg);
442 static void pt_config_stop(struct perf_event *event)
444 u64 ctl = READ_ONCE(event->hw.config);
446 /* may be already stopped by a PMI */
447 if (!(ctl & RTIT_CTL_TRACEEN))
450 ctl &= ~RTIT_CTL_TRACEEN;
451 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
453 WRITE_ONCE(event->hw.config, ctl);
456 * A wrmsr that disables trace generation serializes other PT
457 * registers and causes all data packets to be written to memory,
458 * but a fence is required for the data to become globally visible.
460 * The below WMB, separating data store and aux_head store matches
461 * the consumer's RMB that separates aux_head load and data load.
466 static void pt_config_buffer(void *buf, unsigned int topa_idx,
467 unsigned int output_off)
471 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf));
473 reg = 0x7f | ((u64)topa_idx << 7) | ((u64)output_off << 32);
475 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg);
479 * Keep ToPA table-related metadata on the same page as the actual table,
480 * taking up a few words from the top
483 #define TENTS_PER_PAGE (((PAGE_SIZE - 40) / sizeof(struct topa_entry)) - 1)
486 * struct topa - page-sized ToPA table with metadata at the top
487 * @table: actual ToPA table entries, as understood by PT hardware
488 * @list: linkage to struct pt_buffer's list of tables
489 * @phys: physical address of this page
490 * @offset: offset of the first entry in this table in the buffer
491 * @size: total size of all entries in this table
492 * @last: index of the last initialized entry in this table
495 struct topa_entry table[TENTS_PER_PAGE];
496 struct list_head list;
503 /* make -1 stand for the last table entry */
504 #define TOPA_ENTRY(t, i) ((i) == -1 ? &(t)->table[(t)->last] : &(t)->table[(i)])
507 * topa_alloc() - allocate page-sized ToPA table
508 * @cpu: CPU on which to allocate.
509 * @gfp: Allocation flags.
511 * Return: On success, return the pointer to ToPA table page.
513 static struct topa *topa_alloc(int cpu, gfp_t gfp)
515 int node = cpu_to_node(cpu);
519 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0);
523 topa = page_address(p);
525 topa->phys = page_to_phys(p);
528 * In case of singe-entry ToPA, always put the self-referencing END
529 * link as the 2nd entry in the table
531 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) {
532 TOPA_ENTRY(topa, 1)->base = topa->phys >> TOPA_SHIFT;
533 TOPA_ENTRY(topa, 1)->end = 1;
540 * topa_free() - free a page-sized ToPA table
541 * @topa: Table to deallocate.
543 static void topa_free(struct topa *topa)
545 free_page((unsigned long)topa);
549 * topa_insert_table() - insert a ToPA table into a buffer
550 * @buf: PT buffer that's being extended.
551 * @topa: New topa table to be inserted.
553 * If it's the first table in this buffer, set up buffer's pointers
554 * accordingly; otherwise, add a END=1 link entry to @topa to the current
555 * "last" table and adjust the last table pointer to @topa.
557 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa)
559 struct topa *last = buf->last;
561 list_add_tail(&topa->list, &buf->tables);
564 buf->first = buf->last = buf->cur = topa;
568 topa->offset = last->offset + last->size;
571 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
574 BUG_ON(last->last != TENTS_PER_PAGE - 1);
576 TOPA_ENTRY(last, -1)->base = topa->phys >> TOPA_SHIFT;
577 TOPA_ENTRY(last, -1)->end = 1;
581 * topa_table_full() - check if a ToPA table is filled up
584 static bool topa_table_full(struct topa *topa)
586 /* single-entry ToPA is a special case */
587 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
590 return topa->last == TENTS_PER_PAGE - 1;
594 * topa_insert_pages() - create a list of ToPA tables
595 * @buf: PT buffer being initialized.
596 * @gfp: Allocation flags.
598 * This initializes a list of ToPA tables with entries from
599 * the data_pages provided by rb_alloc_aux().
601 * Return: 0 on success or error code.
603 static int topa_insert_pages(struct pt_buffer *buf, gfp_t gfp)
605 struct topa *topa = buf->last;
609 p = virt_to_page(buf->data_pages[buf->nr_pages]);
611 order = page_private(p);
613 if (topa_table_full(topa)) {
614 topa = topa_alloc(buf->cpu, gfp);
618 topa_insert_table(buf, topa);
621 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT;
622 TOPA_ENTRY(topa, -1)->size = order;
623 if (!buf->snapshot && !pt_cap_get(PT_CAP_topa_multiple_entries)) {
624 TOPA_ENTRY(topa, -1)->intr = 1;
625 TOPA_ENTRY(topa, -1)->stop = 1;
629 topa->size += sizes(order);
631 buf->nr_pages += 1ul << order;
637 * pt_topa_dump() - print ToPA tables and their entries
640 static void pt_topa_dump(struct pt_buffer *buf)
644 list_for_each_entry(topa, &buf->tables, list) {
647 pr_debug("# table @%p (%016Lx), off %llx size %zx\n", topa->table,
648 topa->phys, topa->offset, topa->size);
649 for (i = 0; i < TENTS_PER_PAGE; i++) {
650 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n",
652 (unsigned long)topa->table[i].base << TOPA_SHIFT,
653 sizes(topa->table[i].size),
654 topa->table[i].end ? 'E' : ' ',
655 topa->table[i].intr ? 'I' : ' ',
656 topa->table[i].stop ? 'S' : ' ',
657 *(u64 *)&topa->table[i]);
658 if ((pt_cap_get(PT_CAP_topa_multiple_entries) &&
659 topa->table[i].stop) ||
667 * pt_buffer_advance() - advance to the next output region
670 * Advance the current pointers in the buffer to the next ToPA entry.
672 static void pt_buffer_advance(struct pt_buffer *buf)
677 if (buf->cur_idx == buf->cur->last) {
678 if (buf->cur == buf->last)
679 buf->cur = buf->first;
681 buf->cur = list_entry(buf->cur->list.next, struct topa,
688 * pt_update_head() - calculate current offsets and sizes
689 * @pt: Per-cpu pt context.
691 * Update buffer's current write pointer position and data size.
693 static void pt_update_head(struct pt *pt)
695 struct pt_buffer *buf = perf_get_aux(&pt->handle);
696 u64 topa_idx, base, old;
698 /* offset of the first region in this table from the beginning of buf */
699 base = buf->cur->offset + buf->output_off;
701 /* offset of the current output region within this table */
702 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++)
703 base += sizes(buf->cur->table[topa_idx].size);
706 local_set(&buf->data_size, base);
708 old = (local64_xchg(&buf->head, base) &
709 ((buf->nr_pages << PAGE_SHIFT) - 1));
711 base += buf->nr_pages << PAGE_SHIFT;
713 local_add(base - old, &buf->data_size);
718 * pt_buffer_region() - obtain current output region's address
721 static void *pt_buffer_region(struct pt_buffer *buf)
723 return phys_to_virt(buf->cur->table[buf->cur_idx].base << TOPA_SHIFT);
727 * pt_buffer_region_size() - obtain current output region's size
730 static size_t pt_buffer_region_size(struct pt_buffer *buf)
732 return sizes(buf->cur->table[buf->cur_idx].size);
736 * pt_handle_status() - take care of possible status conditions
737 * @pt: Per-cpu pt context.
739 static void pt_handle_status(struct pt *pt)
741 struct pt_buffer *buf = perf_get_aux(&pt->handle);
745 rdmsrl(MSR_IA32_RTIT_STATUS, status);
747 if (status & RTIT_STATUS_ERROR) {
748 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
750 status &= ~RTIT_STATUS_ERROR;
753 if (status & RTIT_STATUS_STOPPED) {
754 status &= ~RTIT_STATUS_STOPPED;
757 * On systems that only do single-entry ToPA, hitting STOP
758 * means we are already losing data; need to let the decoder
761 if (!pt_cap_get(PT_CAP_topa_multiple_entries) ||
762 buf->output_off == sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size)) {
763 local_inc(&buf->lost);
769 * Also on single-entry ToPA implementations, interrupt will come
770 * before the output reaches its output region's boundary.
772 if (!pt_cap_get(PT_CAP_topa_multiple_entries) && !buf->snapshot &&
773 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) {
774 void *head = pt_buffer_region(buf);
776 /* everything within this margin needs to be zeroed out */
777 memset(head + buf->output_off, 0,
778 pt_buffer_region_size(buf) -
784 pt_buffer_advance(buf);
786 wrmsrl(MSR_IA32_RTIT_STATUS, status);
790 * pt_read_offset() - translate registers into buffer pointers
793 * Set buffer's output pointers from MSR values.
795 static void pt_read_offset(struct pt_buffer *buf)
797 u64 offset, base_topa;
799 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, base_topa);
800 buf->cur = phys_to_virt(base_topa);
802 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, offset);
803 /* offset within current output region */
804 buf->output_off = offset >> 32;
805 /* index of current output region within this table */
806 buf->cur_idx = (offset & 0xffffff80) >> 7;
810 * pt_topa_next_entry() - obtain index of the first page in the next ToPA entry
812 * @pg: Page offset in the buffer.
814 * When advancing to the next output region (ToPA entry), given a page offset
815 * into the buffer, we need to find the offset of the first page in the next
818 static unsigned int pt_topa_next_entry(struct pt_buffer *buf, unsigned int pg)
820 struct topa_entry *te = buf->topa_index[pg];
823 if (buf->first == buf->last && buf->first->last == 1)
828 pg &= buf->nr_pages - 1;
829 } while (buf->topa_index[pg] == te);
835 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer
837 * @handle: Current output handle.
839 * Place INT and STOP marks to prevent overwriting old data that the consumer
840 * hasn't yet collected and waking up the consumer after a certain fraction of
841 * the buffer has filled up. Only needed and sensible for non-snapshot counters.
843 * This obviously relies on buf::head to figure out buffer markers, so it has
844 * to be called after pt_buffer_reset_offsets() and before the hardware tracing
847 static int pt_buffer_reset_markers(struct pt_buffer *buf,
848 struct perf_output_handle *handle)
851 unsigned long head = local64_read(&buf->head);
852 unsigned long idx, npages, wakeup;
854 /* can't stop in the middle of an output region */
855 if (buf->output_off + handle->size + 1 <
856 sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size))
860 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */
861 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
864 /* clear STOP and INT from current entry */
865 buf->topa_index[buf->stop_pos]->stop = 0;
866 buf->topa_index[buf->stop_pos]->intr = 0;
867 buf->topa_index[buf->intr_pos]->intr = 0;
869 /* how many pages till the STOP marker */
870 npages = handle->size >> PAGE_SHIFT;
872 /* if it's on a page boundary, fill up one more page */
873 if (!offset_in_page(head + handle->size + 1))
876 idx = (head >> PAGE_SHIFT) + npages;
877 idx &= buf->nr_pages - 1;
880 wakeup = handle->wakeup >> PAGE_SHIFT;
882 /* in the worst case, wake up the consumer one page before hard stop */
883 idx = (head >> PAGE_SHIFT) + npages - 1;
887 idx &= buf->nr_pages - 1;
890 buf->topa_index[buf->stop_pos]->stop = 1;
891 buf->topa_index[buf->stop_pos]->intr = 1;
892 buf->topa_index[buf->intr_pos]->intr = 1;
898 * pt_buffer_setup_topa_index() - build topa_index[] table of regions
901 * topa_index[] references output regions indexed by offset into the
902 * buffer for purposes of quick reverse lookup.
904 static void pt_buffer_setup_topa_index(struct pt_buffer *buf)
906 struct topa *cur = buf->first, *prev = buf->last;
907 struct topa_entry *te_cur = TOPA_ENTRY(cur, 0),
908 *te_prev = TOPA_ENTRY(prev, prev->last - 1);
911 while (pg < buf->nr_pages) {
914 /* pages within one topa entry */
915 for (tidx = 0; tidx < 1 << te_cur->size; tidx++, pg++)
916 buf->topa_index[pg] = te_prev;
920 if (idx == cur->last - 1) {
921 /* advance to next topa table */
923 cur = list_entry(cur->list.next, struct topa, list);
927 te_cur = TOPA_ENTRY(cur, idx);
933 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head
935 * @head: Write pointer (aux_head) from AUX buffer.
937 * Find the ToPA table and entry corresponding to given @head and set buffer's
938 * "current" pointers accordingly. This is done after we have obtained the
939 * current aux_head position from a successful call to perf_aux_output_begin()
940 * to make sure the hardware is writing to the right place.
942 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed
943 * into PT msrs when the tracing is enabled and buf::head and buf::data_size,
944 * which are used to determine INT and STOP markers' locations by a subsequent
945 * call to pt_buffer_reset_markers().
947 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head)
952 head &= (buf->nr_pages << PAGE_SHIFT) - 1;
954 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1);
955 pg = pt_topa_next_entry(buf, pg);
957 buf->cur = (struct topa *)((unsigned long)buf->topa_index[pg] & PAGE_MASK);
958 buf->cur_idx = ((unsigned long)buf->topa_index[pg] -
959 (unsigned long)buf->cur) / sizeof(struct topa_entry);
960 buf->output_off = head & (sizes(buf->cur->table[buf->cur_idx].size) - 1);
962 local64_set(&buf->head, head);
963 local_set(&buf->data_size, 0);
967 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer
970 static void pt_buffer_fini_topa(struct pt_buffer *buf)
972 struct topa *topa, *iter;
974 list_for_each_entry_safe(topa, iter, &buf->tables, list) {
976 * right now, this is in free_aux() path only, so
977 * no need to unlink this table from the list
984 * pt_buffer_init_topa() - initialize ToPA table for pt buffer
986 * @size: Total size of all regions within this ToPA.
987 * @gfp: Allocation flags.
989 static int pt_buffer_init_topa(struct pt_buffer *buf, unsigned long nr_pages,
995 topa = topa_alloc(buf->cpu, gfp);
999 topa_insert_table(buf, topa);
1001 while (buf->nr_pages < nr_pages) {
1002 err = topa_insert_pages(buf, gfp);
1004 pt_buffer_fini_topa(buf);
1009 pt_buffer_setup_topa_index(buf);
1011 /* link last table to the first one, unless we're double buffering */
1012 if (pt_cap_get(PT_CAP_topa_multiple_entries)) {
1013 TOPA_ENTRY(buf->last, -1)->base = buf->first->phys >> TOPA_SHIFT;
1014 TOPA_ENTRY(buf->last, -1)->end = 1;
1022 * pt_buffer_setup_aux() - set up topa tables for a PT buffer
1023 * @cpu: Cpu on which to allocate, -1 means current.
1024 * @pages: Array of pointers to buffer pages passed from perf core.
1025 * @nr_pages: Number of pages in the buffer.
1026 * @snapshot: If this is a snapshot/overwrite counter.
1028 * This is a pmu::setup_aux callback that sets up ToPA tables and all the
1029 * bookkeeping for an AUX buffer.
1031 * Return: Our private PT buffer structure.
1034 pt_buffer_setup_aux(int cpu, void **pages, int nr_pages, bool snapshot)
1036 struct pt_buffer *buf;
1043 cpu = raw_smp_processor_id();
1044 node = cpu_to_node(cpu);
1046 buf = kzalloc_node(offsetof(struct pt_buffer, topa_index[nr_pages]),
1052 buf->snapshot = snapshot;
1053 buf->data_pages = pages;
1055 INIT_LIST_HEAD(&buf->tables);
1057 ret = pt_buffer_init_topa(buf, nr_pages, GFP_KERNEL);
1067 * pt_buffer_free_aux() - perf AUX deallocation path callback
1070 static void pt_buffer_free_aux(void *data)
1072 struct pt_buffer *buf = data;
1074 pt_buffer_fini_topa(buf);
1078 static int pt_addr_filters_init(struct perf_event *event)
1080 struct pt_filters *filters;
1081 int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu);
1083 if (!pt_cap_get(PT_CAP_num_address_ranges))
1086 filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node);
1091 memcpy(filters, event->parent->hw.addr_filters,
1094 event->hw.addr_filters = filters;
1099 static void pt_addr_filters_fini(struct perf_event *event)
1101 kfree(event->hw.addr_filters);
1102 event->hw.addr_filters = NULL;
1105 static inline bool valid_kernel_ip(unsigned long ip)
1107 return virt_addr_valid(ip) && kernel_ip(ip);
1110 static int pt_event_addr_filters_validate(struct list_head *filters)
1112 struct perf_addr_filter *filter;
1115 list_for_each_entry(filter, filters, entry) {
1116 /* PT doesn't support single address triggers */
1117 if (!filter->range || !filter->size)
1120 if (!filter->path.dentry) {
1121 if (!valid_kernel_ip(filter->offset))
1124 if (!valid_kernel_ip(filter->offset + filter->size))
1128 if (++range > pt_cap_get(PT_CAP_num_address_ranges))
1135 static void pt_event_addr_filters_sync(struct perf_event *event)
1137 struct perf_addr_filters_head *head = perf_event_addr_filters(event);
1138 unsigned long msr_a, msr_b, *offs = event->addr_filters_offs;
1139 struct pt_filters *filters = event->hw.addr_filters;
1140 struct perf_addr_filter *filter;
1146 list_for_each_entry(filter, &head->list, entry) {
1147 if (filter->path.dentry && !offs[range]) {
1150 /* apply the offset */
1151 msr_a = filter->offset + offs[range];
1152 msr_b = filter->size + msr_a - 1;
1155 filters->filter[range].msr_a = msr_a;
1156 filters->filter[range].msr_b = msr_b;
1157 filters->filter[range].config = filter->filter ? 1 : 2;
1161 filters->nr_filters = range;
1165 * intel_pt_interrupt() - PT PMI handler
1167 void intel_pt_interrupt(void)
1169 struct pt *pt = this_cpu_ptr(&pt_ctx);
1170 struct pt_buffer *buf;
1171 struct perf_event *event = pt->handle.event;
1174 * There may be a dangling PT bit in the interrupt status register
1175 * after PT has been disabled by pt_event_stop(). Make sure we don't
1176 * do anything (particularly, re-enable) for this event here.
1178 if (!READ_ONCE(pt->handle_nmi))
1182 * If VMX is on and PT does not support it, don't touch anything.
1184 if (READ_ONCE(pt->vmx_on))
1190 pt_config_stop(event);
1192 buf = perf_get_aux(&pt->handle);
1196 pt_read_offset(buf);
1198 pt_handle_status(pt);
1202 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0),
1203 local_xchg(&buf->lost, 0));
1205 if (!event->hw.state) {
1208 buf = perf_aux_output_begin(&pt->handle, event);
1210 event->hw.state = PERF_HES_STOPPED;
1214 pt_buffer_reset_offsets(buf, pt->handle.head);
1215 /* snapshot counters don't use PMI, so it's safe */
1216 ret = pt_buffer_reset_markers(buf, &pt->handle);
1218 perf_aux_output_end(&pt->handle, 0, true);
1222 pt_config_buffer(buf->cur->table, buf->cur_idx,
1228 void intel_pt_handle_vmx(int on)
1230 struct pt *pt = this_cpu_ptr(&pt_ctx);
1231 struct perf_event *event;
1232 unsigned long flags;
1234 /* PT plays nice with VMX, do nothing */
1239 * VMXON will clear RTIT_CTL.TraceEn; we need to make
1240 * sure to not try to set it while VMX is on. Disable
1241 * interrupts to avoid racing with pmu callbacks;
1242 * concurrent PMI should be handled fine.
1244 local_irq_save(flags);
1245 WRITE_ONCE(pt->vmx_on, on);
1248 /* prevent pt_config_stop() from writing RTIT_CTL */
1249 event = pt->handle.event;
1251 event->hw.config = 0;
1253 local_irq_restore(flags);
1255 EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
1261 static void pt_event_start(struct perf_event *event, int mode)
1263 struct hw_perf_event *hwc = &event->hw;
1264 struct pt *pt = this_cpu_ptr(&pt_ctx);
1265 struct pt_buffer *buf;
1267 if (READ_ONCE(pt->vmx_on))
1270 buf = perf_aux_output_begin(&pt->handle, event);
1274 pt_buffer_reset_offsets(buf, pt->handle.head);
1275 if (!buf->snapshot) {
1276 if (pt_buffer_reset_markers(buf, &pt->handle))
1280 WRITE_ONCE(pt->handle_nmi, 1);
1283 pt_config_buffer(buf->cur->table, buf->cur_idx,
1290 perf_aux_output_end(&pt->handle, 0, true);
1292 hwc->state = PERF_HES_STOPPED;
1295 static void pt_event_stop(struct perf_event *event, int mode)
1297 struct pt *pt = this_cpu_ptr(&pt_ctx);
1300 * Protect against the PMI racing with disabling wrmsr,
1301 * see comment in intel_pt_interrupt().
1303 WRITE_ONCE(pt->handle_nmi, 0);
1305 pt_config_stop(event);
1307 if (event->hw.state == PERF_HES_STOPPED)
1310 event->hw.state = PERF_HES_STOPPED;
1312 if (mode & PERF_EF_UPDATE) {
1313 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1318 if (WARN_ON_ONCE(pt->handle.event != event))
1321 pt_read_offset(buf);
1323 pt_handle_status(pt);
1329 local_xchg(&buf->data_size,
1330 buf->nr_pages << PAGE_SHIFT);
1331 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0),
1332 local_xchg(&buf->lost, 0));
1336 static void pt_event_del(struct perf_event *event, int mode)
1338 pt_event_stop(event, PERF_EF_UPDATE);
1341 static int pt_event_add(struct perf_event *event, int mode)
1343 struct pt *pt = this_cpu_ptr(&pt_ctx);
1344 struct hw_perf_event *hwc = &event->hw;
1347 if (pt->handle.event)
1350 if (mode & PERF_EF_START) {
1351 pt_event_start(event, 0);
1353 if (hwc->state == PERF_HES_STOPPED)
1356 hwc->state = PERF_HES_STOPPED;
1365 static void pt_event_read(struct perf_event *event)
1369 static void pt_event_destroy(struct perf_event *event)
1371 pt_addr_filters_fini(event);
1372 x86_del_exclusive(x86_lbr_exclusive_pt);
1375 static int pt_event_init(struct perf_event *event)
1377 if (event->attr.type != pt_pmu.pmu.type)
1380 if (!pt_event_valid(event))
1383 if (x86_add_exclusive(x86_lbr_exclusive_pt))
1386 if (pt_addr_filters_init(event)) {
1387 x86_del_exclusive(x86_lbr_exclusive_pt);
1391 event->destroy = pt_event_destroy;
1396 void cpu_emergency_stop_pt(void)
1398 struct pt *pt = this_cpu_ptr(&pt_ctx);
1400 if (pt->handle.event)
1401 pt_event_stop(pt->handle.event, PERF_EF_UPDATE);
1404 static __init int pt_init(void)
1406 int ret, cpu, prior_warn = 0;
1408 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE);
1410 if (!boot_cpu_has(X86_FEATURE_INTEL_PT))
1414 for_each_online_cpu(cpu) {
1417 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
1418 if (!ret && (ctl & RTIT_CTL_TRACEEN))
1424 x86_add_exclusive(x86_lbr_exclusive_pt);
1425 pr_warn("PT is enabled at boot time, doing nothing\n");
1430 ret = pt_pmu_hw_init();
1434 if (!pt_cap_get(PT_CAP_topa_output)) {
1435 pr_warn("ToPA output is not supported on this CPU\n");
1439 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
1440 pt_pmu.pmu.capabilities =
1441 PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF;
1443 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
1444 pt_pmu.pmu.attr_groups = pt_attr_groups;
1445 pt_pmu.pmu.task_ctx_nr = perf_sw_context;
1446 pt_pmu.pmu.event_init = pt_event_init;
1447 pt_pmu.pmu.add = pt_event_add;
1448 pt_pmu.pmu.del = pt_event_del;
1449 pt_pmu.pmu.start = pt_event_start;
1450 pt_pmu.pmu.stop = pt_event_stop;
1451 pt_pmu.pmu.read = pt_event_read;
1452 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux;
1453 pt_pmu.pmu.free_aux = pt_buffer_free_aux;
1454 pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync;
1455 pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate;
1456 pt_pmu.pmu.nr_addr_filters =
1457 pt_cap_get(PT_CAP_num_address_ranges);
1459 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1);
1463 arch_initcall(pt_init);