arch/x86/events/intel/ds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/bitops.h>
   3 #include <linux/types.h>
   4 #include <linux/slab.h>
   5
   6 #include <asm/cpu_entry_area.h>
   7 #include <asm/perf_event.h>
   8 #include <asm/tlbflush.h>
   9 #include <asm/insn.h>
  10
  11 #include "../perf_event.h"
  12
  13 /* Waste a full page so it can be mapped into the cpu_entry_area */
  14 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
  15
  16 /* The size of a BTS record in bytes: */
  17 #define BTS_RECORD_SIZE         24
  18
  19 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  20
  21 /*
  22  * pebs_record_32 for p4 and core not supported
  23
  24 struct pebs_record_32 {
  25         u32 flags, ip;
  26         u32 ax, bc, cx, dx;
  27         u32 si, di, bp, sp;
  28 };
  29
  30  */
  31
  32 union intel_x86_pebs_dse {
  33         u64 val;
  34         struct {
  35                 unsigned int ld_dse:4;
  36                 unsigned int ld_stlb_miss:1;
  37                 unsigned int ld_locked:1;
  38                 unsigned int ld_reserved:26;
  39         };
  40         struct {
  41                 unsigned int st_l1d_hit:1;
  42                 unsigned int st_reserved1:3;
  43                 unsigned int st_stlb_miss:1;
  44                 unsigned int st_locked:1;
  45                 unsigned int st_reserved2:26;
  46         };
  47 };
  48
  49
  50 /*
  51  * Map PEBS Load Latency Data Source encodings to generic
  52  * memory data source information
  53  */
  54 #define P(a, b) PERF_MEM_S(a, b)
  55 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  56 #define LEVEL(x) P(LVLNUM, x)
  57 #define REM P(REMOTE, REMOTE)
  58 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  59
  60 /* Version for Sandy Bridge and later */
  61 static u64 pebs_data_source[] = {
  62         P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  63         OP_LH | P(LVL, L1)  | LEVEL(L1) | P(SNOOP, NONE),  /* 0x01: L1 local */
  64         OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
  65         OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),  /* 0x03: L2 hit */
  66         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, NONE),  /* 0x04: L3 hit */
  67         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, MISS),  /* 0x05: L3 hit, snoop miss */
  68         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HIT),   /* 0x06: L3 hit, snoop hit */
  69         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HITM),  /* 0x07: L3 hit, snoop hitm */
  70         OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  71         OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  72         OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, HIT),       /* 0x0a: L3 miss, shared */
  73         OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  74         OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | SNOOP_NONE_MISS,     /* 0x0c: L3 miss, excl */
  75         OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
  76         OP_LH | P(LVL, IO)  | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
  77         OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
  78 };
  79
  80 /* Patch up minor differences in the bits */
  81 void __init intel_pmu_pebs_data_source_nhm(void)
  82 {
  83         pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
  84         pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  85         pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  86 }
  87
  88 void __init intel_pmu_pebs_data_source_skl(bool pmem)
  89 {
  90         u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
  91
  92         pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
  93         pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
  94         pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
  95         pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
  96         pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
  97 }
  98
  99 static u64 precise_store_data(u64 status)
 100 {
 101         union intel_x86_pebs_dse dse;
 102         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
 103
 104         dse.val = status;
 105
 106         /*
 107          * bit 4: TLB access
 108          * 1 = stored missed 2nd level TLB
 109          *
 110          * so it either hit the walker or the OS
 111          * otherwise hit 2nd level TLB
 112          */
 113         if (dse.st_stlb_miss)
 114                 val |= P(TLB, MISS);
 115         else
 116                 val |= P(TLB, HIT);
 117
 118         /*
 119          * bit 0: hit L1 data cache
 120          * if not set, then all we know is that
 121          * it missed L1D
 122          */
 123         if (dse.st_l1d_hit)
 124                 val |= P(LVL, HIT);
 125         else
 126                 val |= P(LVL, MISS);
 127
 128         /*
 129          * bit 5: Locked prefix
 130          */
 131         if (dse.st_locked)
 132                 val |= P(LOCK, LOCKED);
 133
 134         return val;
 135 }
 136
 137 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 138 {
 139         union perf_mem_data_src dse;
 140
 141         dse.val = PERF_MEM_NA;
 142
 143         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 144                 dse.mem_op = PERF_MEM_OP_STORE;
 145         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 146                 dse.mem_op = PERF_MEM_OP_LOAD;
 147
 148         /*
 149          * L1 info only valid for following events:
 150          *
 151          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 152          * MEM_UOPS_RETIRED.LOCK_STORES
 153          * MEM_UOPS_RETIRED.SPLIT_STORES
 154          * MEM_UOPS_RETIRED.ALL_STORES
 155          */
 156         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 157                 if (status & 1)
 158                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 159                 else
 160                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 161         }
 162         return dse.val;
 163 }
 164
 165 static u64 load_latency_data(u64 status)
 166 {
 167         union intel_x86_pebs_dse dse;
 168         u64 val;
 169
 170         dse.val = status;
 171
 172         /*
 173          * use the mapping table for bit 0-3
 174          */
 175         val = pebs_data_source[dse.ld_dse];
 176
 177         /*
 178          * Nehalem models do not support TLB, Lock infos
 179          */
 180         if (x86_pmu.pebs_no_tlb) {
 181                 val |= P(TLB, NA) | P(LOCK, NA);
 182                 return val;
 183         }
 184         /*
 185          * bit 4: TLB access
 186          * 0 = did not miss 2nd level TLB
 187          * 1 = missed 2nd level TLB
 188          */
 189         if (dse.ld_stlb_miss)
 190                 val |= P(TLB, MISS) | P(TLB, L2);
 191         else
 192                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 193
 194         /*
 195          * bit 5: locked prefix
 196          */
 197         if (dse.ld_locked)
 198                 val |= P(LOCK, LOCKED);
 199
 200         return val;
 201 }
 202
 203 struct pebs_record_core {
 204         u64 flags, ip;
 205         u64 ax, bx, cx, dx;
 206         u64 si, di, bp, sp;
 207         u64 r8,  r9,  r10, r11;
 208         u64 r12, r13, r14, r15;
 209 };
 210
 211 struct pebs_record_nhm {
 212         u64 flags, ip;
 213         u64 ax, bx, cx, dx;
 214         u64 si, di, bp, sp;
 215         u64 r8,  r9,  r10, r11;
 216         u64 r12, r13, r14, r15;
 217         u64 status, dla, dse, lat;
 218 };
 219
 220 /*
 221  * Same as pebs_record_nhm, with two additional fields.
 222  */
 223 struct pebs_record_hsw {
 224         u64 flags, ip;
 225         u64 ax, bx, cx, dx;
 226         u64 si, di, bp, sp;
 227         u64 r8,  r9,  r10, r11;
 228         u64 r12, r13, r14, r15;
 229         u64 status, dla, dse, lat;
 230         u64 real_ip, tsx_tuning;
 231 };
 232
 233 union hsw_tsx_tuning {
 234         struct {
 235                 u32 cycles_last_block     : 32,
 236                     hle_abort             : 1,
 237                     rtm_abort             : 1,
 238                     instruction_abort     : 1,
 239                     non_instruction_abort : 1,
 240                     retry                 : 1,
 241                     data_conflict         : 1,
 242                     capacity_writes       : 1,
 243                     capacity_reads        : 1;
 244         };
 245         u64         value;
 246 };
 247
 248 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 249
 250 /* Same as HSW, plus TSC */
 251
 252 struct pebs_record_skl {
 253         u64 flags, ip;
 254         u64 ax, bx, cx, dx;
 255         u64 si, di, bp, sp;
 256         u64 r8,  r9,  r10, r11;
 257         u64 r12, r13, r14, r15;
 258         u64 status, dla, dse, lat;
 259         u64 real_ip, tsx_tuning;
 260         u64 tsc;
 261 };
 262
 263 void init_debug_store_on_cpu(int cpu)
 264 {
 265         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 266
 267         if (!ds)
 268                 return;
 269
 270         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 271                      (u32)((u64)(unsigned long)ds),
 272                      (u32)((u64)(unsigned long)ds >> 32));
 273 }
 274
 275 void fini_debug_store_on_cpu(int cpu)
 276 {
 277         if (!per_cpu(cpu_hw_events, cpu).ds)
 278                 return;
 279
 280         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 281 }
 282
 283 static DEFINE_PER_CPU(void *, insn_buffer);
 284
 285 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
 286 {
 287         unsigned long start = (unsigned long)cea;
 288         phys_addr_t pa;
 289         size_t msz = 0;
 290
 291         pa = virt_to_phys(addr);
 292
 293         preempt_disable();
 294         for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
 295                 cea_set_pte(cea, pa, prot);
 296
 297         /*
 298          * This is a cross-CPU update of the cpu_entry_area, we must shoot down
 299          * all TLB entries for it.
 300          */
 301         flush_tlb_kernel_range(start, start + size);
 302         preempt_enable();
 303 }
 304
 305 static void ds_clear_cea(void *cea, size_t size)
 306 {
 307         unsigned long start = (unsigned long)cea;
 308         size_t msz = 0;
 309
 310         preempt_disable();
 311         for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
 312                 cea_set_pte(cea, 0, PAGE_NONE);
 313
 314         flush_tlb_kernel_range(start, start + size);
 315         preempt_enable();
 316 }
 317
 318 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
 319 {
 320         unsigned int order = get_order(size);
 321         int node = cpu_to_node(cpu);
 322         struct page *page;
 323
 324         page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
 325         return page ? page_address(page) : NULL;
 326 }
 327
 328 static void dsfree_pages(const void *buffer, size_t size)
 329 {
 330         if (buffer)
 331                 free_pages((unsigned long)buffer, get_order(size));
 332 }
 333
 334 static int alloc_pebs_buffer(int cpu)
 335 {
 336         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 337         struct debug_store *ds = hwev->ds;
 338         size_t bsiz = x86_pmu.pebs_buffer_size;
 339         int max, node = cpu_to_node(cpu);
 340         void *buffer, *insn_buff, *cea;
 341
 342         if (!x86_pmu.pebs)
 343                 return 0;
 344
 345         buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
 346         if (unlikely(!buffer))
 347                 return -ENOMEM;
 348
 349         /*
 350          * HSW+ already provides us the eventing ip; no need to allocate this
 351          * buffer then.
 352          */
 353         if (x86_pmu.intel_cap.pebs_format < 2) {
 354                 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 355                 if (!insn_buff) {
 356                         dsfree_pages(buffer, bsiz);
 357                         return -ENOMEM;
 358                 }
 359                 per_cpu(insn_buffer, cpu) = insn_buff;
 360         }
 361         hwev->ds_pebs_vaddr = buffer;
 362         /* Update the cpu entry area mapping */
 363         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
 364         ds->pebs_buffer_base = (unsigned long) cea;
 365         ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
 366         ds->pebs_index = ds->pebs_buffer_base;
 367         max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
 368         ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
 369         return 0;
 370 }
 371
 372 static void release_pebs_buffer(int cpu)
 373 {
 374         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 375         void *cea;
 376
 377         if (!x86_pmu.pebs)
 378                 return;
 379
 380         kfree(per_cpu(insn_buffer, cpu));
 381         per_cpu(insn_buffer, cpu) = NULL;
 382
 383         /* Clear the fixmap */
 384         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
 385         ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
 386         dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
 387         hwev->ds_pebs_vaddr = NULL;
 388 }
 389
 390 static int alloc_bts_buffer(int cpu)
 391 {
 392         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 393         struct debug_store *ds = hwev->ds;
 394         void *buffer, *cea;
 395         int max;
 396
 397         if (!x86_pmu.bts)
 398                 return 0;
 399
 400         buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
 401         if (unlikely(!buffer)) {
 402                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 403                 return -ENOMEM;
 404         }
 405         hwev->ds_bts_vaddr = buffer;
 406         /* Update the fixmap */
 407         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
 408         ds->bts_buffer_base = (unsigned long) cea;
 409         ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
 410         ds->bts_index = ds->bts_buffer_base;
 411         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 412         ds->bts_absolute_maximum = ds->bts_buffer_base +
 413                                         max * BTS_RECORD_SIZE;
 414         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 415                                         (max / 16) * BTS_RECORD_SIZE;
 416         return 0;
 417 }
 418
 419 static void release_bts_buffer(int cpu)
 420 {
 421         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 422         void *cea;
 423
 424         if (!x86_pmu.bts)
 425                 return;
 426
 427         /* Clear the fixmap */
 428         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
 429         ds_clear_cea(cea, BTS_BUFFER_SIZE);
 430         dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
 431         hwev->ds_bts_vaddr = NULL;
 432 }
 433
 434 static int alloc_ds_buffer(int cpu)
 435 {
 436         struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
 437
 438         memset(ds, 0, sizeof(*ds));
 439         per_cpu(cpu_hw_events, cpu).ds = ds;
 440         return 0;
 441 }
 442
 443 static void release_ds_buffer(int cpu)
 444 {
 445         per_cpu(cpu_hw_events, cpu).ds = NULL;
 446 }
 447
 448 void release_ds_buffers(void)
 449 {
 450         int cpu;
 451
 452         if (!x86_pmu.bts && !x86_pmu.pebs)
 453                 return;
 454
 455         for_each_possible_cpu(cpu)
 456                 release_ds_buffer(cpu);
 457
 458         for_each_possible_cpu(cpu) {
 459                 /*
 460                  * Again, ignore errors from offline CPUs, they will no longer
 461                  * observe cpu_hw_events.ds and not program the DS_AREA when
 462                  * they come up.
 463                  */
 464                 fini_debug_store_on_cpu(cpu);
 465         }
 466
 467         for_each_possible_cpu(cpu) {
 468                 release_pebs_buffer(cpu);
 469                 release_bts_buffer(cpu);
 470         }
 471 }
 472
 473 void reserve_ds_buffers(void)
 474 {
 475         int bts_err = 0, pebs_err = 0;
 476         int cpu;
 477
 478         x86_pmu.bts_active = 0;
 479         x86_pmu.pebs_active = 0;
 480
 481         if (!x86_pmu.bts && !x86_pmu.pebs)
 482                 return;
 483
 484         if (!x86_pmu.bts)
 485                 bts_err = 1;
 486
 487         if (!x86_pmu.pebs)
 488                 pebs_err = 1;
 489
 490         for_each_possible_cpu(cpu) {
 491                 if (alloc_ds_buffer(cpu)) {
 492                         bts_err = 1;
 493                         pebs_err = 1;
 494                 }
 495
 496                 if (!bts_err && alloc_bts_buffer(cpu))
 497                         bts_err = 1;
 498
 499                 if (!pebs_err && alloc_pebs_buffer(cpu))
 500                         pebs_err = 1;
 501
 502                 if (bts_err && pebs_err)
 503                         break;
 504         }
 505
 506         if (bts_err) {
 507                 for_each_possible_cpu(cpu)
 508                         release_bts_buffer(cpu);
 509         }
 510
 511         if (pebs_err) {
 512                 for_each_possible_cpu(cpu)
 513                         release_pebs_buffer(cpu);
 514         }
 515
 516         if (bts_err && pebs_err) {
 517                 for_each_possible_cpu(cpu)
 518                         release_ds_buffer(cpu);
 519         } else {
 520                 if (x86_pmu.bts && !bts_err)
 521                         x86_pmu.bts_active = 1;
 522
 523                 if (x86_pmu.pebs && !pebs_err)
 524                         x86_pmu.pebs_active = 1;
 525
 526                 for_each_possible_cpu(cpu) {
 527                         /*
 528                          * Ignores wrmsr_on_cpu() errors for offline CPUs they
 529                          * will get this call through intel_pmu_cpu_starting().
 530                          */
 531                         init_debug_store_on_cpu(cpu);
 532                 }
 533         }
 534 }
 535
 536 /*
 537  * BTS
 538  */
 539
 540 struct event_constraint bts_constraint =
 541         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 542
 543 void intel_pmu_enable_bts(u64 config)
 544 {
 545         unsigned long debugctlmsr;
 546
 547         debugctlmsr = get_debugctlmsr();
 548
 549         debugctlmsr |= DEBUGCTLMSR_TR;
 550         debugctlmsr |= DEBUGCTLMSR_BTS;
 551         if (config & ARCH_PERFMON_EVENTSEL_INT)
 552                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 553
 554         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 555                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 556
 557         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 558                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 559
 560         update_debugctlmsr(debugctlmsr);
 561 }
 562
 563 void intel_pmu_disable_bts(void)
 564 {
 565         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 566         unsigned long debugctlmsr;
 567
 568         if (!cpuc->ds)
 569                 return;
 570
 571         debugctlmsr = get_debugctlmsr();
 572
 573         debugctlmsr &=
 574                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 575                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 576
 577         update_debugctlmsr(debugctlmsr);
 578 }
 579
 580 int intel_pmu_drain_bts_buffer(void)
 581 {
 582         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 583         struct debug_store *ds = cpuc->ds;
 584         struct bts_record {
 585                 u64     from;
 586                 u64     to;
 587                 u64     flags;
 588         };
 589         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 590         struct bts_record *at, *base, *top;
 591         struct perf_output_handle handle;
 592         struct perf_event_header header;
 593         struct perf_sample_data data;
 594         unsigned long skip = 0;
 595         struct pt_regs regs;
 596
 597         if (!event)
 598                 return 0;
 599
 600         if (!x86_pmu.bts_active)
 601                 return 0;
 602
 603         base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 604         top  = (struct bts_record *)(unsigned long)ds->bts_index;
 605
 606         if (top <= base)
 607                 return 0;
 608
 609         memset(&regs, 0, sizeof(regs));
 610
 611         ds->bts_index = ds->bts_buffer_base;
 612
 613         perf_sample_data_init(&data, 0, event->hw.last_period);
 614
 615         /*
 616          * BTS leaks kernel addresses in branches across the cpl boundary,
 617          * such as traps or system calls, so unless the user is asking for
 618          * kernel tracing (and right now it's not possible), we'd need to
 619          * filter them out. But first we need to count how many of those we
 620          * have in the current batch. This is an extra O(n) pass, however,
 621          * it's much faster than the other one especially considering that
 622          * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
 623          * alloc_bts_buffer()).
 624          */
 625         for (at = base; at < top; at++) {
 626                 /*
 627                  * Note that right now *this* BTS code only works if
 628                  * attr::exclude_kernel is set, but let's keep this extra
 629                  * check here in case that changes.
 630                  */
 631                 if (event->attr.exclude_kernel &&
 632                     (kernel_ip(at->from) || kernel_ip(at->to)))
 633                         skip++;
 634         }
 635
 636         /*
 637          * Prepare a generic sample, i.e. fill in the invariant fields.
 638          * We will overwrite the from and to address before we output
 639          * the sample.
 640          */
 641         rcu_read_lock();
 642         perf_prepare_sample(&header, &data, event, &regs);
 643
 644         if (perf_output_begin(&handle, event, header.size *
 645                               (top - base - skip)))
 646                 goto unlock;
 647
 648         for (at = base; at < top; at++) {
 649                 /* Filter out any records that contain kernel addresses. */
 650                 if (event->attr.exclude_kernel &&
 651                     (kernel_ip(at->from) || kernel_ip(at->to)))
 652                         continue;
 653
 654                 data.ip         = at->from;
 655                 data.addr       = at->to;
 656
 657                 perf_output_sample(&handle, &header, &data, event);
 658         }
 659
 660         perf_output_end(&handle);
 661
 662         /* There's new data available. */
 663         event->hw.interrupts++;
 664         event->pending_kill = POLL_IN;
 665 unlock:
 666         rcu_read_unlock();
 667         return 1;
 668 }
 669
 670 static inline void intel_pmu_drain_pebs_buffer(void)
 671 {
 672         x86_pmu.drain_pebs(NULL);
 673 }
 674
 675 /*
 676  * PEBS
 677  */
 678 struct event_constraint intel_core2_pebs_event_constraints[] = {
 679         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 680         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 681         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 682         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 683         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 684         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 685         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
 686         EVENT_CONSTRAINT_END
 687 };
 688
 689 struct event_constraint intel_atom_pebs_event_constraints[] = {
 690         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 691         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 692         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 693         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 694         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
 695         /* Allow all events as PEBS with no flags */
 696         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 697         EVENT_CONSTRAINT_END
 698 };
 699
 700 struct event_constraint intel_slm_pebs_event_constraints[] = {
 701         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 702         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
 703         /* Allow all events as PEBS with no flags */
 704         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 705         EVENT_CONSTRAINT_END
 706 };
 707
 708 struct event_constraint intel_glm_pebs_event_constraints[] = {
 709         /* Allow all events as PEBS with no flags */
 710         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 711         EVENT_CONSTRAINT_END
 712 };
 713
 714 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 715         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 716         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 717         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 718         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 719         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 720         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 721         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 722         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 723         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 724         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 725         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 726         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 727         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 728         EVENT_CONSTRAINT_END
 729 };
 730
 731 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 732         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 733         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 734         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 735         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 736         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 737         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 738         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 739         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 740         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 741         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 742         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 743         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 744         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 745         EVENT_CONSTRAINT_END
 746 };
 747
 748 struct event_constraint intel_snb_pebs_event_constraints[] = {
 749         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 750         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 751         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 752         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 753         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 754         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 755         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 756         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 757         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 758         /* Allow all events as PEBS with no flags */
 759         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 760         EVENT_CONSTRAINT_END
 761 };
 762
 763 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 764         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 765         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 766         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 767         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 768         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 769         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 770         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 771         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 772         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 773         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 774         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 775         /* Allow all events as PEBS with no flags */
 776         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 777         EVENT_CONSTRAINT_END
 778 };
 779
 780 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 781         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 782         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 783         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 784         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 785         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 786         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 787         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 788         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 789         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 790         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 791         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 792         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 793         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 794         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 795         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 796         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 797         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 798         /* Allow all events as PEBS with no flags */
 799         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 800         EVENT_CONSTRAINT_END
 801 };
 802
 803 struct event_constraint intel_bdw_pebs_event_constraints[] = {
 804         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 805         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 806         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 807         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 808         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 809         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 810         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 811         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 812         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 813         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 814         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 815         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 816         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 817         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 818         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 819         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 820         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 821         /* Allow all events as PEBS with no flags */
 822         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 823         EVENT_CONSTRAINT_END
 824 };
 825
 826
 827 struct event_constraint intel_skl_pebs_event_constraints[] = {
 828         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 829         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 830         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 831         /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
 832         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 833         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 834         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 835         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 836         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
 837         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
 838         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
 839         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
 840         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
 841         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
 842         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
 843         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
 844         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
 845         /* Allow all events as PEBS with no flags */
 846         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 847         EVENT_CONSTRAINT_END
 848 };
 849
 850 struct event_constraint intel_icl_pebs_event_constraints[] = {
 851         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),   /* INST_RETIRED.PREC_DIST */
 852         INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),  /* SLOTS */
 853
 854         INTEL_PLD_CONSTRAINT(0x1cd, 0xff),                      /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 855         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),   /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 856         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),   /* MEM_INST_RETIRED.STLB_MISS_STORES */
 857         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),   /* MEM_INST_RETIRED.LOCK_LOADS */
 858         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),   /* MEM_INST_RETIRED.SPLIT_LOADS */
 859         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),   /* MEM_INST_RETIRED.SPLIT_STORES */
 860         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),   /* MEM_INST_RETIRED.ALL_LOADS */
 861         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),   /* MEM_INST_RETIRED.ALL_STORES */
 862
 863         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
 864
 865         INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),                /* MEM_INST_RETIRED.* */
 866
 867         /*
 868          * Everything else is handled by PMU_FL_PEBS_ALL, because we
 869          * need the full constraints from the main table.
 870          */
 871
 872         EVENT_CONSTRAINT_END
 873 };
 874
 875 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 876 {
 877         struct event_constraint *c;
 878
 879         if (!event->attr.precise_ip)
 880                 return NULL;
 881
 882         if (x86_pmu.pebs_constraints) {
 883                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 884                         if (constraint_match(c, event->hw.config)) {
 885                                 event->hw.flags |= c->flags;
 886                                 return c;
 887                         }
 888                 }
 889         }
 890
 891         /*
 892          * Extended PEBS support
 893          * Makes the PEBS code search the normal constraints.
 894          */
 895         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
 896                 return NULL;
 897
 898         return &emptyconstraint;
 899 }
 900
 901 /*
 902  * We need the sched_task callback even for per-cpu events when we use
 903  * the large interrupt threshold, such that we can provide PID and TID
 904  * to PEBS samples.
 905  */
 906 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
 907 {
 908         if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
 909                 return false;
 910
 911         return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
 912 }
 913
 914 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
 915 {
 916         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 917
 918         if (!sched_in && pebs_needs_sched_cb(cpuc))
 919                 intel_pmu_drain_pebs_buffer();
 920 }
 921
 922 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
 923 {
 924         struct debug_store *ds = cpuc->ds;
 925         u64 threshold;
 926         int reserved;
 927
 928         if (cpuc->n_pebs_via_pt)
 929                 return;
 930
 931         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
 932                 reserved = x86_pmu.max_pebs_events + x86_pmu.num_counters_fixed;
 933         else
 934                 reserved = x86_pmu.max_pebs_events;
 935
 936         if (cpuc->n_pebs == cpuc->n_large_pebs) {
 937                 threshold = ds->pebs_absolute_maximum -
 938                         reserved * cpuc->pebs_record_size;
 939         } else {
 940                 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
 941         }
 942
 943         ds->pebs_interrupt_threshold = threshold;
 944 }
 945
 946 static void adaptive_pebs_record_size_update(void)
 947 {
 948         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 949         u64 pebs_data_cfg = cpuc->pebs_data_cfg;
 950         int sz = sizeof(struct pebs_basic);
 951
 952         if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
 953                 sz += sizeof(struct pebs_meminfo);
 954         if (pebs_data_cfg & PEBS_DATACFG_GP)
 955                 sz += sizeof(struct pebs_gprs);
 956         if (pebs_data_cfg & PEBS_DATACFG_XMMS)
 957                 sz += sizeof(struct pebs_xmm);
 958         if (pebs_data_cfg & PEBS_DATACFG_LBRS)
 959                 sz += x86_pmu.lbr_nr * sizeof(struct pebs_lbr_entry);
 960
 961         cpuc->pebs_record_size = sz;
 962 }
 963
 964 #define PERF_PEBS_MEMINFO_TYPE  (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC |   \
 965                                 PERF_SAMPLE_PHYS_ADDR | PERF_SAMPLE_WEIGHT | \
 966                                 PERF_SAMPLE_TRANSACTION)
 967
 968 static u64 pebs_update_adaptive_cfg(struct perf_event *event)
 969 {
 970         struct perf_event_attr *attr = &event->attr;
 971         u64 sample_type = attr->sample_type;
 972         u64 pebs_data_cfg = 0;
 973         bool gprs, tsx_weight;
 974
 975         if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
 976             attr->precise_ip > 1)
 977                 return pebs_data_cfg;
 978
 979         if (sample_type & PERF_PEBS_MEMINFO_TYPE)
 980                 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
 981
 982         /*
 983          * We need GPRs when:
 984          * + user requested them
 985          * + precise_ip < 2 for the non event IP
 986          * + For RTM TSX weight we need GPRs for the abort code.
 987          */
 988         gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
 989                (attr->sample_regs_intr & PEBS_GP_REGS);
 990
 991         tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT) &&
 992                      ((attr->config & INTEL_ARCH_EVENT_MASK) ==
 993                       x86_pmu.rtm_abort_event);
 994
 995         if (gprs || (attr->precise_ip < 2) || tsx_weight)
 996                 pebs_data_cfg |= PEBS_DATACFG_GP;
 997
 998         if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
 999             (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1000                 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1001
1002         if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1003                 /*
1004                  * For now always log all LBRs. Could configure this
1005                  * later.
1006                  */
1007                 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1008                         ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1009         }
1010
1011         return pebs_data_cfg;
1012 }
1013
1014 static void
1015 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1016                   struct perf_event *event, bool add)
1017 {
1018         struct pmu *pmu = event->ctx->pmu;
1019         /*
1020          * Make sure we get updated with the first PEBS
1021          * event. It will trigger also during removal, but
1022          * that does not hurt:
1023          */
1024         bool update = cpuc->n_pebs == 1;
1025
1026         if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1027                 if (!needed_cb)
1028                         perf_sched_cb_inc(pmu);
1029                 else
1030                         perf_sched_cb_dec(pmu);
1031
1032                 update = true;
1033         }
1034
1035         /*
1036          * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1037          * iterating all remaining PEBS events to reconstruct the config.
1038          */
1039         if (x86_pmu.intel_cap.pebs_baseline && add) {
1040                 u64 pebs_data_cfg;
1041
1042                 /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1043                 if (cpuc->n_pebs == 1) {
1044                         cpuc->pebs_data_cfg = 0;
1045                         cpuc->pebs_record_size = sizeof(struct pebs_basic);
1046                 }
1047
1048                 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1049
1050                 /* Update pebs_record_size if new event requires more data. */
1051                 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1052                         cpuc->pebs_data_cfg |= pebs_data_cfg;
1053                         adaptive_pebs_record_size_update();
1054                         update = true;
1055                 }
1056         }
1057
1058         if (update)
1059                 pebs_update_threshold(cpuc);
1060 }
1061
1062 void intel_pmu_pebs_add(struct perf_event *event)
1063 {
1064         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1065         struct hw_perf_event *hwc = &event->hw;
1066         bool needed_cb = pebs_needs_sched_cb(cpuc);
1067
1068         cpuc->n_pebs++;
1069         if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1070                 cpuc->n_large_pebs++;
1071         if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1072                 cpuc->n_pebs_via_pt++;
1073
1074         pebs_update_state(needed_cb, cpuc, event, true);
1075 }
1076
1077 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1078 {
1079         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1080
1081         if (!is_pebs_pt(event))
1082                 return;
1083
1084         if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1085                 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1086 }
1087
1088 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1089 {
1090         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1091         struct hw_perf_event *hwc = &event->hw;
1092         struct debug_store *ds = cpuc->ds;
1093
1094         if (!is_pebs_pt(event))
1095                 return;
1096
1097         if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1098                 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1099
1100         cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1101
1102         wrmsrl(MSR_RELOAD_PMC0 + hwc->idx, ds->pebs_event_reset[hwc->idx]);
1103 }
1104
1105 void intel_pmu_pebs_enable(struct perf_event *event)
1106 {
1107         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1108         struct hw_perf_event *hwc = &event->hw;
1109         struct debug_store *ds = cpuc->ds;
1110
1111         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1112
1113         cpuc->pebs_enabled |= 1ULL << hwc->idx;
1114
1115         if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1116                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1117         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1118                 cpuc->pebs_enabled |= 1ULL << 63;
1119
1120         if (x86_pmu.intel_cap.pebs_baseline) {
1121                 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1122                 if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1123                         wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1124                         cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1125                 }
1126         }
1127
1128         /*
1129          * Use auto-reload if possible to save a MSR write in the PMI.
1130          * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1131          */
1132         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1133                 unsigned int idx = hwc->idx;
1134
1135                 if (idx >= INTEL_PMC_IDX_FIXED)
1136                         idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1137                 ds->pebs_event_reset[idx] =
1138                         (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1139         } else {
1140                 ds->pebs_event_reset[hwc->idx] = 0;
1141         }
1142
1143         intel_pmu_pebs_via_pt_enable(event);
1144 }
1145
1146 void intel_pmu_pebs_del(struct perf_event *event)
1147 {
1148         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1149         struct hw_perf_event *hwc = &event->hw;
1150         bool needed_cb = pebs_needs_sched_cb(cpuc);
1151
1152         cpuc->n_pebs--;
1153         if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1154                 cpuc->n_large_pebs--;
1155         if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1156                 cpuc->n_pebs_via_pt--;
1157
1158         pebs_update_state(needed_cb, cpuc, event, false);
1159 }
1160
1161 void intel_pmu_pebs_disable(struct perf_event *event)
1162 {
1163         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1164         struct hw_perf_event *hwc = &event->hw;
1165
1166         if (cpuc->n_pebs == cpuc->n_large_pebs &&
1167             cpuc->n_pebs != cpuc->n_pebs_via_pt)
1168                 intel_pmu_drain_pebs_buffer();
1169
1170         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1171
1172         if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1173             (x86_pmu.version < 5))
1174                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1175         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1176                 cpuc->pebs_enabled &= ~(1ULL << 63);
1177
1178         intel_pmu_pebs_via_pt_disable(event);
1179
1180         if (cpuc->enabled)
1181                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1182
1183         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1184 }
1185
1186 void intel_pmu_pebs_enable_all(void)
1187 {
1188         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1189
1190         if (cpuc->pebs_enabled)
1191                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1192 }
1193
1194 void intel_pmu_pebs_disable_all(void)
1195 {
1196         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1197
1198         if (cpuc->pebs_enabled)
1199                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1200 }
1201
1202 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1203 {
1204         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1205         unsigned long from = cpuc->lbr_entries[0].from;
1206         unsigned long old_to, to = cpuc->lbr_entries[0].to;
1207         unsigned long ip = regs->ip;
1208         int is_64bit = 0;
1209         void *kaddr;
1210         int size;
1211
1212         /*
1213          * We don't need to fixup if the PEBS assist is fault like
1214          */
1215         if (!x86_pmu.intel_cap.pebs_trap)
1216                 return 1;
1217
1218         /*
1219          * No LBR entry, no basic block, no rewinding
1220          */
1221         if (!cpuc->lbr_stack.nr || !from || !to)
1222                 return 0;
1223
1224         /*
1225          * Basic blocks should never cross user/kernel boundaries
1226          */
1227         if (kernel_ip(ip) != kernel_ip(to))
1228                 return 0;
1229
1230         /*
1231          * unsigned math, either ip is before the start (impossible) or
1232          * the basic block is larger than 1 page (sanity)
1233          */
1234         if ((ip - to) > PEBS_FIXUP_SIZE)
1235                 return 0;
1236
1237         /*
1238          * We sampled a branch insn, rewind using the LBR stack
1239          */
1240         if (ip == to) {
1241                 set_linear_ip(regs, from);
1242                 return 1;
1243         }
1244
1245         size = ip - to;
1246         if (!kernel_ip(ip)) {
1247                 int bytes;
1248                 u8 *buf = this_cpu_read(insn_buffer);
1249
1250                 /* 'size' must fit our buffer, see above */
1251                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1252                 if (bytes != 0)
1253                         return 0;
1254
1255                 kaddr = buf;
1256         } else {
1257                 kaddr = (void *)to;
1258         }
1259
1260         do {
1261                 struct insn insn;
1262
1263                 old_to = to;
1264
1265 #ifdef CONFIG_X86_64
1266                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
1267 #endif
1268                 insn_init(&insn, kaddr, size, is_64bit);
1269                 insn_get_length(&insn);
1270                 /*
1271                  * Make sure there was not a problem decoding the
1272                  * instruction and getting the length.  This is
1273                  * doubly important because we have an infinite
1274                  * loop if insn.length=0.
1275                  */
1276                 if (!insn.length)
1277                         break;
1278
1279                 to += insn.length;
1280                 kaddr += insn.length;
1281                 size -= insn.length;
1282         } while (to < ip);
1283
1284         if (to == ip) {
1285                 set_linear_ip(regs, old_to);
1286                 return 1;
1287         }
1288
1289         /*
1290          * Even though we decoded the basic block, the instruction stream
1291          * never matched the given IP, either the TO or the IP got corrupted.
1292          */
1293         return 0;
1294 }
1295
1296 static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1297 {
1298         if (tsx_tuning) {
1299                 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1300                 return tsx.cycles_last_block;
1301         }
1302         return 0;
1303 }
1304
1305 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1306 {
1307         u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1308
1309         /* For RTM XABORTs also log the abort code from AX */
1310         if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1311                 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1312         return txn;
1313 }
1314
1315 static inline u64 get_pebs_status(void *n)
1316 {
1317         if (x86_pmu.intel_cap.pebs_format < 4)
1318                 return ((struct pebs_record_nhm *)n)->status;
1319         return ((struct pebs_basic *)n)->applicable_counters;
1320 }
1321
1322 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1323                 (PERF_X86_EVENT_PEBS_ST_HSW | \
1324                  PERF_X86_EVENT_PEBS_LD_HSW | \
1325                  PERF_X86_EVENT_PEBS_NA_HSW)
1326
1327 static u64 get_data_src(struct perf_event *event, u64 aux)
1328 {
1329         u64 val = PERF_MEM_NA;
1330         int fl = event->hw.flags;
1331         bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1332
1333         if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1334                 val = load_latency_data(aux);
1335         else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1336                 val = precise_datala_hsw(event, aux);
1337         else if (fst)
1338                 val = precise_store_data(aux);
1339         return val;
1340 }
1341
1342 static void setup_pebs_fixed_sample_data(struct perf_event *event,
1343                                    struct pt_regs *iregs, void *__pebs,
1344                                    struct perf_sample_data *data,
1345                                    struct pt_regs *regs)
1346 {
1347         /*
1348          * We cast to the biggest pebs_record but are careful not to
1349          * unconditionally access the 'extra' entries.
1350          */
1351         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1352         struct pebs_record_skl *pebs = __pebs;
1353         u64 sample_type;
1354         int fll;
1355
1356         if (pebs == NULL)
1357                 return;
1358
1359         sample_type = event->attr.sample_type;
1360         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1361
1362         perf_sample_data_init(data, 0, event->hw.last_period);
1363
1364         data->period = event->hw.last_period;
1365
1366         /*
1367          * Use latency for weight (only avail with PEBS-LL)
1368          */
1369         if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1370                 data->weight = pebs->lat;
1371
1372         /*
1373          * data.data_src encodes the data source
1374          */
1375         if (sample_type & PERF_SAMPLE_DATA_SRC)
1376                 data->data_src.val = get_data_src(event, pebs->dse);
1377
1378         /*
1379          * We must however always use iregs for the unwinder to stay sane; the
1380          * record BP,SP,IP can point into thin air when the record is from a
1381          * previous PMI context or an (I)RET happened between the record and
1382          * PMI.
1383          */
1384         if (sample_type & PERF_SAMPLE_CALLCHAIN)
1385                 data->callchain = perf_callchain(event, iregs);
1386
1387         /*
1388          * We use the interrupt regs as a base because the PEBS record does not
1389          * contain a full regs set, specifically it seems to lack segment
1390          * descriptors, which get used by things like user_mode().
1391          *
1392          * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1393          */
1394         *regs = *iregs;
1395
1396         /*
1397          * Initialize regs_>flags from PEBS,
1398          * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1399          * i.e., do not rely on it being zero:
1400          */
1401         regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1402
1403         if (sample_type & PERF_SAMPLE_REGS_INTR) {
1404                 regs->ax = pebs->ax;
1405                 regs->bx = pebs->bx;
1406                 regs->cx = pebs->cx;
1407                 regs->dx = pebs->dx;
1408                 regs->si = pebs->si;
1409                 regs->di = pebs->di;
1410
1411                 regs->bp = pebs->bp;
1412                 regs->sp = pebs->sp;
1413
1414 #ifndef CONFIG_X86_32
1415                 regs->r8 = pebs->r8;
1416                 regs->r9 = pebs->r9;
1417                 regs->r10 = pebs->r10;
1418                 regs->r11 = pebs->r11;
1419                 regs->r12 = pebs->r12;
1420                 regs->r13 = pebs->r13;
1421                 regs->r14 = pebs->r14;
1422                 regs->r15 = pebs->r15;
1423 #endif
1424         }
1425
1426         if (event->attr.precise_ip > 1) {
1427                 /*
1428                  * Haswell and later processors have an 'eventing IP'
1429                  * (real IP) which fixes the off-by-1 skid in hardware.
1430                  * Use it when precise_ip >= 2 :
1431                  */
1432                 if (x86_pmu.intel_cap.pebs_format >= 2) {
1433                         set_linear_ip(regs, pebs->real_ip);
1434                         regs->flags |= PERF_EFLAGS_EXACT;
1435                 } else {
1436                         /* Otherwise, use PEBS off-by-1 IP: */
1437                         set_linear_ip(regs, pebs->ip);
1438
1439                         /*
1440                          * With precise_ip >= 2, try to fix up the off-by-1 IP
1441                          * using the LBR. If successful, the fixup function
1442                          * corrects regs->ip and calls set_linear_ip() on regs:
1443                          */
1444                         if (intel_pmu_pebs_fixup_ip(regs))
1445                                 regs->flags |= PERF_EFLAGS_EXACT;
1446                 }
1447         } else {
1448                 /*
1449                  * When precise_ip == 1, return the PEBS off-by-1 IP,
1450                  * no fixup attempted:
1451                  */
1452                 set_linear_ip(regs, pebs->ip);
1453         }
1454
1455
1456         if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) &&
1457             x86_pmu.intel_cap.pebs_format >= 1)
1458                 data->addr = pebs->dla;
1459
1460         if (x86_pmu.intel_cap.pebs_format >= 2) {
1461                 /* Only set the TSX weight when no memory weight. */
1462                 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1463                         data->weight = intel_get_tsx_weight(pebs->tsx_tuning);
1464
1465                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1466                         data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1467                                                               pebs->ax);
1468         }
1469
1470         /*
1471          * v3 supplies an accurate time stamp, so we use that
1472          * for the time stamp.
1473          *
1474          * We can only do this for the default trace clock.
1475          */
1476         if (x86_pmu.intel_cap.pebs_format >= 3 &&
1477                 event->attr.use_clockid == 0)
1478                 data->time = native_sched_clock_from_tsc(pebs->tsc);
1479
1480         if (has_branch_stack(event))
1481                 data->br_stack = &cpuc->lbr_stack;
1482 }
1483
1484 static void adaptive_pebs_save_regs(struct pt_regs *regs,
1485                                     struct pebs_gprs *gprs)
1486 {
1487         regs->ax = gprs->ax;
1488         regs->bx = gprs->bx;
1489         regs->cx = gprs->cx;
1490         regs->dx = gprs->dx;
1491         regs->si = gprs->si;
1492         regs->di = gprs->di;
1493         regs->bp = gprs->bp;
1494         regs->sp = gprs->sp;
1495 #ifndef CONFIG_X86_32
1496         regs->r8 = gprs->r8;
1497         regs->r9 = gprs->r9;
1498         regs->r10 = gprs->r10;
1499         regs->r11 = gprs->r11;
1500         regs->r12 = gprs->r12;
1501         regs->r13 = gprs->r13;
1502         regs->r14 = gprs->r14;
1503         regs->r15 = gprs->r15;
1504 #endif
1505 }
1506
1507 /*
1508  * With adaptive PEBS the layout depends on what fields are configured.
1509  */
1510
1511 static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1512                                             struct pt_regs *iregs, void *__pebs,
1513                                             struct perf_sample_data *data,
1514                                             struct pt_regs *regs)
1515 {
1516         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1517         struct pebs_basic *basic = __pebs;
1518         void *next_record = basic + 1;
1519         u64 sample_type;
1520         u64 format_size;
1521         struct pebs_meminfo *meminfo = NULL;
1522         struct pebs_gprs *gprs = NULL;
1523         struct x86_perf_regs *perf_regs;
1524
1525         if (basic == NULL)
1526                 return;
1527
1528         perf_regs = container_of(regs, struct x86_perf_regs, regs);
1529         perf_regs->xmm_regs = NULL;
1530
1531         sample_type = event->attr.sample_type;
1532         format_size = basic->format_size;
1533         perf_sample_data_init(data, 0, event->hw.last_period);
1534         data->period = event->hw.last_period;
1535
1536         if (event->attr.use_clockid == 0)
1537                 data->time = native_sched_clock_from_tsc(basic->tsc);
1538
1539         /*
1540          * We must however always use iregs for the unwinder to stay sane; the
1541          * record BP,SP,IP can point into thin air when the record is from a
1542          * previous PMI context or an (I)RET happened between the record and
1543          * PMI.
1544          */
1545         if (sample_type & PERF_SAMPLE_CALLCHAIN)
1546                 data->callchain = perf_callchain(event, iregs);
1547
1548         *regs = *iregs;
1549         /* The ip in basic is EventingIP */
1550         set_linear_ip(regs, basic->ip);
1551         regs->flags = PERF_EFLAGS_EXACT;
1552
1553         /*
1554          * The record for MEMINFO is in front of GP
1555          * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1556          * Save the pointer here but process later.
1557          */
1558         if (format_size & PEBS_DATACFG_MEMINFO) {
1559                 meminfo = next_record;
1560                 next_record = meminfo + 1;
1561         }
1562
1563         if (format_size & PEBS_DATACFG_GP) {
1564                 gprs = next_record;
1565                 next_record = gprs + 1;
1566
1567                 if (event->attr.precise_ip < 2) {
1568                         set_linear_ip(regs, gprs->ip);
1569                         regs->flags &= ~PERF_EFLAGS_EXACT;
1570                 }
1571
1572                 if (sample_type & PERF_SAMPLE_REGS_INTR)
1573                         adaptive_pebs_save_regs(regs, gprs);
1574         }
1575
1576         if (format_size & PEBS_DATACFG_MEMINFO) {
1577                 if (sample_type & PERF_SAMPLE_WEIGHT)
1578                         data->weight = meminfo->latency ?:
1579                                 intel_get_tsx_weight(meminfo->tsx_tuning);
1580
1581                 if (sample_type & PERF_SAMPLE_DATA_SRC)
1582                         data->data_src.val = get_data_src(event, meminfo->aux);
1583
1584                 if (sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
1585                         data->addr = meminfo->address;
1586
1587                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1588                         data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
1589                                                           gprs ? gprs->ax : 0);
1590         }
1591
1592         if (format_size & PEBS_DATACFG_XMMS) {
1593                 struct pebs_xmm *xmm = next_record;
1594
1595                 next_record = xmm + 1;
1596                 perf_regs->xmm_regs = xmm->xmm;
1597         }
1598
1599         if (format_size & PEBS_DATACFG_LBRS) {
1600                 struct pebs_lbr *lbr = next_record;
1601                 int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
1602                                         & 0xff) + 1;
1603                 next_record = next_record + num_lbr*sizeof(struct pebs_lbr_entry);
1604
1605                 if (has_branch_stack(event)) {
1606                         intel_pmu_store_pebs_lbrs(lbr);
1607                         data->br_stack = &cpuc->lbr_stack;
1608                 }
1609         }
1610
1611         WARN_ONCE(next_record != __pebs + (format_size >> 48),
1612                         "PEBS record size %llu, expected %llu, config %llx\n",
1613                         format_size >> 48,
1614                         (u64)(next_record - __pebs),
1615                         basic->format_size);
1616 }
1617
1618 static inline void *
1619 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1620 {
1621         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1622         void *at;
1623         u64 pebs_status;
1624
1625         /*
1626          * fmt0 does not have a status bitfield (does not use
1627          * perf_record_nhm format)
1628          */
1629         if (x86_pmu.intel_cap.pebs_format < 1)
1630                 return base;
1631
1632         if (base == NULL)
1633                 return NULL;
1634
1635         for (at = base; at < top; at += cpuc->pebs_record_size) {
1636                 unsigned long status = get_pebs_status(at);
1637
1638                 if (test_bit(bit, (unsigned long *)&status)) {
1639                         /* PEBS v3 has accurate status bits */
1640                         if (x86_pmu.intel_cap.pebs_format >= 3)
1641                                 return at;
1642
1643                         if (status == (1 << bit))
1644                                 return at;
1645
1646                         /* clear non-PEBS bit and re-check */
1647                         pebs_status = status & cpuc->pebs_enabled;
1648                         pebs_status &= PEBS_COUNTER_MASK;
1649                         if (pebs_status == (1 << bit))
1650                                 return at;
1651                 }
1652         }
1653         return NULL;
1654 }
1655
1656 void intel_pmu_auto_reload_read(struct perf_event *event)
1657 {
1658         WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
1659
1660         perf_pmu_disable(event->pmu);
1661         intel_pmu_drain_pebs_buffer();
1662         perf_pmu_enable(event->pmu);
1663 }
1664
1665 /*
1666  * Special variant of intel_pmu_save_and_restart() for auto-reload.
1667  */
1668 static int
1669 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1670 {
1671         struct hw_perf_event *hwc = &event->hw;
1672         int shift = 64 - x86_pmu.cntval_bits;
1673         u64 period = hwc->sample_period;
1674         u64 prev_raw_count, new_raw_count;
1675         s64 new, old;
1676
1677         WARN_ON(!period);
1678
1679         /*
1680          * drain_pebs() only happens when the PMU is disabled.
1681          */
1682         WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1683
1684         prev_raw_count = local64_read(&hwc->prev_count);
1685         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1686         local64_set(&hwc->prev_count, new_raw_count);
1687
1688         /*
1689          * Since the counter increments a negative counter value and
1690          * overflows on the sign switch, giving the interval:
1691          *
1692          *   [-period, 0]
1693          *
1694          * the difference between two consequtive reads is:
1695          *
1696          *   A) value2 - value1;
1697          *      when no overflows have happened in between,
1698          *
1699          *   B) (0 - value1) + (value2 - (-period));
1700          *      when one overflow happened in between,
1701          *
1702          *   C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1703          *      when @n overflows happened in between.
1704          *
1705          * Here A) is the obvious difference, B) is the extension to the
1706          * discrete interval, where the first term is to the top of the
1707          * interval and the second term is from the bottom of the next
1708          * interval and C) the extension to multiple intervals, where the
1709          * middle term is the whole intervals covered.
1710          *
1711          * An equivalent of C, by reduction, is:
1712          *
1713          *   value2 - value1 + n * period
1714          */
1715         new = ((s64)(new_raw_count << shift) >> shift);
1716         old = ((s64)(prev_raw_count << shift) >> shift);
1717         local64_add(new - old + count * period, &event->count);
1718
1719         local64_set(&hwc->period_left, -new);
1720
1721         perf_event_update_userpage(event);
1722
1723         return 0;
1724 }
1725
1726 static void __intel_pmu_pebs_event(struct perf_event *event,
1727                                    struct pt_regs *iregs,
1728                                    void *base, void *top,
1729                                    int bit, int count,
1730                                    void (*setup_sample)(struct perf_event *,
1731                                                 struct pt_regs *,
1732                                                 void *,
1733                                                 struct perf_sample_data *,
1734                                                 struct pt_regs *))
1735 {
1736         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1737         struct hw_perf_event *hwc = &event->hw;
1738         struct perf_sample_data data;
1739         struct x86_perf_regs perf_regs;
1740         struct pt_regs *regs = &perf_regs.regs;
1741         void *at = get_next_pebs_record_by_bit(base, top, bit);
1742         struct pt_regs dummy_iregs;
1743
1744         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1745                 /*
1746                  * Now, auto-reload is only enabled in fixed period mode.
1747                  * The reload value is always hwc->sample_period.
1748                  * May need to change it, if auto-reload is enabled in
1749                  * freq mode later.
1750                  */
1751                 intel_pmu_save_and_restart_reload(event, count);
1752         } else if (!intel_pmu_save_and_restart(event))
1753                 return;
1754
1755         if (!iregs)
1756                 iregs = &dummy_iregs;
1757
1758         while (count > 1) {
1759                 setup_sample(event, iregs, at, &data, regs);
1760                 perf_event_output(event, &data, regs);
1761                 at += cpuc->pebs_record_size;
1762                 at = get_next_pebs_record_by_bit(at, top, bit);
1763                 count--;
1764         }
1765
1766         setup_sample(event, iregs, at, &data, regs);
1767         if (iregs == &dummy_iregs) {
1768                 /*
1769                  * The PEBS records may be drained in the non-overflow context,
1770                  * e.g., large PEBS + context switch. Perf should treat the
1771                  * last record the same as other PEBS records, and doesn't
1772                  * invoke the generic overflow handler.
1773                  */
1774                 perf_event_output(event, &data, regs);
1775         } else {
1776                 /*
1777                  * All but the last records are processed.
1778                  * The last one is left to be able to call the overflow handler.
1779                  */
1780                 if (perf_event_overflow(event, &data, regs))
1781                         x86_pmu_stop(event, 0);
1782         }
1783 }
1784
1785 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1786 {
1787         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1788         struct debug_store *ds = cpuc->ds;
1789         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1790         struct pebs_record_core *at, *top;
1791         int n;
1792
1793         if (!x86_pmu.pebs_active)
1794                 return;
1795
1796         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1797         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1798
1799         /*
1800          * Whatever else happens, drain the thing
1801          */
1802         ds->pebs_index = ds->pebs_buffer_base;
1803
1804         if (!test_bit(0, cpuc->active_mask))
1805                 return;
1806
1807         WARN_ON_ONCE(!event);
1808
1809         if (!event->attr.precise_ip)
1810                 return;
1811
1812         n = top - at;
1813         if (n <= 0) {
1814                 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1815                         intel_pmu_save_and_restart_reload(event, 0);
1816                 return;
1817         }
1818
1819         __intel_pmu_pebs_event(event, iregs, at, top, 0, n,
1820                                setup_pebs_fixed_sample_data);
1821 }
1822
1823 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
1824 {
1825         struct perf_event *event;
1826         int bit;
1827
1828         /*
1829          * The drain_pebs() could be called twice in a short period
1830          * for auto-reload event in pmu::read(). There are no
1831          * overflows have happened in between.
1832          * It needs to call intel_pmu_save_and_restart_reload() to
1833          * update the event->count for this case.
1834          */
1835         for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
1836                 event = cpuc->events[bit];
1837                 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1838                         intel_pmu_save_and_restart_reload(event, 0);
1839         }
1840 }
1841
1842 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1843 {
1844         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1845         struct debug_store *ds = cpuc->ds;
1846         struct perf_event *event;
1847         void *base, *at, *top;
1848         short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1849         short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1850         int bit, i, size;
1851         u64 mask;
1852
1853         if (!x86_pmu.pebs_active)
1854                 return;
1855
1856         base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1857         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1858
1859         ds->pebs_index = ds->pebs_buffer_base;
1860
1861         mask = (1ULL << x86_pmu.max_pebs_events) - 1;
1862         size = x86_pmu.max_pebs_events;
1863         if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
1864                 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
1865                 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
1866         }
1867
1868         if (unlikely(base >= top)) {
1869                 intel_pmu_pebs_event_update_no_drain(cpuc, size);
1870                 return;
1871         }
1872
1873         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1874                 struct pebs_record_nhm *p = at;
1875                 u64 pebs_status;
1876
1877                 pebs_status = p->status & cpuc->pebs_enabled;
1878                 pebs_status &= mask;
1879
1880                 /* PEBS v3 has more accurate status bits */
1881                 if (x86_pmu.intel_cap.pebs_format >= 3) {
1882                         for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
1883                                 counts[bit]++;
1884
1885                         continue;
1886                 }
1887
1888                 /*
1889                  * On some CPUs the PEBS status can be zero when PEBS is
1890                  * racing with clearing of GLOBAL_STATUS.
1891                  *
1892                  * Normally we would drop that record, but in the
1893                  * case when there is only a single active PEBS event
1894                  * we can assume it's for that event.
1895                  */
1896                 if (!pebs_status && cpuc->pebs_enabled &&
1897                         !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1898                         pebs_status = p->status = cpuc->pebs_enabled;
1899
1900                 bit = find_first_bit((unsigned long *)&pebs_status,
1901                                         x86_pmu.max_pebs_events);
1902                 if (bit >= x86_pmu.max_pebs_events)
1903                         continue;
1904
1905                 /*
1906                  * The PEBS hardware does not deal well with the situation
1907                  * when events happen near to each other and multiple bits
1908                  * are set. But it should happen rarely.
1909                  *
1910                  * If these events include one PEBS and multiple non-PEBS
1911                  * events, it doesn't impact PEBS record. The record will
1912                  * be handled normally. (slow path)
1913                  *
1914                  * If these events include two or more PEBS events, the
1915                  * records for the events can be collapsed into a single
1916                  * one, and it's not possible to reconstruct all events
1917                  * that caused the PEBS record. It's called collision.
1918                  * If collision happened, the record will be dropped.
1919                  */
1920                 if (pebs_status != (1ULL << bit)) {
1921                         for_each_set_bit(i, (unsigned long *)&pebs_status, size)
1922                                 error[i]++;
1923                         continue;
1924                 }
1925
1926                 counts[bit]++;
1927         }
1928
1929         for_each_set_bit(bit, (unsigned long *)&mask, size) {
1930                 if ((counts[bit] == 0) && (error[bit] == 0))
1931                         continue;
1932
1933                 event = cpuc->events[bit];
1934                 if (WARN_ON_ONCE(!event))
1935                         continue;
1936
1937                 if (WARN_ON_ONCE(!event->attr.precise_ip))
1938                         continue;
1939
1940                 /* log dropped samples number */
1941                 if (error[bit]) {
1942                         perf_log_lost_samples(event, error[bit]);
1943
1944                         if (perf_event_account_interrupt(event))
1945                                 x86_pmu_stop(event, 0);
1946                 }
1947
1948                 if (counts[bit]) {
1949                         __intel_pmu_pebs_event(event, iregs, base,
1950                                                top, bit, counts[bit],
1951                                                setup_pebs_fixed_sample_data);
1952                 }
1953         }
1954 }
1955
1956 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs)
1957 {
1958         short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1959         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1960         struct debug_store *ds = cpuc->ds;
1961         struct perf_event *event;
1962         void *base, *at, *top;
1963         int bit, size;
1964         u64 mask;
1965
1966         if (!x86_pmu.pebs_active)
1967                 return;
1968
1969         base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
1970         top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
1971
1972         ds->pebs_index = ds->pebs_buffer_base;
1973
1974         mask = ((1ULL << x86_pmu.max_pebs_events) - 1) |
1975                (((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
1976         size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
1977
1978         if (unlikely(base >= top)) {
1979                 intel_pmu_pebs_event_update_no_drain(cpuc, size);
1980                 return;
1981         }
1982
1983         for (at = base; at < top; at += cpuc->pebs_record_size) {
1984                 u64 pebs_status;
1985
1986                 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
1987                 pebs_status &= mask;
1988
1989                 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
1990                         counts[bit]++;
1991         }
1992
1993         for_each_set_bit(bit, (unsigned long *)&mask, size) {
1994                 if (counts[bit] == 0)
1995                         continue;
1996
1997                 event = cpuc->events[bit];
1998                 if (WARN_ON_ONCE(!event))
1999                         continue;
2000
2001                 if (WARN_ON_ONCE(!event->attr.precise_ip))
2002                         continue;
2003
2004                 __intel_pmu_pebs_event(event, iregs, base,
2005                                        top, bit, counts[bit],
2006                                        setup_pebs_adaptive_sample_data);
2007         }
2008 }
2009
2010 /*
2011  * BTS, PEBS probe and setup
2012  */
2013
2014 void __init intel_ds_init(void)
2015 {
2016         /*
2017          * No support for 32bit formats
2018          */
2019         if (!boot_cpu_has(X86_FEATURE_DTES64))
2020                 return;
2021
2022         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
2023         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2024         x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2025         if (x86_pmu.version <= 4)
2026                 x86_pmu.pebs_no_isolation = 1;
2027
2028         if (x86_pmu.pebs) {
2029                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
2030                 char *pebs_qual = "";
2031                 int format = x86_pmu.intel_cap.pebs_format;
2032
2033                 if (format < 4)
2034                         x86_pmu.intel_cap.pebs_baseline = 0;
2035
2036                 switch (format) {
2037                 case 0:
2038                         pr_cont("PEBS fmt0%c, ", pebs_type);
2039                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2040                         /*
2041                          * Using >PAGE_SIZE buffers makes the WRMSR to
2042                          * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2043                          * mysteriously hang on Core2.
2044                          *
2045                          * As a workaround, we don't do this.
2046                          */
2047                         x86_pmu.pebs_buffer_size = PAGE_SIZE;
2048                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2049                         break;
2050
2051                 case 1:
2052                         pr_cont("PEBS fmt1%c, ", pebs_type);
2053                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2054                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2055                         break;
2056
2057                 case 2:
2058                         pr_cont("PEBS fmt2%c, ", pebs_type);
2059                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2060                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2061                         break;
2062
2063                 case 3:
2064                         pr_cont("PEBS fmt3%c, ", pebs_type);
2065                         x86_pmu.pebs_record_size =
2066                                                 sizeof(struct pebs_record_skl);
2067                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2068                         x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2069                         break;
2070
2071                 case 4:
2072                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2073                         x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2074                         if (x86_pmu.intel_cap.pebs_baseline) {
2075                                 x86_pmu.large_pebs_flags |=
2076                                         PERF_SAMPLE_BRANCH_STACK |
2077                                         PERF_SAMPLE_TIME;
2078                                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
2079                                 pebs_qual = "-baseline";
2080                                 x86_get_pmu()->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2081                         } else {
2082                                 /* Only basic record supported */
2083                                 x86_pmu.large_pebs_flags &=
2084                                         ~(PERF_SAMPLE_ADDR |
2085                                           PERF_SAMPLE_TIME |
2086                                           PERF_SAMPLE_DATA_SRC |
2087                                           PERF_SAMPLE_TRANSACTION |
2088                                           PERF_SAMPLE_REGS_USER |
2089                                           PERF_SAMPLE_REGS_INTR);
2090                         }
2091                         pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2092
2093                         if (x86_pmu.intel_cap.pebs_output_pt_available) {
2094                                 pr_cont("PEBS-via-PT, ");
2095                                 x86_get_pmu()->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2096                         }
2097
2098                         break;
2099
2100                 default:
2101                         pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2102                         x86_pmu.pebs = 0;
2103                 }
2104         }
2105 }
2106
2107 void perf_restore_debug_store(void)
2108 {
2109         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2110
2111         if (!x86_pmu.bts && !x86_pmu.pebs)
2112                 return;
2113
2114         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2115 }