arch/x86/events/intel/cstate.c

   1 /*
   2  * Support cstate residency counters
   3  *
   4  * Copyright (C) 2015, Intel Corp.
   5  * Author: Kan Liang (kan.liang@intel.com)
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Library General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Library General Public License for more details.
  16  *
  17  */
  18
  19 /*
  20  * This file export cstate related free running (read-only) counters
  21  * for perf. These counters may be use simultaneously by other tools,
  22  * such as turbostat. However, it still make sense to implement them
  23  * in perf. Because we can conveniently collect them together with
  24  * other events, and allow to use them from tools without special MSR
  25  * access code.
  26  *
  27  * The events only support system-wide mode counting. There is no
  28  * sampling support because it is not supported by the hardware.
  29  *
  30  * According to counters' scope and category, two PMUs are registered
  31  * with the perf_event core subsystem.
  32  *  - 'cstate_core': The counter is available for each physical core.
  33  *    The counters include CORE_C*_RESIDENCY.
  34  *  - 'cstate_pkg': The counter is available for each physical package.
  35  *    The counters include PKG_C*_RESIDENCY.
  36  *
  37  * All of these counters are specified in the Intel® 64 and IA-32
  38  * Architectures Software Developer.s Manual Vol3b.
  39  *
  40  * Model specific counters:
  41  *      MSR_CORE_C1_RES: CORE C1 Residency Counter
  42  *                       perf code: 0x00
  43  *                       Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
  44  *                                        MTL
  45  *                       Scope: Core (each processor core has a MSR)
  46  *      MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  47  *                             perf code: 0x01
  48  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
  49  *                                              CNL,KBL,CML,TNT
  50  *                             Scope: Core
  51  *      MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  52  *                             perf code: 0x02
  53  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  54  *                                              SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  55  *                                              TGL,TNT,RKL,ADL,RPL,SPR,MTL
  56  *                             Scope: Core
  57  *      MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  58  *                             perf code: 0x03
  59  *                             Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
  60  *                                              ICL,TGL,RKL,ADL,RPL,MTL
  61  *                             Scope: Core
  62  *      MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  63  *                             perf code: 0x00
  64  *                             Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
  65  *                                              KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
  66  *                                              RPL,SPR,MTL
  67  *                             Scope: Package (physical package)
  68  *      MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  69  *                             perf code: 0x01
  70  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
  71  *                                              GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
  72  *                                              ADL,RPL,MTL
  73  *                             Scope: Package (physical package)
  74  *      MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  75  *                             perf code: 0x02
  76  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  77  *                                              SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  78  *                                              TGL,TNT,RKL,ADL,RPL,SPR,MTL
  79  *                             Scope: Package (physical package)
  80  *      MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  81  *                             perf code: 0x03
  82  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
  83  *                                              KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL
  84  *                             Scope: Package (physical package)
  85  *      MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  86  *                             perf code: 0x04
  87  *                             Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
  88  *                                              ADL,RPL,MTL
  89  *                             Scope: Package (physical package)
  90  *      MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  91  *                             perf code: 0x05
  92  *                             Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
  93  *                                              ADL,RPL,MTL
  94  *                             Scope: Package (physical package)
  95  *      MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  96  *                             perf code: 0x06
  97  *                             Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
  98  *                                              TNT,RKL,ADL,RPL,MTL
  99  *                             Scope: Package (physical package)
 100  *
 101  */
 102
 103 #include <linux/module.h>
 104 #include <linux/slab.h>
 105 #include <linux/perf_event.h>
 106 #include <linux/nospec.h>
 107 #include <asm/cpu_device_id.h>
 108 #include <asm/intel-family.h>
 109 #include "../perf_event.h"
 110 #include "../probe.h"
 111
 112 MODULE_LICENSE("GPL");
 113
 114 #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format)         \
 115 static ssize_t __cstate_##_var##_show(struct device *dev,       \
 116                                 struct device_attribute *attr,  \
 117                                 char *page)                     \
 118 {                                                               \
 119         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);             \
 120         return sprintf(page, _format "\n");                     \
 121 }                                                               \
 122 static struct device_attribute format_attr_##_var =             \
 123         __ATTR(_name, 0444, __cstate_##_var##_show, NULL)
 124
 125 static ssize_t cstate_get_attr_cpumask(struct device *dev,
 126                                        struct device_attribute *attr,
 127                                        char *buf);
 128
 129 /* Model -> events mapping */
 130 struct cstate_model {
 131         unsigned long           core_events;
 132         unsigned long           pkg_events;
 133         unsigned long           quirks;
 134 };
 135
 136 /* Quirk flags */
 137 #define SLM_PKG_C6_USE_C7_MSR   (1UL << 0)
 138 #define KNL_CORE_C6_MSR         (1UL << 1)
 139
 140 struct perf_cstate_msr {
 141         u64     msr;
 142         struct  perf_pmu_events_attr *attr;
 143 };
 144
 145
 146 /* cstate_core PMU */
 147 static struct pmu cstate_core_pmu;
 148 static bool has_cstate_core;
 149
 150 enum perf_cstate_core_events {
 151         PERF_CSTATE_CORE_C1_RES = 0,
 152         PERF_CSTATE_CORE_C3_RES,
 153         PERF_CSTATE_CORE_C6_RES,
 154         PERF_CSTATE_CORE_C7_RES,
 155
 156         PERF_CSTATE_CORE_EVENT_MAX,
 157 };
 158
 159 PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00");
 160 PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01");
 161 PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02");
 162 PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_core_c7, "event=0x03");
 163
 164 static unsigned long core_msr_mask;
 165
 166 PMU_EVENT_GROUP(events, cstate_core_c1);
 167 PMU_EVENT_GROUP(events, cstate_core_c3);
 168 PMU_EVENT_GROUP(events, cstate_core_c6);
 169 PMU_EVENT_GROUP(events, cstate_core_c7);
 170
 171 static bool test_msr(int idx, void *data)
 172 {
 173         return test_bit(idx, (unsigned long *) data);
 174 }
 175
 176 static struct perf_msr core_msr[] = {
 177         [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES,          &group_cstate_core_c1,  test_msr },
 178         [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY,    &group_cstate_core_c3,  test_msr },
 179         [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY,    &group_cstate_core_c6,  test_msr },
 180         [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY,    &group_cstate_core_c7,  test_msr },
 181 };
 182
 183 static struct attribute *attrs_empty[] = {
 184         NULL,
 185 };
 186
 187 /*
 188  * There are no default events, but we need to create
 189  * "events" group (with empty attrs) before updating
 190  * it with detected events.
 191  */
 192 static struct attribute_group core_events_attr_group = {
 193         .name = "events",
 194         .attrs = attrs_empty,
 195 };
 196
 197 DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63");
 198 static struct attribute *core_format_attrs[] = {
 199         &format_attr_core_event.attr,
 200         NULL,
 201 };
 202
 203 static struct attribute_group core_format_attr_group = {
 204         .name = "format",
 205         .attrs = core_format_attrs,
 206 };
 207
 208 static cpumask_t cstate_core_cpu_mask;
 209 static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL);
 210
 211 static struct attribute *cstate_cpumask_attrs[] = {
 212         &dev_attr_cpumask.attr,
 213         NULL,
 214 };
 215
 216 static struct attribute_group cpumask_attr_group = {
 217         .attrs = cstate_cpumask_attrs,
 218 };
 219
 220 static const struct attribute_group *core_attr_groups[] = {
 221         &core_events_attr_group,
 222         &core_format_attr_group,
 223         &cpumask_attr_group,
 224         NULL,
 225 };
 226
 227 /* cstate_pkg PMU */
 228 static struct pmu cstate_pkg_pmu;
 229 static bool has_cstate_pkg;
 230
 231 enum perf_cstate_pkg_events {
 232         PERF_CSTATE_PKG_C2_RES = 0,
 233         PERF_CSTATE_PKG_C3_RES,
 234         PERF_CSTATE_PKG_C6_RES,
 235         PERF_CSTATE_PKG_C7_RES,
 236         PERF_CSTATE_PKG_C8_RES,
 237         PERF_CSTATE_PKG_C9_RES,
 238         PERF_CSTATE_PKG_C10_RES,
 239
 240         PERF_CSTATE_PKG_EVENT_MAX,
 241 };
 242
 243 PMU_EVENT_ATTR_STRING(c2-residency,  attr_cstate_pkg_c2,  "event=0x00");
 244 PMU_EVENT_ATTR_STRING(c3-residency,  attr_cstate_pkg_c3,  "event=0x01");
 245 PMU_EVENT_ATTR_STRING(c6-residency,  attr_cstate_pkg_c6,  "event=0x02");
 246 PMU_EVENT_ATTR_STRING(c7-residency,  attr_cstate_pkg_c7,  "event=0x03");
 247 PMU_EVENT_ATTR_STRING(c8-residency,  attr_cstate_pkg_c8,  "event=0x04");
 248 PMU_EVENT_ATTR_STRING(c9-residency,  attr_cstate_pkg_c9,  "event=0x05");
 249 PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06");
 250
 251 static unsigned long pkg_msr_mask;
 252
 253 PMU_EVENT_GROUP(events, cstate_pkg_c2);
 254 PMU_EVENT_GROUP(events, cstate_pkg_c3);
 255 PMU_EVENT_GROUP(events, cstate_pkg_c6);
 256 PMU_EVENT_GROUP(events, cstate_pkg_c7);
 257 PMU_EVENT_GROUP(events, cstate_pkg_c8);
 258 PMU_EVENT_GROUP(events, cstate_pkg_c9);
 259 PMU_EVENT_GROUP(events, cstate_pkg_c10);
 260
 261 static struct perf_msr pkg_msr[] = {
 262         [PERF_CSTATE_PKG_C2_RES]  = { MSR_PKG_C2_RESIDENCY,     &group_cstate_pkg_c2,   test_msr },
 263         [PERF_CSTATE_PKG_C3_RES]  = { MSR_PKG_C3_RESIDENCY,     &group_cstate_pkg_c3,   test_msr },
 264         [PERF_CSTATE_PKG_C6_RES]  = { MSR_PKG_C6_RESIDENCY,     &group_cstate_pkg_c6,   test_msr },
 265         [PERF_CSTATE_PKG_C7_RES]  = { MSR_PKG_C7_RESIDENCY,     &group_cstate_pkg_c7,   test_msr },
 266         [PERF_CSTATE_PKG_C8_RES]  = { MSR_PKG_C8_RESIDENCY,     &group_cstate_pkg_c8,   test_msr },
 267         [PERF_CSTATE_PKG_C9_RES]  = { MSR_PKG_C9_RESIDENCY,     &group_cstate_pkg_c9,   test_msr },
 268         [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY,    &group_cstate_pkg_c10,  test_msr },
 269 };
 270
 271 static struct attribute_group pkg_events_attr_group = {
 272         .name = "events",
 273         .attrs = attrs_empty,
 274 };
 275
 276 DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63");
 277 static struct attribute *pkg_format_attrs[] = {
 278         &format_attr_pkg_event.attr,
 279         NULL,
 280 };
 281 static struct attribute_group pkg_format_attr_group = {
 282         .name = "format",
 283         .attrs = pkg_format_attrs,
 284 };
 285
 286 static cpumask_t cstate_pkg_cpu_mask;
 287
 288 static const struct attribute_group *pkg_attr_groups[] = {
 289         &pkg_events_attr_group,
 290         &pkg_format_attr_group,
 291         &cpumask_attr_group,
 292         NULL,
 293 };
 294
 295 static ssize_t cstate_get_attr_cpumask(struct device *dev,
 296                                        struct device_attribute *attr,
 297                                        char *buf)
 298 {
 299         struct pmu *pmu = dev_get_drvdata(dev);
 300
 301         if (pmu == &cstate_core_pmu)
 302                 return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask);
 303         else if (pmu == &cstate_pkg_pmu)
 304                 return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask);
 305         else
 306                 return 0;
 307 }
 308
 309 static int cstate_pmu_event_init(struct perf_event *event)
 310 {
 311         u64 cfg = event->attr.config;
 312         int cpu;
 313
 314         if (event->attr.type != event->pmu->type)
 315                 return -ENOENT;
 316
 317         /* unsupported modes and filters */
 318         if (event->attr.sample_period) /* no sampling */
 319                 return -EINVAL;
 320
 321         if (event->cpu < 0)
 322                 return -EINVAL;
 323
 324         if (event->pmu == &cstate_core_pmu) {
 325                 if (cfg >= PERF_CSTATE_CORE_EVENT_MAX)
 326                         return -EINVAL;
 327                 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_CORE_EVENT_MAX);
 328                 if (!(core_msr_mask & (1 << cfg)))
 329                         return -EINVAL;
 330                 event->hw.event_base = core_msr[cfg].msr;
 331                 cpu = cpumask_any_and(&cstate_core_cpu_mask,
 332                                       topology_sibling_cpumask(event->cpu));
 333         } else if (event->pmu == &cstate_pkg_pmu) {
 334                 if (cfg >= PERF_CSTATE_PKG_EVENT_MAX)
 335                         return -EINVAL;
 336                 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX);
 337                 if (!(pkg_msr_mask & (1 << cfg)))
 338                         return -EINVAL;
 339
 340                 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
 341
 342                 event->hw.event_base = pkg_msr[cfg].msr;
 343                 cpu = cpumask_any_and(&cstate_pkg_cpu_mask,
 344                                       topology_die_cpumask(event->cpu));
 345         } else {
 346                 return -ENOENT;
 347         }
 348
 349         if (cpu >= nr_cpu_ids)
 350                 return -ENODEV;
 351
 352         event->cpu = cpu;
 353         event->hw.config = cfg;
 354         event->hw.idx = -1;
 355         return 0;
 356 }
 357
 358 static inline u64 cstate_pmu_read_counter(struct perf_event *event)
 359 {
 360         u64 val;
 361
 362         rdmsrl(event->hw.event_base, val);
 363         return val;
 364 }
 365
 366 static void cstate_pmu_event_update(struct perf_event *event)
 367 {
 368         struct hw_perf_event *hwc = &event->hw;
 369         u64 prev_raw_count, new_raw_count;
 370
 371         prev_raw_count = local64_read(&hwc->prev_count);
 372         do {
 373                 new_raw_count = cstate_pmu_read_counter(event);
 374         } while (!local64_try_cmpxchg(&hwc->prev_count,
 375                                       &prev_raw_count, new_raw_count));
 376
 377         local64_add(new_raw_count - prev_raw_count, &event->count);
 378 }
 379
 380 static void cstate_pmu_event_start(struct perf_event *event, int mode)
 381 {
 382         local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event));
 383 }
 384
 385 static void cstate_pmu_event_stop(struct perf_event *event, int mode)
 386 {
 387         cstate_pmu_event_update(event);
 388 }
 389
 390 static void cstate_pmu_event_del(struct perf_event *event, int mode)
 391 {
 392         cstate_pmu_event_stop(event, PERF_EF_UPDATE);
 393 }
 394
 395 static int cstate_pmu_event_add(struct perf_event *event, int mode)
 396 {
 397         if (mode & PERF_EF_START)
 398                 cstate_pmu_event_start(event, mode);
 399
 400         return 0;
 401 }
 402
 403 /*
 404  * Check if exiting cpu is the designated reader. If so migrate the
 405  * events when there is a valid target available
 406  */
 407 static int cstate_cpu_exit(unsigned int cpu)
 408 {
 409         unsigned int target;
 410
 411         if (has_cstate_core &&
 412             cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) {
 413
 414                 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
 415                 /* Migrate events if there is a valid target */
 416                 if (target < nr_cpu_ids) {
 417                         cpumask_set_cpu(target, &cstate_core_cpu_mask);
 418                         perf_pmu_migrate_context(&cstate_core_pmu, cpu, target);
 419                 }
 420         }
 421
 422         if (has_cstate_pkg &&
 423             cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) {
 424
 425                 target = cpumask_any_but(topology_die_cpumask(cpu), cpu);
 426                 /* Migrate events if there is a valid target */
 427                 if (target < nr_cpu_ids) {
 428                         cpumask_set_cpu(target, &cstate_pkg_cpu_mask);
 429                         perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target);
 430                 }
 431         }
 432         return 0;
 433 }
 434
 435 static int cstate_cpu_init(unsigned int cpu)
 436 {
 437         unsigned int target;
 438
 439         /*
 440          * If this is the first online thread of that core, set it in
 441          * the core cpu mask as the designated reader.
 442          */
 443         target = cpumask_any_and(&cstate_core_cpu_mask,
 444                                  topology_sibling_cpumask(cpu));
 445
 446         if (has_cstate_core && target >= nr_cpu_ids)
 447                 cpumask_set_cpu(cpu, &cstate_core_cpu_mask);
 448
 449         /*
 450          * If this is the first online thread of that package, set it
 451          * in the package cpu mask as the designated reader.
 452          */
 453         target = cpumask_any_and(&cstate_pkg_cpu_mask,
 454                                  topology_die_cpumask(cpu));
 455         if (has_cstate_pkg && target >= nr_cpu_ids)
 456                 cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask);
 457
 458         return 0;
 459 }
 460
 461 static const struct attribute_group *core_attr_update[] = {
 462         &group_cstate_core_c1,
 463         &group_cstate_core_c3,
 464         &group_cstate_core_c6,
 465         &group_cstate_core_c7,
 466         NULL,
 467 };
 468
 469 static const struct attribute_group *pkg_attr_update[] = {
 470         &group_cstate_pkg_c2,
 471         &group_cstate_pkg_c3,
 472         &group_cstate_pkg_c6,
 473         &group_cstate_pkg_c7,
 474         &group_cstate_pkg_c8,
 475         &group_cstate_pkg_c9,
 476         &group_cstate_pkg_c10,
 477         NULL,
 478 };
 479
 480 static struct pmu cstate_core_pmu = {
 481         .attr_groups    = core_attr_groups,
 482         .attr_update    = core_attr_update,
 483         .name           = "cstate_core",
 484         .task_ctx_nr    = perf_invalid_context,
 485         .event_init     = cstate_pmu_event_init,
 486         .add            = cstate_pmu_event_add,
 487         .del            = cstate_pmu_event_del,
 488         .start          = cstate_pmu_event_start,
 489         .stop           = cstate_pmu_event_stop,
 490         .read           = cstate_pmu_event_update,
 491         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 492         .module         = THIS_MODULE,
 493 };
 494
 495 static struct pmu cstate_pkg_pmu = {
 496         .attr_groups    = pkg_attr_groups,
 497         .attr_update    = pkg_attr_update,
 498         .name           = "cstate_pkg",
 499         .task_ctx_nr    = perf_invalid_context,
 500         .event_init     = cstate_pmu_event_init,
 501         .add            = cstate_pmu_event_add,
 502         .del            = cstate_pmu_event_del,
 503         .start          = cstate_pmu_event_start,
 504         .stop           = cstate_pmu_event_stop,
 505         .read           = cstate_pmu_event_update,
 506         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 507         .module         = THIS_MODULE,
 508 };
 509
 510 static const struct cstate_model nhm_cstates __initconst = {
 511         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 512                                   BIT(PERF_CSTATE_CORE_C6_RES),
 513
 514         .pkg_events             = BIT(PERF_CSTATE_PKG_C3_RES) |
 515                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 516                                   BIT(PERF_CSTATE_PKG_C7_RES),
 517 };
 518
 519 static const struct cstate_model snb_cstates __initconst = {
 520         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 521                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 522                                   BIT(PERF_CSTATE_CORE_C7_RES),
 523
 524         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 525                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 526                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 527                                   BIT(PERF_CSTATE_PKG_C7_RES),
 528 };
 529
 530 static const struct cstate_model hswult_cstates __initconst = {
 531         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 532                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 533                                   BIT(PERF_CSTATE_CORE_C7_RES),
 534
 535         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 536                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 537                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 538                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 539                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 540                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 541                                   BIT(PERF_CSTATE_PKG_C10_RES),
 542 };
 543
 544 static const struct cstate_model cnl_cstates __initconst = {
 545         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 546                                   BIT(PERF_CSTATE_CORE_C3_RES) |
 547                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 548                                   BIT(PERF_CSTATE_CORE_C7_RES),
 549
 550         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 551                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 552                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 553                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 554                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 555                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 556                                   BIT(PERF_CSTATE_PKG_C10_RES),
 557 };
 558
 559 static const struct cstate_model icl_cstates __initconst = {
 560         .core_events            = BIT(PERF_CSTATE_CORE_C6_RES) |
 561                                   BIT(PERF_CSTATE_CORE_C7_RES),
 562
 563         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 564                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 565                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 566                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 567                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 568                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 569                                   BIT(PERF_CSTATE_PKG_C10_RES),
 570 };
 571
 572 static const struct cstate_model icx_cstates __initconst = {
 573         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 574                                   BIT(PERF_CSTATE_CORE_C6_RES),
 575
 576         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 577                                   BIT(PERF_CSTATE_PKG_C6_RES),
 578 };
 579
 580 static const struct cstate_model adl_cstates __initconst = {
 581         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 582                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 583                                   BIT(PERF_CSTATE_CORE_C7_RES),
 584
 585         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 586                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 587                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 588                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 589                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 590                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 591                                   BIT(PERF_CSTATE_PKG_C10_RES),
 592 };
 593
 594 static const struct cstate_model slm_cstates __initconst = {
 595         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 596                                   BIT(PERF_CSTATE_CORE_C6_RES),
 597
 598         .pkg_events             = BIT(PERF_CSTATE_PKG_C6_RES),
 599         .quirks                 = SLM_PKG_C6_USE_C7_MSR,
 600 };
 601
 602
 603 static const struct cstate_model knl_cstates __initconst = {
 604         .core_events            = BIT(PERF_CSTATE_CORE_C6_RES),
 605
 606         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 607                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 608                                   BIT(PERF_CSTATE_PKG_C6_RES),
 609         .quirks                 = KNL_CORE_C6_MSR,
 610 };
 611
 612
 613 static const struct cstate_model glm_cstates __initconst = {
 614         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 615                                   BIT(PERF_CSTATE_CORE_C3_RES) |
 616                                   BIT(PERF_CSTATE_CORE_C6_RES),
 617
 618         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 619                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 620                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 621                                   BIT(PERF_CSTATE_PKG_C10_RES),
 622 };
 623
 624
 625 static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 626         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,             &nhm_cstates),
 627         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,          &nhm_cstates),
 628         X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX,          &nhm_cstates),
 629
 630         X86_MATCH_INTEL_FAM6_MODEL(WESTMERE,            &nhm_cstates),
 631         X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP,         &nhm_cstates),
 632         X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX,         &nhm_cstates),
 633
 634         X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,         &snb_cstates),
 635         X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,       &snb_cstates),
 636
 637         X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,           &snb_cstates),
 638         X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X,         &snb_cstates),
 639
 640         X86_MATCH_INTEL_FAM6_MODEL(HASWELL,             &snb_cstates),
 641         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X,           &snb_cstates),
 642         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G,           &snb_cstates),
 643
 644         X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L,           &hswult_cstates),
 645
 646         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,     &slm_cstates),
 647         X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,   &slm_cstates),
 648         X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,        &slm_cstates),
 649
 650         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL,           &snb_cstates),
 651         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D,         &snb_cstates),
 652         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G,         &snb_cstates),
 653         X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X,         &snb_cstates),
 654
 655         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,           &snb_cstates),
 656         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,             &snb_cstates),
 657         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X,           &snb_cstates),
 658
 659         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,          &hswult_cstates),
 660         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,            &hswult_cstates),
 661         X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,         &hswult_cstates),
 662         X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,           &hswult_cstates),
 663
 664         X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,        &cnl_cstates),
 665
 666         X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,        &knl_cstates),
 667         X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,        &knl_cstates),
 668
 669         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,       &glm_cstates),
 670         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,     &glm_cstates),
 671         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,  &glm_cstates),
 672         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      &glm_cstates),
 673         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        &glm_cstates),
 674         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      &glm_cstates),
 675         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &adl_cstates),
 676
 677         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           &icl_cstates),
 678         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,             &icl_cstates),
 679         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,           &icx_cstates),
 680         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           &icx_cstates),
 681         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &icx_cstates),
 682         X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &icx_cstates),
 683         X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X,     &icx_cstates),
 684         X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_D,     &icx_cstates),
 685
 686         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,         &icl_cstates),
 687         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           &icl_cstates),
 688         X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &icl_cstates),
 689         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &adl_cstates),
 690         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &adl_cstates),
 691         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &adl_cstates),
 692         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &adl_cstates),
 693         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &adl_cstates),
 694         X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE,          &adl_cstates),
 695         X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L,        &adl_cstates),
 696         { },
 697 };
 698 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
 699
 700 static int __init cstate_probe(const struct cstate_model *cm)
 701 {
 702         /* SLM has different MSR for PKG C6 */
 703         if (cm->quirks & SLM_PKG_C6_USE_C7_MSR)
 704                 pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY;
 705
 706         /* KNL has different MSR for CORE C6 */
 707         if (cm->quirks & KNL_CORE_C6_MSR)
 708                 pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY;
 709
 710
 711         core_msr_mask = perf_msr_probe(core_msr, PERF_CSTATE_CORE_EVENT_MAX,
 712                                        true, (void *) &cm->core_events);
 713
 714         pkg_msr_mask = perf_msr_probe(pkg_msr, PERF_CSTATE_PKG_EVENT_MAX,
 715                                       true, (void *) &cm->pkg_events);
 716
 717         has_cstate_core = !!core_msr_mask;
 718         has_cstate_pkg  = !!pkg_msr_mask;
 719
 720         return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV;
 721 }
 722
 723 static inline void cstate_cleanup(void)
 724 {
 725         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE);
 726         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING);
 727
 728         if (has_cstate_core)
 729                 perf_pmu_unregister(&cstate_core_pmu);
 730
 731         if (has_cstate_pkg)
 732                 perf_pmu_unregister(&cstate_pkg_pmu);
 733 }
 734
 735 static int __init cstate_init(void)
 736 {
 737         int err;
 738
 739         cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING,
 740                           "perf/x86/cstate:starting", cstate_cpu_init, NULL);
 741         cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE,
 742                           "perf/x86/cstate:online", NULL, cstate_cpu_exit);
 743
 744         if (has_cstate_core) {
 745                 err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1);
 746                 if (err) {
 747                         has_cstate_core = false;
 748                         pr_info("Failed to register cstate core pmu\n");
 749                         cstate_cleanup();
 750                         return err;
 751                 }
 752         }
 753
 754         if (has_cstate_pkg) {
 755                 if (topology_max_die_per_package() > 1) {
 756                         err = perf_pmu_register(&cstate_pkg_pmu,
 757                                                 "cstate_die", -1);
 758                 } else {
 759                         err = perf_pmu_register(&cstate_pkg_pmu,
 760                                                 cstate_pkg_pmu.name, -1);
 761                 }
 762                 if (err) {
 763                         has_cstate_pkg = false;
 764                         pr_info("Failed to register cstate pkg pmu\n");
 765                         cstate_cleanup();
 766                         return err;
 767                 }
 768         }
 769         return 0;
 770 }
 771
 772 static int __init cstate_pmu_init(void)
 773 {
 774         const struct x86_cpu_id *id;
 775         int err;
 776
 777         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 778                 return -ENODEV;
 779
 780         id = x86_match_cpu(intel_cstates_match);
 781         if (!id)
 782                 return -ENODEV;
 783
 784         err = cstate_probe((const struct cstate_model *) id->driver_data);
 785         if (err)
 786                 return err;
 787
 788         return cstate_init();
 789 }
 790 module_init(cstate_pmu_init);
 791
 792 static void __exit cstate_pmu_exit(void)
 793 {
 794         cstate_cleanup();
 795 }
 796 module_exit(cstate_pmu_exit);