arch/x86/events/intel/core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Per core/cpu state
   4  *
   5  * Used to coordinate shared registers between HT threads or
   6  * among events on a single PMU.
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/stddef.h>
  12 #include <linux/types.h>
  13 #include <linux/init.h>
  14 #include <linux/slab.h>
  15 #include <linux/export.h>
  16 #include <linux/nmi.h>
  17
  18 #include <asm/cpufeature.h>
  19 #include <asm/hardirq.h>
  20 #include <asm/intel-family.h>
  21 #include <asm/intel_pt.h>
  22 #include <asm/apic.h>
  23 #include <asm/cpu_device_id.h>
  24
  25 #include "../perf_event.h"
  26
  27 /*
  28  * Intel PerfMon, used on Core and later.
  29  */
  30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  31 {
  32         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  33         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  34         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  35         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  36         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  37         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  38         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  39         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  40 };
  41
  42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  43 {
  44         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  45         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  46         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  47         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  48         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  49         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  50         EVENT_CONSTRAINT_END
  51 };
  52
  53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  54 {
  55         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  56         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  57         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  58         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  59         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  60         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  61         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  62         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  63         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  64         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  65         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  66         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  67         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  68         EVENT_CONSTRAINT_END
  69 };
  70
  71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  72 {
  73         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  74         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  75         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  76         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  77         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  78         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  79         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  80         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  81         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  82         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  83         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  84         EVENT_CONSTRAINT_END
  85 };
  86
  87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  88 {
  89         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  90         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  91         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  92         EVENT_EXTRA_END
  93 };
  94
  95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  96 {
  97         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  98         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  99         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 100         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
 101         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
 102         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
 103         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 104         EVENT_CONSTRAINT_END
 105 };
 106
 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 108 {
 109         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 110         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 111         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 112         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 113         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 114         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 115         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 116         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 117         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 118         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 119         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 120         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 121
 122         /*
 123          * When HT is off these events can only run on the bottom 4 counters
 124          * When HT is on, they are impacted by the HT bug and require EXCL access
 125          */
 126         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 127         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 128         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 129         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 130
 131         EVENT_CONSTRAINT_END
 132 };
 133
 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 135 {
 136         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 137         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 138         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 139         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 140         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
 141         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 142         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 143         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 144         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 145         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 146         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 147         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 148         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 149
 150         /*
 151          * When HT is off these events can only run on the bottom 4 counters
 152          * When HT is on, they are impacted by the HT bug and require EXCL access
 153          */
 154         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 155         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 156         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 157         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 158
 159         EVENT_CONSTRAINT_END
 160 };
 161
 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 163 {
 164         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 165         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 166         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 167         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 168         EVENT_EXTRA_END
 169 };
 170
 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 172 {
 173         EVENT_CONSTRAINT_END
 174 };
 175
 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 177 {
 178         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 179         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 180         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 181         EVENT_CONSTRAINT_END
 182 };
 183
 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 185 {
 186         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 187         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 188         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 189         EVENT_CONSTRAINT_END
 190 };
 191
 192 static struct event_constraint intel_skl_event_constraints[] = {
 193         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 194         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 195         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 196         INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),    /* INST_RETIRED.PREC_DIST */
 197
 198         /*
 199          * when HT is off, these can only run on the bottom 4 counters
 200          */
 201         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 202         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 203         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 204         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 205         INTEL_EVENT_CONSTRAINT(0xc6, 0xf),      /* FRONTEND_RETIRED.* */
 206
 207         EVENT_CONSTRAINT_END
 208 };
 209
 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
 211         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
 212         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 213         EVENT_EXTRA_END
 214 };
 215
 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 217         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 218         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 219         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 220         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 221         EVENT_EXTRA_END
 222 };
 223
 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 225         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 226         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 227         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 228         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 229         EVENT_EXTRA_END
 230 };
 231
 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 233         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 234         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 235         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 236         /*
 237          * Note the low 8 bits eventsel code is not a continuous field, containing
 238          * some #GPing bits. These are masked out.
 239          */
 240         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 241         EVENT_EXTRA_END
 242 };
 243
 244 static struct event_constraint intel_icl_event_constraints[] = {
 245         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 246         FIXED_EVENT_CONSTRAINT(0x01c0, 0),      /* old INST_RETIRED.PREC_DIST */
 247         FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* INST_RETIRED.PREC_DIST */
 248         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 249         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 250         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 251         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 252         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 253         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 254         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 255         INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
 256         INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
 257         INTEL_EVENT_CONSTRAINT(0x32, 0xf),      /* SW_PREFETCH_ACCESS.* */
 258         INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
 259         INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
 260         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_TOTAL */
 261         INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff),  /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
 262         INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
 263         INTEL_EVENT_CONSTRAINT(0xa3, 0xf),      /* CYCLE_ACTIVITY.* */
 264         INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
 265         INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
 266         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
 267         INTEL_EVENT_CONSTRAINT(0xef, 0xf),
 268         INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
 269         EVENT_CONSTRAINT_END
 270 };
 271
 272 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
 273         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
 274         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 275         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 276         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 277         EVENT_EXTRA_END
 278 };
 279
 280 static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
 281         INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
 282         INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
 283         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 284         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
 285         INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
 286         INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
 287         EVENT_EXTRA_END
 288 };
 289
 290 static struct event_constraint intel_spr_event_constraints[] = {
 291         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 292         FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* INST_RETIRED.PREC_DIST */
 293         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 294         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 295         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 296         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 297         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 298         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 299         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 300         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
 301         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
 302         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
 303         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
 304
 305         INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
 306         INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
 307         /*
 308          * Generally event codes < 0x90 are restricted to counters 0-3.
 309          * The 0x2E and 0x3C are exception, which has no restriction.
 310          */
 311         INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
 312
 313         INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
 314         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
 315         INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
 316         INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
 317         INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
 318         INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
 319         INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 320         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
 321         /*
 322          * Generally event codes >= 0x90 are likely to have no restrictions.
 323          * The exception are defined as above.
 324          */
 325         INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
 326
 327         EVENT_CONSTRAINT_END
 328 };
 329
 330
 331 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 332 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 333 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 334
 335 static struct attribute *nhm_mem_events_attrs[] = {
 336         EVENT_PTR(mem_ld_nhm),
 337         NULL,
 338 };
 339
 340 /*
 341  * topdown events for Intel Core CPUs.
 342  *
 343  * The events are all in slots, which is a free slot in a 4 wide
 344  * pipeline. Some events are already reported in slots, for cycle
 345  * events we multiply by the pipeline width (4).
 346  *
 347  * With Hyper Threading on, topdown metrics are either summed or averaged
 348  * between the threads of a core: (count_t0 + count_t1).
 349  *
 350  * For the average case the metric is always scaled to pipeline width,
 351  * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
 352  */
 353
 354 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
 355         "event=0x3c,umask=0x0",                 /* cpu_clk_unhalted.thread */
 356         "event=0x3c,umask=0x0,any=1");          /* cpu_clk_unhalted.thread_any */
 357 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
 358 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
 359         "event=0xe,umask=0x1");                 /* uops_issued.any */
 360 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
 361         "event=0xc2,umask=0x2");                /* uops_retired.retire_slots */
 362 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
 363         "event=0x9c,umask=0x1");                /* idq_uops_not_delivered_core */
 364 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
 365         "event=0xd,umask=0x3,cmask=1",          /* int_misc.recovery_cycles */
 366         "event=0xd,umask=0x3,cmask=1,any=1");   /* int_misc.recovery_cycles_any */
 367 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
 368         "4", "2");
 369
 370 EVENT_ATTR_STR(slots,                   slots,                  "event=0x00,umask=0x4");
 371 EVENT_ATTR_STR(topdown-retiring,        td_retiring,            "event=0x00,umask=0x80");
 372 EVENT_ATTR_STR(topdown-bad-spec,        td_bad_spec,            "event=0x00,umask=0x81");
 373 EVENT_ATTR_STR(topdown-fe-bound,        td_fe_bound,            "event=0x00,umask=0x82");
 374 EVENT_ATTR_STR(topdown-be-bound,        td_be_bound,            "event=0x00,umask=0x83");
 375 EVENT_ATTR_STR(topdown-heavy-ops,       td_heavy_ops,           "event=0x00,umask=0x84");
 376 EVENT_ATTR_STR(topdown-br-mispredict,   td_br_mispredict,       "event=0x00,umask=0x85");
 377 EVENT_ATTR_STR(topdown-fetch-lat,       td_fetch_lat,           "event=0x00,umask=0x86");
 378 EVENT_ATTR_STR(topdown-mem-bound,       td_mem_bound,           "event=0x00,umask=0x87");
 379
 380 static struct attribute *snb_events_attrs[] = {
 381         EVENT_PTR(td_slots_issued),
 382         EVENT_PTR(td_slots_retired),
 383         EVENT_PTR(td_fetch_bubbles),
 384         EVENT_PTR(td_total_slots),
 385         EVENT_PTR(td_total_slots_scale),
 386         EVENT_PTR(td_recovery_bubbles),
 387         EVENT_PTR(td_recovery_bubbles_scale),
 388         NULL,
 389 };
 390
 391 static struct attribute *snb_mem_events_attrs[] = {
 392         EVENT_PTR(mem_ld_snb),
 393         EVENT_PTR(mem_st_snb),
 394         NULL,
 395 };
 396
 397 static struct event_constraint intel_hsw_event_constraints[] = {
 398         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 399         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 400         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 401         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 402         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 403         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 404         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 405         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 406         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 407         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 408         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 409         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 410
 411         /*
 412          * When HT is off these events can only run on the bottom 4 counters
 413          * When HT is on, they are impacted by the HT bug and require EXCL access
 414          */
 415         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 416         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 417         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 418         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 419
 420         EVENT_CONSTRAINT_END
 421 };
 422
 423 static struct event_constraint intel_bdw_event_constraints[] = {
 424         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 425         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 426         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 427         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 428         INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),        /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
 429         /*
 430          * when HT is off, these can only run on the bottom 4 counters
 431          */
 432         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 433         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 434         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 435         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 436         EVENT_CONSTRAINT_END
 437 };
 438
 439 static u64 intel_pmu_event_map(int hw_event)
 440 {
 441         return intel_perfmon_event_map[hw_event];
 442 }
 443
 444 static __initconst const u64 spr_hw_cache_event_ids
 445                                 [PERF_COUNT_HW_CACHE_MAX]
 446                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 447                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 448 {
 449  [ C(L1D ) ] = {
 450         [ C(OP_READ) ] = {
 451                 [ C(RESULT_ACCESS) ] = 0x81d0,
 452                 [ C(RESULT_MISS)   ] = 0xe124,
 453         },
 454         [ C(OP_WRITE) ] = {
 455                 [ C(RESULT_ACCESS) ] = 0x82d0,
 456         },
 457  },
 458  [ C(L1I ) ] = {
 459         [ C(OP_READ) ] = {
 460                 [ C(RESULT_MISS)   ] = 0xe424,
 461         },
 462         [ C(OP_WRITE) ] = {
 463                 [ C(RESULT_ACCESS) ] = -1,
 464                 [ C(RESULT_MISS)   ] = -1,
 465         },
 466  },
 467  [ C(LL  ) ] = {
 468         [ C(OP_READ) ] = {
 469                 [ C(RESULT_ACCESS) ] = 0x12a,
 470                 [ C(RESULT_MISS)   ] = 0x12a,
 471         },
 472         [ C(OP_WRITE) ] = {
 473                 [ C(RESULT_ACCESS) ] = 0x12a,
 474                 [ C(RESULT_MISS)   ] = 0x12a,
 475         },
 476  },
 477  [ C(DTLB) ] = {
 478         [ C(OP_READ) ] = {
 479                 [ C(RESULT_ACCESS) ] = 0x81d0,
 480                 [ C(RESULT_MISS)   ] = 0xe12,
 481         },
 482         [ C(OP_WRITE) ] = {
 483                 [ C(RESULT_ACCESS) ] = 0x82d0,
 484                 [ C(RESULT_MISS)   ] = 0xe13,
 485         },
 486  },
 487  [ C(ITLB) ] = {
 488         [ C(OP_READ) ] = {
 489                 [ C(RESULT_ACCESS) ] = -1,
 490                 [ C(RESULT_MISS)   ] = 0xe11,
 491         },
 492         [ C(OP_WRITE) ] = {
 493                 [ C(RESULT_ACCESS) ] = -1,
 494                 [ C(RESULT_MISS)   ] = -1,
 495         },
 496         [ C(OP_PREFETCH) ] = {
 497                 [ C(RESULT_ACCESS) ] = -1,
 498                 [ C(RESULT_MISS)   ] = -1,
 499         },
 500  },
 501  [ C(BPU ) ] = {
 502         [ C(OP_READ) ] = {
 503                 [ C(RESULT_ACCESS) ] = 0x4c4,
 504                 [ C(RESULT_MISS)   ] = 0x4c5,
 505         },
 506         [ C(OP_WRITE) ] = {
 507                 [ C(RESULT_ACCESS) ] = -1,
 508                 [ C(RESULT_MISS)   ] = -1,
 509         },
 510         [ C(OP_PREFETCH) ] = {
 511                 [ C(RESULT_ACCESS) ] = -1,
 512                 [ C(RESULT_MISS)   ] = -1,
 513         },
 514  },
 515  [ C(NODE) ] = {
 516         [ C(OP_READ) ] = {
 517                 [ C(RESULT_ACCESS) ] = 0x12a,
 518                 [ C(RESULT_MISS)   ] = 0x12a,
 519         },
 520  },
 521 };
 522
 523 static __initconst const u64 spr_hw_cache_extra_regs
 524                                 [PERF_COUNT_HW_CACHE_MAX]
 525                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 526                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 527 {
 528  [ C(LL  ) ] = {
 529         [ C(OP_READ) ] = {
 530                 [ C(RESULT_ACCESS) ] = 0x10001,
 531                 [ C(RESULT_MISS)   ] = 0x3fbfc00001,
 532         },
 533         [ C(OP_WRITE) ] = {
 534                 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
 535                 [ C(RESULT_MISS)   ] = 0x3f3fc00002,
 536         },
 537  },
 538  [ C(NODE) ] = {
 539         [ C(OP_READ) ] = {
 540                 [ C(RESULT_ACCESS) ] = 0x10c000001,
 541                 [ C(RESULT_MISS)   ] = 0x3fb3000001,
 542         },
 543  },
 544 };
 545
 546 /*
 547  * Notes on the events:
 548  * - data reads do not include code reads (comparable to earlier tables)
 549  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 550  * - remote node access includes remote memory, remote cache, remote mmio.
 551  * - prefetches are not included in the counts.
 552  * - icache miss does not include decoded icache
 553  */
 554
 555 #define SKL_DEMAND_DATA_RD              BIT_ULL(0)
 556 #define SKL_DEMAND_RFO                  BIT_ULL(1)
 557 #define SKL_ANY_RESPONSE                BIT_ULL(16)
 558 #define SKL_SUPPLIER_NONE               BIT_ULL(17)
 559 #define SKL_L3_MISS_LOCAL_DRAM          BIT_ULL(26)
 560 #define SKL_L3_MISS_REMOTE_HOP0_DRAM    BIT_ULL(27)
 561 #define SKL_L3_MISS_REMOTE_HOP1_DRAM    BIT_ULL(28)
 562 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM   BIT_ULL(29)
 563 #define SKL_L3_MISS                     (SKL_L3_MISS_LOCAL_DRAM| \
 564                                          SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 565                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 566                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 567 #define SKL_SPL_HIT                     BIT_ULL(30)
 568 #define SKL_SNOOP_NONE                  BIT_ULL(31)
 569 #define SKL_SNOOP_NOT_NEEDED            BIT_ULL(32)
 570 #define SKL_SNOOP_MISS                  BIT_ULL(33)
 571 #define SKL_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 572 #define SKL_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 573 #define SKL_SNOOP_HITM                  BIT_ULL(36)
 574 #define SKL_SNOOP_NON_DRAM              BIT_ULL(37)
 575 #define SKL_ANY_SNOOP                   (SKL_SPL_HIT|SKL_SNOOP_NONE| \
 576                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 577                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 578                                          SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
 579 #define SKL_DEMAND_READ                 SKL_DEMAND_DATA_RD
 580 #define SKL_SNOOP_DRAM                  (SKL_SNOOP_NONE| \
 581                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 582                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 583                                          SKL_SNOOP_HITM|SKL_SPL_HIT)
 584 #define SKL_DEMAND_WRITE                SKL_DEMAND_RFO
 585 #define SKL_LLC_ACCESS                  SKL_ANY_RESPONSE
 586 #define SKL_L3_MISS_REMOTE              (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 587                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 588                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 589
 590 static __initconst const u64 skl_hw_cache_event_ids
 591                                 [PERF_COUNT_HW_CACHE_MAX]
 592                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 593                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 594 {
 595  [ C(L1D ) ] = {
 596         [ C(OP_READ) ] = {
 597                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 598                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 599         },
 600         [ C(OP_WRITE) ] = {
 601                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 602                 [ C(RESULT_MISS)   ] = 0x0,
 603         },
 604         [ C(OP_PREFETCH) ] = {
 605                 [ C(RESULT_ACCESS) ] = 0x0,
 606                 [ C(RESULT_MISS)   ] = 0x0,
 607         },
 608  },
 609  [ C(L1I ) ] = {
 610         [ C(OP_READ) ] = {
 611                 [ C(RESULT_ACCESS) ] = 0x0,
 612                 [ C(RESULT_MISS)   ] = 0x283,   /* ICACHE_64B.MISS */
 613         },
 614         [ C(OP_WRITE) ] = {
 615                 [ C(RESULT_ACCESS) ] = -1,
 616                 [ C(RESULT_MISS)   ] = -1,
 617         },
 618         [ C(OP_PREFETCH) ] = {
 619                 [ C(RESULT_ACCESS) ] = 0x0,
 620                 [ C(RESULT_MISS)   ] = 0x0,
 621         },
 622  },
 623  [ C(LL  ) ] = {
 624         [ C(OP_READ) ] = {
 625                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 626                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 627         },
 628         [ C(OP_WRITE) ] = {
 629                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 630                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 631         },
 632         [ C(OP_PREFETCH) ] = {
 633                 [ C(RESULT_ACCESS) ] = 0x0,
 634                 [ C(RESULT_MISS)   ] = 0x0,
 635         },
 636  },
 637  [ C(DTLB) ] = {
 638         [ C(OP_READ) ] = {
 639                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 640                 [ C(RESULT_MISS)   ] = 0xe08,   /* DTLB_LOAD_MISSES.WALK_COMPLETED */
 641         },
 642         [ C(OP_WRITE) ] = {
 643                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 644                 [ C(RESULT_MISS)   ] = 0xe49,   /* DTLB_STORE_MISSES.WALK_COMPLETED */
 645         },
 646         [ C(OP_PREFETCH) ] = {
 647                 [ C(RESULT_ACCESS) ] = 0x0,
 648                 [ C(RESULT_MISS)   ] = 0x0,
 649         },
 650  },
 651  [ C(ITLB) ] = {
 652         [ C(OP_READ) ] = {
 653                 [ C(RESULT_ACCESS) ] = 0x2085,  /* ITLB_MISSES.STLB_HIT */
 654                 [ C(RESULT_MISS)   ] = 0xe85,   /* ITLB_MISSES.WALK_COMPLETED */
 655         },
 656         [ C(OP_WRITE) ] = {
 657                 [ C(RESULT_ACCESS) ] = -1,
 658                 [ C(RESULT_MISS)   ] = -1,
 659         },
 660         [ C(OP_PREFETCH) ] = {
 661                 [ C(RESULT_ACCESS) ] = -1,
 662                 [ C(RESULT_MISS)   ] = -1,
 663         },
 664  },
 665  [ C(BPU ) ] = {
 666         [ C(OP_READ) ] = {
 667                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 668                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 669         },
 670         [ C(OP_WRITE) ] = {
 671                 [ C(RESULT_ACCESS) ] = -1,
 672                 [ C(RESULT_MISS)   ] = -1,
 673         },
 674         [ C(OP_PREFETCH) ] = {
 675                 [ C(RESULT_ACCESS) ] = -1,
 676                 [ C(RESULT_MISS)   ] = -1,
 677         },
 678  },
 679  [ C(NODE) ] = {
 680         [ C(OP_READ) ] = {
 681                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 682                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 683         },
 684         [ C(OP_WRITE) ] = {
 685                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 686                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 687         },
 688         [ C(OP_PREFETCH) ] = {
 689                 [ C(RESULT_ACCESS) ] = 0x0,
 690                 [ C(RESULT_MISS)   ] = 0x0,
 691         },
 692  },
 693 };
 694
 695 static __initconst const u64 skl_hw_cache_extra_regs
 696                                 [PERF_COUNT_HW_CACHE_MAX]
 697                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 698                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 699 {
 700  [ C(LL  ) ] = {
 701         [ C(OP_READ) ] = {
 702                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 703                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 704                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 705                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 706                                        SKL_SUPPLIER_NONE,
 707         },
 708         [ C(OP_WRITE) ] = {
 709                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 710                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 711                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 712                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 713                                        SKL_SUPPLIER_NONE,
 714         },
 715         [ C(OP_PREFETCH) ] = {
 716                 [ C(RESULT_ACCESS) ] = 0x0,
 717                 [ C(RESULT_MISS)   ] = 0x0,
 718         },
 719  },
 720  [ C(NODE) ] = {
 721         [ C(OP_READ) ] = {
 722                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 723                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 724                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 725                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 726         },
 727         [ C(OP_WRITE) ] = {
 728                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 729                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 730                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 731                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 732         },
 733         [ C(OP_PREFETCH) ] = {
 734                 [ C(RESULT_ACCESS) ] = 0x0,
 735                 [ C(RESULT_MISS)   ] = 0x0,
 736         },
 737  },
 738 };
 739
 740 #define SNB_DMND_DATA_RD        (1ULL << 0)
 741 #define SNB_DMND_RFO            (1ULL << 1)
 742 #define SNB_DMND_IFETCH         (1ULL << 2)
 743 #define SNB_DMND_WB             (1ULL << 3)
 744 #define SNB_PF_DATA_RD          (1ULL << 4)
 745 #define SNB_PF_RFO              (1ULL << 5)
 746 #define SNB_PF_IFETCH           (1ULL << 6)
 747 #define SNB_LLC_DATA_RD         (1ULL << 7)
 748 #define SNB_LLC_RFO             (1ULL << 8)
 749 #define SNB_LLC_IFETCH          (1ULL << 9)
 750 #define SNB_BUS_LOCKS           (1ULL << 10)
 751 #define SNB_STRM_ST             (1ULL << 11)
 752 #define SNB_OTHER               (1ULL << 15)
 753 #define SNB_RESP_ANY            (1ULL << 16)
 754 #define SNB_NO_SUPP             (1ULL << 17)
 755 #define SNB_LLC_HITM            (1ULL << 18)
 756 #define SNB_LLC_HITE            (1ULL << 19)
 757 #define SNB_LLC_HITS            (1ULL << 20)
 758 #define SNB_LLC_HITF            (1ULL << 21)
 759 #define SNB_LOCAL               (1ULL << 22)
 760 #define SNB_REMOTE              (0xffULL << 23)
 761 #define SNB_SNP_NONE            (1ULL << 31)
 762 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 763 #define SNB_SNP_MISS            (1ULL << 33)
 764 #define SNB_NO_FWD              (1ULL << 34)
 765 #define SNB_SNP_FWD             (1ULL << 35)
 766 #define SNB_HITM                (1ULL << 36)
 767 #define SNB_NON_DRAM            (1ULL << 37)
 768
 769 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 770 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 771 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 772
 773 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 774                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 775                                  SNB_HITM)
 776
 777 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 778 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 779
 780 #define SNB_L3_ACCESS           SNB_RESP_ANY
 781 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 782
 783 static __initconst const u64 snb_hw_cache_extra_regs
 784                                 [PERF_COUNT_HW_CACHE_MAX]
 785                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 786                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 787 {
 788  [ C(LL  ) ] = {
 789         [ C(OP_READ) ] = {
 790                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 791                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 792         },
 793         [ C(OP_WRITE) ] = {
 794                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 795                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 796         },
 797         [ C(OP_PREFETCH) ] = {
 798                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 799                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 800         },
 801  },
 802  [ C(NODE) ] = {
 803         [ C(OP_READ) ] = {
 804                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 805                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 806         },
 807         [ C(OP_WRITE) ] = {
 808                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 809                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 810         },
 811         [ C(OP_PREFETCH) ] = {
 812                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 813                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 814         },
 815  },
 816 };
 817
 818 static __initconst const u64 snb_hw_cache_event_ids
 819                                 [PERF_COUNT_HW_CACHE_MAX]
 820                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 821                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 822 {
 823  [ C(L1D) ] = {
 824         [ C(OP_READ) ] = {
 825                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 826                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 827         },
 828         [ C(OP_WRITE) ] = {
 829                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 830                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 831         },
 832         [ C(OP_PREFETCH) ] = {
 833                 [ C(RESULT_ACCESS) ] = 0x0,
 834                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 835         },
 836  },
 837  [ C(L1I ) ] = {
 838         [ C(OP_READ) ] = {
 839                 [ C(RESULT_ACCESS) ] = 0x0,
 840                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 841         },
 842         [ C(OP_WRITE) ] = {
 843                 [ C(RESULT_ACCESS) ] = -1,
 844                 [ C(RESULT_MISS)   ] = -1,
 845         },
 846         [ C(OP_PREFETCH) ] = {
 847                 [ C(RESULT_ACCESS) ] = 0x0,
 848                 [ C(RESULT_MISS)   ] = 0x0,
 849         },
 850  },
 851  [ C(LL  ) ] = {
 852         [ C(OP_READ) ] = {
 853                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 854                 [ C(RESULT_ACCESS) ] = 0x01b7,
 855                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 856                 [ C(RESULT_MISS)   ] = 0x01b7,
 857         },
 858         [ C(OP_WRITE) ] = {
 859                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 860                 [ C(RESULT_ACCESS) ] = 0x01b7,
 861                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 862                 [ C(RESULT_MISS)   ] = 0x01b7,
 863         },
 864         [ C(OP_PREFETCH) ] = {
 865                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 866                 [ C(RESULT_ACCESS) ] = 0x01b7,
 867                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 868                 [ C(RESULT_MISS)   ] = 0x01b7,
 869         },
 870  },
 871  [ C(DTLB) ] = {
 872         [ C(OP_READ) ] = {
 873                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 874                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 875         },
 876         [ C(OP_WRITE) ] = {
 877                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 878                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 879         },
 880         [ C(OP_PREFETCH) ] = {
 881                 [ C(RESULT_ACCESS) ] = 0x0,
 882                 [ C(RESULT_MISS)   ] = 0x0,
 883         },
 884  },
 885  [ C(ITLB) ] = {
 886         [ C(OP_READ) ] = {
 887                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 888                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 889         },
 890         [ C(OP_WRITE) ] = {
 891                 [ C(RESULT_ACCESS) ] = -1,
 892                 [ C(RESULT_MISS)   ] = -1,
 893         },
 894         [ C(OP_PREFETCH) ] = {
 895                 [ C(RESULT_ACCESS) ] = -1,
 896                 [ C(RESULT_MISS)   ] = -1,
 897         },
 898  },
 899  [ C(BPU ) ] = {
 900         [ C(OP_READ) ] = {
 901                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 902                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 903         },
 904         [ C(OP_WRITE) ] = {
 905                 [ C(RESULT_ACCESS) ] = -1,
 906                 [ C(RESULT_MISS)   ] = -1,
 907         },
 908         [ C(OP_PREFETCH) ] = {
 909                 [ C(RESULT_ACCESS) ] = -1,
 910                 [ C(RESULT_MISS)   ] = -1,
 911         },
 912  },
 913  [ C(NODE) ] = {
 914         [ C(OP_READ) ] = {
 915                 [ C(RESULT_ACCESS) ] = 0x01b7,
 916                 [ C(RESULT_MISS)   ] = 0x01b7,
 917         },
 918         [ C(OP_WRITE) ] = {
 919                 [ C(RESULT_ACCESS) ] = 0x01b7,
 920                 [ C(RESULT_MISS)   ] = 0x01b7,
 921         },
 922         [ C(OP_PREFETCH) ] = {
 923                 [ C(RESULT_ACCESS) ] = 0x01b7,
 924                 [ C(RESULT_MISS)   ] = 0x01b7,
 925         },
 926  },
 927
 928 };
 929
 930 /*
 931  * Notes on the events:
 932  * - data reads do not include code reads (comparable to earlier tables)
 933  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 934  * - remote node access includes remote memory, remote cache, remote mmio.
 935  * - prefetches are not included in the counts because they are not
 936  *   reliably counted.
 937  */
 938
 939 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 940 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 941 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 942 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 943 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 944 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 945 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 946 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 947 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 948                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 949                                          HSW_L3_MISS_REMOTE_HOP2P)
 950 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 951 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 952 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 953 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 954 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 955 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 956 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 957 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 958                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 959                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 960                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 961 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 962 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 963 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 964 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 965                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 966 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 967
 968 #define BDW_L3_MISS_LOCAL               BIT(26)
 969 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 970                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 971                                          HSW_L3_MISS_REMOTE_HOP2P)
 972
 973
 974 static __initconst const u64 hsw_hw_cache_event_ids
 975                                 [PERF_COUNT_HW_CACHE_MAX]
 976                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 977                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 978 {
 979  [ C(L1D ) ] = {
 980         [ C(OP_READ) ] = {
 981                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 982                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 983         },
 984         [ C(OP_WRITE) ] = {
 985                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 986                 [ C(RESULT_MISS)   ] = 0x0,
 987         },
 988         [ C(OP_PREFETCH) ] = {
 989                 [ C(RESULT_ACCESS) ] = 0x0,
 990                 [ C(RESULT_MISS)   ] = 0x0,
 991         },
 992  },
 993  [ C(L1I ) ] = {
 994         [ C(OP_READ) ] = {
 995                 [ C(RESULT_ACCESS) ] = 0x0,
 996                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 997         },
 998         [ C(OP_WRITE) ] = {
 999                 [ C(RESULT_ACCESS) ] = -1,
1000                 [ C(RESULT_MISS)   ] = -1,
1001         },
1002         [ C(OP_PREFETCH) ] = {
1003                 [ C(RESULT_ACCESS) ] = 0x0,
1004                 [ C(RESULT_MISS)   ] = 0x0,
1005         },
1006  },
1007  [ C(LL  ) ] = {
1008         [ C(OP_READ) ] = {
1009                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1010                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1011         },
1012         [ C(OP_WRITE) ] = {
1013                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1014                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1015         },
1016         [ C(OP_PREFETCH) ] = {
1017                 [ C(RESULT_ACCESS) ] = 0x0,
1018                 [ C(RESULT_MISS)   ] = 0x0,
1019         },
1020  },
1021  [ C(DTLB) ] = {
1022         [ C(OP_READ) ] = {
1023                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
1024                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1025         },
1026         [ C(OP_WRITE) ] = {
1027                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
1028                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1029         },
1030         [ C(OP_PREFETCH) ] = {
1031                 [ C(RESULT_ACCESS) ] = 0x0,
1032                 [ C(RESULT_MISS)   ] = 0x0,
1033         },
1034  },
1035  [ C(ITLB) ] = {
1036         [ C(OP_READ) ] = {
1037                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
1038                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1039         },
1040         [ C(OP_WRITE) ] = {
1041                 [ C(RESULT_ACCESS) ] = -1,
1042                 [ C(RESULT_MISS)   ] = -1,
1043         },
1044         [ C(OP_PREFETCH) ] = {
1045                 [ C(RESULT_ACCESS) ] = -1,
1046                 [ C(RESULT_MISS)   ] = -1,
1047         },
1048  },
1049  [ C(BPU ) ] = {
1050         [ C(OP_READ) ] = {
1051                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
1052                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
1053         },
1054         [ C(OP_WRITE) ] = {
1055                 [ C(RESULT_ACCESS) ] = -1,
1056                 [ C(RESULT_MISS)   ] = -1,
1057         },
1058         [ C(OP_PREFETCH) ] = {
1059                 [ C(RESULT_ACCESS) ] = -1,
1060                 [ C(RESULT_MISS)   ] = -1,
1061         },
1062  },
1063  [ C(NODE) ] = {
1064         [ C(OP_READ) ] = {
1065                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1066                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1067         },
1068         [ C(OP_WRITE) ] = {
1069                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1070                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1071         },
1072         [ C(OP_PREFETCH) ] = {
1073                 [ C(RESULT_ACCESS) ] = 0x0,
1074                 [ C(RESULT_MISS)   ] = 0x0,
1075         },
1076  },
1077 };
1078
1079 static __initconst const u64 hsw_hw_cache_extra_regs
1080                                 [PERF_COUNT_HW_CACHE_MAX]
1081                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1082                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1083 {
1084  [ C(LL  ) ] = {
1085         [ C(OP_READ) ] = {
1086                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1087                                        HSW_LLC_ACCESS,
1088                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1089                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1090         },
1091         [ C(OP_WRITE) ] = {
1092                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1093                                        HSW_LLC_ACCESS,
1094                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1095                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1096         },
1097         [ C(OP_PREFETCH) ] = {
1098                 [ C(RESULT_ACCESS) ] = 0x0,
1099                 [ C(RESULT_MISS)   ] = 0x0,
1100         },
1101  },
1102  [ C(NODE) ] = {
1103         [ C(OP_READ) ] = {
1104                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1105                                        HSW_L3_MISS_LOCAL_DRAM|
1106                                        HSW_SNOOP_DRAM,
1107                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1108                                        HSW_L3_MISS_REMOTE|
1109                                        HSW_SNOOP_DRAM,
1110         },
1111         [ C(OP_WRITE) ] = {
1112                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1113                                        HSW_L3_MISS_LOCAL_DRAM|
1114                                        HSW_SNOOP_DRAM,
1115                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1116                                        HSW_L3_MISS_REMOTE|
1117                                        HSW_SNOOP_DRAM,
1118         },
1119         [ C(OP_PREFETCH) ] = {
1120                 [ C(RESULT_ACCESS) ] = 0x0,
1121                 [ C(RESULT_MISS)   ] = 0x0,
1122         },
1123  },
1124 };
1125
1126 static __initconst const u64 westmere_hw_cache_event_ids
1127                                 [PERF_COUNT_HW_CACHE_MAX]
1128                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1129                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1130 {
1131  [ C(L1D) ] = {
1132         [ C(OP_READ) ] = {
1133                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1134                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1135         },
1136         [ C(OP_WRITE) ] = {
1137                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1138                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1139         },
1140         [ C(OP_PREFETCH) ] = {
1141                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1142                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1143         },
1144  },
1145  [ C(L1I ) ] = {
1146         [ C(OP_READ) ] = {
1147                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1148                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1149         },
1150         [ C(OP_WRITE) ] = {
1151                 [ C(RESULT_ACCESS) ] = -1,
1152                 [ C(RESULT_MISS)   ] = -1,
1153         },
1154         [ C(OP_PREFETCH) ] = {
1155                 [ C(RESULT_ACCESS) ] = 0x0,
1156                 [ C(RESULT_MISS)   ] = 0x0,
1157         },
1158  },
1159  [ C(LL  ) ] = {
1160         [ C(OP_READ) ] = {
1161                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1162                 [ C(RESULT_ACCESS) ] = 0x01b7,
1163                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1164                 [ C(RESULT_MISS)   ] = 0x01b7,
1165         },
1166         /*
1167          * Use RFO, not WRITEBACK, because a write miss would typically occur
1168          * on RFO.
1169          */
1170         [ C(OP_WRITE) ] = {
1171                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1172                 [ C(RESULT_ACCESS) ] = 0x01b7,
1173                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1174                 [ C(RESULT_MISS)   ] = 0x01b7,
1175         },
1176         [ C(OP_PREFETCH) ] = {
1177                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1178                 [ C(RESULT_ACCESS) ] = 0x01b7,
1179                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1180                 [ C(RESULT_MISS)   ] = 0x01b7,
1181         },
1182  },
1183  [ C(DTLB) ] = {
1184         [ C(OP_READ) ] = {
1185                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1186                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1187         },
1188         [ C(OP_WRITE) ] = {
1189                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1190                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1191         },
1192         [ C(OP_PREFETCH) ] = {
1193                 [ C(RESULT_ACCESS) ] = 0x0,
1194                 [ C(RESULT_MISS)   ] = 0x0,
1195         },
1196  },
1197  [ C(ITLB) ] = {
1198         [ C(OP_READ) ] = {
1199                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1200                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
1201         },
1202         [ C(OP_WRITE) ] = {
1203                 [ C(RESULT_ACCESS) ] = -1,
1204                 [ C(RESULT_MISS)   ] = -1,
1205         },
1206         [ C(OP_PREFETCH) ] = {
1207                 [ C(RESULT_ACCESS) ] = -1,
1208                 [ C(RESULT_MISS)   ] = -1,
1209         },
1210  },
1211  [ C(BPU ) ] = {
1212         [ C(OP_READ) ] = {
1213                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1214                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1215         },
1216         [ C(OP_WRITE) ] = {
1217                 [ C(RESULT_ACCESS) ] = -1,
1218                 [ C(RESULT_MISS)   ] = -1,
1219         },
1220         [ C(OP_PREFETCH) ] = {
1221                 [ C(RESULT_ACCESS) ] = -1,
1222                 [ C(RESULT_MISS)   ] = -1,
1223         },
1224  },
1225  [ C(NODE) ] = {
1226         [ C(OP_READ) ] = {
1227                 [ C(RESULT_ACCESS) ] = 0x01b7,
1228                 [ C(RESULT_MISS)   ] = 0x01b7,
1229         },
1230         [ C(OP_WRITE) ] = {
1231                 [ C(RESULT_ACCESS) ] = 0x01b7,
1232                 [ C(RESULT_MISS)   ] = 0x01b7,
1233         },
1234         [ C(OP_PREFETCH) ] = {
1235                 [ C(RESULT_ACCESS) ] = 0x01b7,
1236                 [ C(RESULT_MISS)   ] = 0x01b7,
1237         },
1238  },
1239 };
1240
1241 /*
1242  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1243  * See IA32 SDM Vol 3B 30.6.1.3
1244  */
1245
1246 #define NHM_DMND_DATA_RD        (1 << 0)
1247 #define NHM_DMND_RFO            (1 << 1)
1248 #define NHM_DMND_IFETCH         (1 << 2)
1249 #define NHM_DMND_WB             (1 << 3)
1250 #define NHM_PF_DATA_RD          (1 << 4)
1251 #define NHM_PF_DATA_RFO         (1 << 5)
1252 #define NHM_PF_IFETCH           (1 << 6)
1253 #define NHM_OFFCORE_OTHER       (1 << 7)
1254 #define NHM_UNCORE_HIT          (1 << 8)
1255 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
1256 #define NHM_OTHER_CORE_HITM     (1 << 10)
1257                                 /* reserved */
1258 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
1259 #define NHM_REMOTE_DRAM         (1 << 13)
1260 #define NHM_LOCAL_DRAM          (1 << 14)
1261 #define NHM_NON_DRAM            (1 << 15)
1262
1263 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1264 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
1265
1266 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
1267 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
1268 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1269
1270 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1271 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1272 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
1273
1274 static __initconst const u64 nehalem_hw_cache_extra_regs
1275                                 [PERF_COUNT_HW_CACHE_MAX]
1276                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1277                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1278 {
1279  [ C(LL  ) ] = {
1280         [ C(OP_READ) ] = {
1281                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1282                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
1283         },
1284         [ C(OP_WRITE) ] = {
1285                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1286                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
1287         },
1288         [ C(OP_PREFETCH) ] = {
1289                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1290                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1291         },
1292  },
1293  [ C(NODE) ] = {
1294         [ C(OP_READ) ] = {
1295                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1296                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
1297         },
1298         [ C(OP_WRITE) ] = {
1299                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1300                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
1301         },
1302         [ C(OP_PREFETCH) ] = {
1303                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1304                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1305         },
1306  },
1307 };
1308
1309 static __initconst const u64 nehalem_hw_cache_event_ids
1310                                 [PERF_COUNT_HW_CACHE_MAX]
1311                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1312                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1313 {
1314  [ C(L1D) ] = {
1315         [ C(OP_READ) ] = {
1316                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1317                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1318         },
1319         [ C(OP_WRITE) ] = {
1320                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1321                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1322         },
1323         [ C(OP_PREFETCH) ] = {
1324                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1325                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1326         },
1327  },
1328  [ C(L1I ) ] = {
1329         [ C(OP_READ) ] = {
1330                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1331                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1332         },
1333         [ C(OP_WRITE) ] = {
1334                 [ C(RESULT_ACCESS) ] = -1,
1335                 [ C(RESULT_MISS)   ] = -1,
1336         },
1337         [ C(OP_PREFETCH) ] = {
1338                 [ C(RESULT_ACCESS) ] = 0x0,
1339                 [ C(RESULT_MISS)   ] = 0x0,
1340         },
1341  },
1342  [ C(LL  ) ] = {
1343         [ C(OP_READ) ] = {
1344                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1345                 [ C(RESULT_ACCESS) ] = 0x01b7,
1346                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1347                 [ C(RESULT_MISS)   ] = 0x01b7,
1348         },
1349         /*
1350          * Use RFO, not WRITEBACK, because a write miss would typically occur
1351          * on RFO.
1352          */
1353         [ C(OP_WRITE) ] = {
1354                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1355                 [ C(RESULT_ACCESS) ] = 0x01b7,
1356                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1357                 [ C(RESULT_MISS)   ] = 0x01b7,
1358         },
1359         [ C(OP_PREFETCH) ] = {
1360                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1361                 [ C(RESULT_ACCESS) ] = 0x01b7,
1362                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1363                 [ C(RESULT_MISS)   ] = 0x01b7,
1364         },
1365  },
1366  [ C(DTLB) ] = {
1367         [ C(OP_READ) ] = {
1368                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
1369                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1370         },
1371         [ C(OP_WRITE) ] = {
1372                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
1373                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1374         },
1375         [ C(OP_PREFETCH) ] = {
1376                 [ C(RESULT_ACCESS) ] = 0x0,
1377                 [ C(RESULT_MISS)   ] = 0x0,
1378         },
1379  },
1380  [ C(ITLB) ] = {
1381         [ C(OP_READ) ] = {
1382                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1383                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
1384         },
1385         [ C(OP_WRITE) ] = {
1386                 [ C(RESULT_ACCESS) ] = -1,
1387                 [ C(RESULT_MISS)   ] = -1,
1388         },
1389         [ C(OP_PREFETCH) ] = {
1390                 [ C(RESULT_ACCESS) ] = -1,
1391                 [ C(RESULT_MISS)   ] = -1,
1392         },
1393  },
1394  [ C(BPU ) ] = {
1395         [ C(OP_READ) ] = {
1396                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1397                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1398         },
1399         [ C(OP_WRITE) ] = {
1400                 [ C(RESULT_ACCESS) ] = -1,
1401                 [ C(RESULT_MISS)   ] = -1,
1402         },
1403         [ C(OP_PREFETCH) ] = {
1404                 [ C(RESULT_ACCESS) ] = -1,
1405                 [ C(RESULT_MISS)   ] = -1,
1406         },
1407  },
1408  [ C(NODE) ] = {
1409         [ C(OP_READ) ] = {
1410                 [ C(RESULT_ACCESS) ] = 0x01b7,
1411                 [ C(RESULT_MISS)   ] = 0x01b7,
1412         },
1413         [ C(OP_WRITE) ] = {
1414                 [ C(RESULT_ACCESS) ] = 0x01b7,
1415                 [ C(RESULT_MISS)   ] = 0x01b7,
1416         },
1417         [ C(OP_PREFETCH) ] = {
1418                 [ C(RESULT_ACCESS) ] = 0x01b7,
1419                 [ C(RESULT_MISS)   ] = 0x01b7,
1420         },
1421  },
1422 };
1423
1424 static __initconst const u64 core2_hw_cache_event_ids
1425                                 [PERF_COUNT_HW_CACHE_MAX]
1426                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1427                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1428 {
1429  [ C(L1D) ] = {
1430         [ C(OP_READ) ] = {
1431                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
1432                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
1433         },
1434         [ C(OP_WRITE) ] = {
1435                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
1436                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
1437         },
1438         [ C(OP_PREFETCH) ] = {
1439                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
1440                 [ C(RESULT_MISS)   ] = 0,
1441         },
1442  },
1443  [ C(L1I ) ] = {
1444         [ C(OP_READ) ] = {
1445                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
1446                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
1447         },
1448         [ C(OP_WRITE) ] = {
1449                 [ C(RESULT_ACCESS) ] = -1,
1450                 [ C(RESULT_MISS)   ] = -1,
1451         },
1452         [ C(OP_PREFETCH) ] = {
1453                 [ C(RESULT_ACCESS) ] = 0,
1454                 [ C(RESULT_MISS)   ] = 0,
1455         },
1456  },
1457  [ C(LL  ) ] = {
1458         [ C(OP_READ) ] = {
1459                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1460                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1461         },
1462         [ C(OP_WRITE) ] = {
1463                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1464                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1465         },
1466         [ C(OP_PREFETCH) ] = {
1467                 [ C(RESULT_ACCESS) ] = 0,
1468                 [ C(RESULT_MISS)   ] = 0,
1469         },
1470  },
1471  [ C(DTLB) ] = {
1472         [ C(OP_READ) ] = {
1473                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
1474                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
1475         },
1476         [ C(OP_WRITE) ] = {
1477                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
1478                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
1479         },
1480         [ C(OP_PREFETCH) ] = {
1481                 [ C(RESULT_ACCESS) ] = 0,
1482                 [ C(RESULT_MISS)   ] = 0,
1483         },
1484  },
1485  [ C(ITLB) ] = {
1486         [ C(OP_READ) ] = {
1487                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1488                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
1489         },
1490         [ C(OP_WRITE) ] = {
1491                 [ C(RESULT_ACCESS) ] = -1,
1492                 [ C(RESULT_MISS)   ] = -1,
1493         },
1494         [ C(OP_PREFETCH) ] = {
1495                 [ C(RESULT_ACCESS) ] = -1,
1496                 [ C(RESULT_MISS)   ] = -1,
1497         },
1498  },
1499  [ C(BPU ) ] = {
1500         [ C(OP_READ) ] = {
1501                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1502                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1503         },
1504         [ C(OP_WRITE) ] = {
1505                 [ C(RESULT_ACCESS) ] = -1,
1506                 [ C(RESULT_MISS)   ] = -1,
1507         },
1508         [ C(OP_PREFETCH) ] = {
1509                 [ C(RESULT_ACCESS) ] = -1,
1510                 [ C(RESULT_MISS)   ] = -1,
1511         },
1512  },
1513 };
1514
1515 static __initconst const u64 atom_hw_cache_event_ids
1516                                 [PERF_COUNT_HW_CACHE_MAX]
1517                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1518                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1519 {
1520  [ C(L1D) ] = {
1521         [ C(OP_READ) ] = {
1522                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1523                 [ C(RESULT_MISS)   ] = 0,
1524         },
1525         [ C(OP_WRITE) ] = {
1526                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1527                 [ C(RESULT_MISS)   ] = 0,
1528         },
1529         [ C(OP_PREFETCH) ] = {
1530                 [ C(RESULT_ACCESS) ] = 0x0,
1531                 [ C(RESULT_MISS)   ] = 0,
1532         },
1533  },
1534  [ C(L1I ) ] = {
1535         [ C(OP_READ) ] = {
1536                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1537                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1538         },
1539         [ C(OP_WRITE) ] = {
1540                 [ C(RESULT_ACCESS) ] = -1,
1541                 [ C(RESULT_MISS)   ] = -1,
1542         },
1543         [ C(OP_PREFETCH) ] = {
1544                 [ C(RESULT_ACCESS) ] = 0,
1545                 [ C(RESULT_MISS)   ] = 0,
1546         },
1547  },
1548  [ C(LL  ) ] = {
1549         [ C(OP_READ) ] = {
1550                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1551                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1552         },
1553         [ C(OP_WRITE) ] = {
1554                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1555                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1556         },
1557         [ C(OP_PREFETCH) ] = {
1558                 [ C(RESULT_ACCESS) ] = 0,
1559                 [ C(RESULT_MISS)   ] = 0,
1560         },
1561  },
1562  [ C(DTLB) ] = {
1563         [ C(OP_READ) ] = {
1564                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1565                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1566         },
1567         [ C(OP_WRITE) ] = {
1568                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1569                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1570         },
1571         [ C(OP_PREFETCH) ] = {
1572                 [ C(RESULT_ACCESS) ] = 0,
1573                 [ C(RESULT_MISS)   ] = 0,
1574         },
1575  },
1576  [ C(ITLB) ] = {
1577         [ C(OP_READ) ] = {
1578                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1579                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1580         },
1581         [ C(OP_WRITE) ] = {
1582                 [ C(RESULT_ACCESS) ] = -1,
1583                 [ C(RESULT_MISS)   ] = -1,
1584         },
1585         [ C(OP_PREFETCH) ] = {
1586                 [ C(RESULT_ACCESS) ] = -1,
1587                 [ C(RESULT_MISS)   ] = -1,
1588         },
1589  },
1590  [ C(BPU ) ] = {
1591         [ C(OP_READ) ] = {
1592                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1593                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1594         },
1595         [ C(OP_WRITE) ] = {
1596                 [ C(RESULT_ACCESS) ] = -1,
1597                 [ C(RESULT_MISS)   ] = -1,
1598         },
1599         [ C(OP_PREFETCH) ] = {
1600                 [ C(RESULT_ACCESS) ] = -1,
1601                 [ C(RESULT_MISS)   ] = -1,
1602         },
1603  },
1604 };
1605
1606 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1607 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1608 /* no_alloc_cycles.not_delivered */
1609 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1610                "event=0xca,umask=0x50");
1611 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1612 /* uops_retired.all */
1613 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1614                "event=0xc2,umask=0x10");
1615 /* uops_retired.all */
1616 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1617                "event=0xc2,umask=0x10");
1618
1619 static struct attribute *slm_events_attrs[] = {
1620         EVENT_PTR(td_total_slots_slm),
1621         EVENT_PTR(td_total_slots_scale_slm),
1622         EVENT_PTR(td_fetch_bubbles_slm),
1623         EVENT_PTR(td_fetch_bubbles_scale_slm),
1624         EVENT_PTR(td_slots_issued_slm),
1625         EVENT_PTR(td_slots_retired_slm),
1626         NULL
1627 };
1628
1629 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1630 {
1631         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1632         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1633         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1634         EVENT_EXTRA_END
1635 };
1636
1637 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1638 #define SLM_DMND_WRITE          SNB_DMND_RFO
1639 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1640
1641 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1642 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1643 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1644
1645 static __initconst const u64 slm_hw_cache_extra_regs
1646                                 [PERF_COUNT_HW_CACHE_MAX]
1647                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1648                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1649 {
1650  [ C(LL  ) ] = {
1651         [ C(OP_READ) ] = {
1652                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1653                 [ C(RESULT_MISS)   ] = 0,
1654         },
1655         [ C(OP_WRITE) ] = {
1656                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1657                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1658         },
1659         [ C(OP_PREFETCH) ] = {
1660                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1661                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1662         },
1663  },
1664 };
1665
1666 static __initconst const u64 slm_hw_cache_event_ids
1667                                 [PERF_COUNT_HW_CACHE_MAX]
1668                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1669                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1670 {
1671  [ C(L1D) ] = {
1672         [ C(OP_READ) ] = {
1673                 [ C(RESULT_ACCESS) ] = 0,
1674                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1675         },
1676         [ C(OP_WRITE) ] = {
1677                 [ C(RESULT_ACCESS) ] = 0,
1678                 [ C(RESULT_MISS)   ] = 0,
1679         },
1680         [ C(OP_PREFETCH) ] = {
1681                 [ C(RESULT_ACCESS) ] = 0,
1682                 [ C(RESULT_MISS)   ] = 0,
1683         },
1684  },
1685  [ C(L1I ) ] = {
1686         [ C(OP_READ) ] = {
1687                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1688                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1689         },
1690         [ C(OP_WRITE) ] = {
1691                 [ C(RESULT_ACCESS) ] = -1,
1692                 [ C(RESULT_MISS)   ] = -1,
1693         },
1694         [ C(OP_PREFETCH) ] = {
1695                 [ C(RESULT_ACCESS) ] = 0,
1696                 [ C(RESULT_MISS)   ] = 0,
1697         },
1698  },
1699  [ C(LL  ) ] = {
1700         [ C(OP_READ) ] = {
1701                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1702                 [ C(RESULT_ACCESS) ] = 0x01b7,
1703                 [ C(RESULT_MISS)   ] = 0,
1704         },
1705         [ C(OP_WRITE) ] = {
1706                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1707                 [ C(RESULT_ACCESS) ] = 0x01b7,
1708                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1709                 [ C(RESULT_MISS)   ] = 0x01b7,
1710         },
1711         [ C(OP_PREFETCH) ] = {
1712                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1713                 [ C(RESULT_ACCESS) ] = 0x01b7,
1714                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1715                 [ C(RESULT_MISS)   ] = 0x01b7,
1716         },
1717  },
1718  [ C(DTLB) ] = {
1719         [ C(OP_READ) ] = {
1720                 [ C(RESULT_ACCESS) ] = 0,
1721                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1722         },
1723         [ C(OP_WRITE) ] = {
1724                 [ C(RESULT_ACCESS) ] = 0,
1725                 [ C(RESULT_MISS)   ] = 0,
1726         },
1727         [ C(OP_PREFETCH) ] = {
1728                 [ C(RESULT_ACCESS) ] = 0,
1729                 [ C(RESULT_MISS)   ] = 0,
1730         },
1731  },
1732  [ C(ITLB) ] = {
1733         [ C(OP_READ) ] = {
1734                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1735                 [ C(RESULT_MISS)   ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1736         },
1737         [ C(OP_WRITE) ] = {
1738                 [ C(RESULT_ACCESS) ] = -1,
1739                 [ C(RESULT_MISS)   ] = -1,
1740         },
1741         [ C(OP_PREFETCH) ] = {
1742                 [ C(RESULT_ACCESS) ] = -1,
1743                 [ C(RESULT_MISS)   ] = -1,
1744         },
1745  },
1746  [ C(BPU ) ] = {
1747         [ C(OP_READ) ] = {
1748                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1749                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1750         },
1751         [ C(OP_WRITE) ] = {
1752                 [ C(RESULT_ACCESS) ] = -1,
1753                 [ C(RESULT_MISS)   ] = -1,
1754         },
1755         [ C(OP_PREFETCH) ] = {
1756                 [ C(RESULT_ACCESS) ] = -1,
1757                 [ C(RESULT_MISS)   ] = -1,
1758         },
1759  },
1760 };
1761
1762 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1763 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1764 /* UOPS_NOT_DELIVERED.ANY */
1765 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1766 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1767 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1768 /* UOPS_RETIRED.ANY */
1769 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1770 /* UOPS_ISSUED.ANY */
1771 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1772
1773 static struct attribute *glm_events_attrs[] = {
1774         EVENT_PTR(td_total_slots_glm),
1775         EVENT_PTR(td_total_slots_scale_glm),
1776         EVENT_PTR(td_fetch_bubbles_glm),
1777         EVENT_PTR(td_recovery_bubbles_glm),
1778         EVENT_PTR(td_slots_issued_glm),
1779         EVENT_PTR(td_slots_retired_glm),
1780         NULL
1781 };
1782
1783 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1784         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1785         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1786         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1787         EVENT_EXTRA_END
1788 };
1789
1790 #define GLM_DEMAND_DATA_RD              BIT_ULL(0)
1791 #define GLM_DEMAND_RFO                  BIT_ULL(1)
1792 #define GLM_ANY_RESPONSE                BIT_ULL(16)
1793 #define GLM_SNP_NONE_OR_MISS            BIT_ULL(33)
1794 #define GLM_DEMAND_READ                 GLM_DEMAND_DATA_RD
1795 #define GLM_DEMAND_WRITE                GLM_DEMAND_RFO
1796 #define GLM_DEMAND_PREFETCH             (SNB_PF_DATA_RD|SNB_PF_RFO)
1797 #define GLM_LLC_ACCESS                  GLM_ANY_RESPONSE
1798 #define GLM_SNP_ANY                     (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1799 #define GLM_LLC_MISS                    (GLM_SNP_ANY|SNB_NON_DRAM)
1800
1801 static __initconst const u64 glm_hw_cache_event_ids
1802                                 [PERF_COUNT_HW_CACHE_MAX]
1803                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1804                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1805         [C(L1D)] = {
1806                 [C(OP_READ)] = {
1807                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1808                         [C(RESULT_MISS)]        = 0x0,
1809                 },
1810                 [C(OP_WRITE)] = {
1811                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1812                         [C(RESULT_MISS)]        = 0x0,
1813                 },
1814                 [C(OP_PREFETCH)] = {
1815                         [C(RESULT_ACCESS)]      = 0x0,
1816                         [C(RESULT_MISS)]        = 0x0,
1817                 },
1818         },
1819         [C(L1I)] = {
1820                 [C(OP_READ)] = {
1821                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1822                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1823                 },
1824                 [C(OP_WRITE)] = {
1825                         [C(RESULT_ACCESS)]      = -1,
1826                         [C(RESULT_MISS)]        = -1,
1827                 },
1828                 [C(OP_PREFETCH)] = {
1829                         [C(RESULT_ACCESS)]      = 0x0,
1830                         [C(RESULT_MISS)]        = 0x0,
1831                 },
1832         },
1833         [C(LL)] = {
1834                 [C(OP_READ)] = {
1835                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1836                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1837                 },
1838                 [C(OP_WRITE)] = {
1839                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1840                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1841                 },
1842                 [C(OP_PREFETCH)] = {
1843                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1844                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1845                 },
1846         },
1847         [C(DTLB)] = {
1848                 [C(OP_READ)] = {
1849                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1850                         [C(RESULT_MISS)]        = 0x0,
1851                 },
1852                 [C(OP_WRITE)] = {
1853                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1854                         [C(RESULT_MISS)]        = 0x0,
1855                 },
1856                 [C(OP_PREFETCH)] = {
1857                         [C(RESULT_ACCESS)]      = 0x0,
1858                         [C(RESULT_MISS)]        = 0x0,
1859                 },
1860         },
1861         [C(ITLB)] = {
1862                 [C(OP_READ)] = {
1863                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1864                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1865                 },
1866                 [C(OP_WRITE)] = {
1867                         [C(RESULT_ACCESS)]      = -1,
1868                         [C(RESULT_MISS)]        = -1,
1869                 },
1870                 [C(OP_PREFETCH)] = {
1871                         [C(RESULT_ACCESS)]      = -1,
1872                         [C(RESULT_MISS)]        = -1,
1873                 },
1874         },
1875         [C(BPU)] = {
1876                 [C(OP_READ)] = {
1877                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1878                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1879                 },
1880                 [C(OP_WRITE)] = {
1881                         [C(RESULT_ACCESS)]      = -1,
1882                         [C(RESULT_MISS)]        = -1,
1883                 },
1884                 [C(OP_PREFETCH)] = {
1885                         [C(RESULT_ACCESS)]      = -1,
1886                         [C(RESULT_MISS)]        = -1,
1887                 },
1888         },
1889 };
1890
1891 static __initconst const u64 glm_hw_cache_extra_regs
1892                                 [PERF_COUNT_HW_CACHE_MAX]
1893                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1894                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1895         [C(LL)] = {
1896                 [C(OP_READ)] = {
1897                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
1898                                                   GLM_LLC_ACCESS,
1899                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
1900                                                   GLM_LLC_MISS,
1901                 },
1902                 [C(OP_WRITE)] = {
1903                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
1904                                                   GLM_LLC_ACCESS,
1905                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
1906                                                   GLM_LLC_MISS,
1907                 },
1908                 [C(OP_PREFETCH)] = {
1909                         [C(RESULT_ACCESS)]      = GLM_DEMAND_PREFETCH|
1910                                                   GLM_LLC_ACCESS,
1911                         [C(RESULT_MISS)]        = GLM_DEMAND_PREFETCH|
1912                                                   GLM_LLC_MISS,
1913                 },
1914         },
1915 };
1916
1917 static __initconst const u64 glp_hw_cache_event_ids
1918                                 [PERF_COUNT_HW_CACHE_MAX]
1919                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1920                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1921         [C(L1D)] = {
1922                 [C(OP_READ)] = {
1923                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1924                         [C(RESULT_MISS)]        = 0x0,
1925                 },
1926                 [C(OP_WRITE)] = {
1927                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1928                         [C(RESULT_MISS)]        = 0x0,
1929                 },
1930                 [C(OP_PREFETCH)] = {
1931                         [C(RESULT_ACCESS)]      = 0x0,
1932                         [C(RESULT_MISS)]        = 0x0,
1933                 },
1934         },
1935         [C(L1I)] = {
1936                 [C(OP_READ)] = {
1937                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1938                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1939                 },
1940                 [C(OP_WRITE)] = {
1941                         [C(RESULT_ACCESS)]      = -1,
1942                         [C(RESULT_MISS)]        = -1,
1943                 },
1944                 [C(OP_PREFETCH)] = {
1945                         [C(RESULT_ACCESS)]      = 0x0,
1946                         [C(RESULT_MISS)]        = 0x0,
1947                 },
1948         },
1949         [C(LL)] = {
1950                 [C(OP_READ)] = {
1951                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1952                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1953                 },
1954                 [C(OP_WRITE)] = {
1955                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1956                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1957                 },
1958                 [C(OP_PREFETCH)] = {
1959                         [C(RESULT_ACCESS)]      = 0x0,
1960                         [C(RESULT_MISS)]        = 0x0,
1961                 },
1962         },
1963         [C(DTLB)] = {
1964                 [C(OP_READ)] = {
1965                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1966                         [C(RESULT_MISS)]        = 0xe08,        /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1967                 },
1968                 [C(OP_WRITE)] = {
1969                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1970                         [C(RESULT_MISS)]        = 0xe49,        /* DTLB_STORE_MISSES.WALK_COMPLETED */
1971                 },
1972                 [C(OP_PREFETCH)] = {
1973                         [C(RESULT_ACCESS)]      = 0x0,
1974                         [C(RESULT_MISS)]        = 0x0,
1975                 },
1976         },
1977         [C(ITLB)] = {
1978                 [C(OP_READ)] = {
1979                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1980                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1981                 },
1982                 [C(OP_WRITE)] = {
1983                         [C(RESULT_ACCESS)]      = -1,
1984                         [C(RESULT_MISS)]        = -1,
1985                 },
1986                 [C(OP_PREFETCH)] = {
1987                         [C(RESULT_ACCESS)]      = -1,
1988                         [C(RESULT_MISS)]        = -1,
1989                 },
1990         },
1991         [C(BPU)] = {
1992                 [C(OP_READ)] = {
1993                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1994                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1995                 },
1996                 [C(OP_WRITE)] = {
1997                         [C(RESULT_ACCESS)]      = -1,
1998                         [C(RESULT_MISS)]        = -1,
1999                 },
2000                 [C(OP_PREFETCH)] = {
2001                         [C(RESULT_ACCESS)]      = -1,
2002                         [C(RESULT_MISS)]        = -1,
2003                 },
2004         },
2005 };
2006
2007 static __initconst const u64 glp_hw_cache_extra_regs
2008                                 [PERF_COUNT_HW_CACHE_MAX]
2009                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2010                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2011         [C(LL)] = {
2012                 [C(OP_READ)] = {
2013                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
2014                                                   GLM_LLC_ACCESS,
2015                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
2016                                                   GLM_LLC_MISS,
2017                 },
2018                 [C(OP_WRITE)] = {
2019                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
2020                                                   GLM_LLC_ACCESS,
2021                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
2022                                                   GLM_LLC_MISS,
2023                 },
2024                 [C(OP_PREFETCH)] = {
2025                         [C(RESULT_ACCESS)]      = 0x0,
2026                         [C(RESULT_MISS)]        = 0x0,
2027                 },
2028         },
2029 };
2030
2031 #define TNT_LOCAL_DRAM                  BIT_ULL(26)
2032 #define TNT_DEMAND_READ                 GLM_DEMAND_DATA_RD
2033 #define TNT_DEMAND_WRITE                GLM_DEMAND_RFO
2034 #define TNT_LLC_ACCESS                  GLM_ANY_RESPONSE
2035 #define TNT_SNP_ANY                     (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2036                                          SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2037 #define TNT_LLC_MISS                    (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2038
2039 static __initconst const u64 tnt_hw_cache_extra_regs
2040                                 [PERF_COUNT_HW_CACHE_MAX]
2041                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2042                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2043         [C(LL)] = {
2044                 [C(OP_READ)] = {
2045                         [C(RESULT_ACCESS)]      = TNT_DEMAND_READ|
2046                                                   TNT_LLC_ACCESS,
2047                         [C(RESULT_MISS)]        = TNT_DEMAND_READ|
2048                                                   TNT_LLC_MISS,
2049                 },
2050                 [C(OP_WRITE)] = {
2051                         [C(RESULT_ACCESS)]      = TNT_DEMAND_WRITE|
2052                                                   TNT_LLC_ACCESS,
2053                         [C(RESULT_MISS)]        = TNT_DEMAND_WRITE|
2054                                                   TNT_LLC_MISS,
2055                 },
2056                 [C(OP_PREFETCH)] = {
2057                         [C(RESULT_ACCESS)]      = 0x0,
2058                         [C(RESULT_MISS)]        = 0x0,
2059                 },
2060         },
2061 };
2062
2063 EVENT_ATTR_STR(topdown-fe-bound,       td_fe_bound_tnt,        "event=0x71,umask=0x0");
2064 EVENT_ATTR_STR(topdown-retiring,       td_retiring_tnt,        "event=0xc2,umask=0x0");
2065 EVENT_ATTR_STR(topdown-bad-spec,       td_bad_spec_tnt,        "event=0x73,umask=0x6");
2066 EVENT_ATTR_STR(topdown-be-bound,       td_be_bound_tnt,        "event=0x74,umask=0x0");
2067
2068 static struct attribute *tnt_events_attrs[] = {
2069         EVENT_PTR(td_fe_bound_tnt),
2070         EVENT_PTR(td_retiring_tnt),
2071         EVENT_PTR(td_bad_spec_tnt),
2072         EVENT_PTR(td_be_bound_tnt),
2073         NULL,
2074 };
2075
2076 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2077         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2078         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2079         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2080         EVENT_EXTRA_END
2081 };
2082
2083 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2084         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2085         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2086         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2087         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2088         EVENT_EXTRA_END
2089 };
2090
2091 #define KNL_OT_L2_HITE          BIT_ULL(19) /* Other Tile L2 Hit */
2092 #define KNL_OT_L2_HITF          BIT_ULL(20) /* Other Tile L2 Hit */
2093 #define KNL_MCDRAM_LOCAL        BIT_ULL(21)
2094 #define KNL_MCDRAM_FAR          BIT_ULL(22)
2095 #define KNL_DDR_LOCAL           BIT_ULL(23)
2096 #define KNL_DDR_FAR             BIT_ULL(24)
2097 #define KNL_DRAM_ANY            (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2098                                     KNL_DDR_LOCAL | KNL_DDR_FAR)
2099 #define KNL_L2_READ             SLM_DMND_READ
2100 #define KNL_L2_WRITE            SLM_DMND_WRITE
2101 #define KNL_L2_PREFETCH         SLM_DMND_PREFETCH
2102 #define KNL_L2_ACCESS           SLM_LLC_ACCESS
2103 #define KNL_L2_MISS             (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2104                                    KNL_DRAM_ANY | SNB_SNP_ANY | \
2105                                                   SNB_NON_DRAM)
2106
2107 static __initconst const u64 knl_hw_cache_extra_regs
2108                                 [PERF_COUNT_HW_CACHE_MAX]
2109                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2110                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2111         [C(LL)] = {
2112                 [C(OP_READ)] = {
2113                         [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2114                         [C(RESULT_MISS)]   = 0,
2115                 },
2116                 [C(OP_WRITE)] = {
2117                         [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2118                         [C(RESULT_MISS)]   = KNL_L2_WRITE | KNL_L2_MISS,
2119                 },
2120                 [C(OP_PREFETCH)] = {
2121                         [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2122                         [C(RESULT_MISS)]   = KNL_L2_PREFETCH | KNL_L2_MISS,
2123                 },
2124         },
2125 };
2126
2127 /*
2128  * Used from PMIs where the LBRs are already disabled.
2129  *
2130  * This function could be called consecutively. It is required to remain in
2131  * disabled state if called consecutively.
2132  *
2133  * During consecutive calls, the same disable value will be written to related
2134  * registers, so the PMU state remains unchanged.
2135  *
2136  * intel_bts events don't coexist with intel PMU's BTS events because of
2137  * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2138  * disabled around intel PMU's event batching etc, only inside the PMI handler.
2139  *
2140  * Avoid PEBS_ENABLE MSR access in PMIs.
2141  * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2142  * It doesn't matter if the PEBS is enabled or not.
2143  * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2144  * access PEBS_ENABLE MSR in disable_all()/enable_all().
2145  * However, there are some cases which may change PEBS status, e.g. PMI
2146  * throttle. The PEBS_ENABLE should be updated where the status changes.
2147  */
2148 static void __intel_pmu_disable_all(void)
2149 {
2150         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2151
2152         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2153
2154         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2155                 intel_pmu_disable_bts();
2156 }
2157
2158 static void intel_pmu_disable_all(void)
2159 {
2160         __intel_pmu_disable_all();
2161         intel_pmu_pebs_disable_all();
2162         intel_pmu_lbr_disable_all();
2163 }
2164
2165 static void __intel_pmu_enable_all(int added, bool pmi)
2166 {
2167         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2168         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2169
2170         intel_pmu_lbr_enable_all(pmi);
2171         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2172                intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2173
2174         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2175                 struct perf_event *event =
2176                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2177
2178                 if (WARN_ON_ONCE(!event))
2179                         return;
2180
2181                 intel_pmu_enable_bts(event->hw.config);
2182         }
2183 }
2184
2185 static void intel_pmu_enable_all(int added)
2186 {
2187         intel_pmu_pebs_enable_all();
2188         __intel_pmu_enable_all(added, false);
2189 }
2190
2191 /*
2192  * Workaround for:
2193  *   Intel Errata AAK100 (model 26)
2194  *   Intel Errata AAP53  (model 30)
2195  *   Intel Errata BD53   (model 44)
2196  *
2197  * The official story:
2198  *   These chips need to be 'reset' when adding counters by programming the
2199  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2200  *   in sequence on the same PMC or on different PMCs.
2201  *
2202  * In practice it appears some of these events do in fact count, and
2203  * we need to program all 4 events.
2204  */
2205 static void intel_pmu_nhm_workaround(void)
2206 {
2207         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2208         static const unsigned long nhm_magic[4] = {
2209                 0x4300B5,
2210                 0x4300D2,
2211                 0x4300B1,
2212                 0x4300B1
2213         };
2214         struct perf_event *event;
2215         int i;
2216
2217         /*
2218          * The Errata requires below steps:
2219          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2220          * 2) Configure 4 PERFEVTSELx with the magic events and clear
2221          *    the corresponding PMCx;
2222          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2223          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2224          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2225          */
2226
2227         /*
2228          * The real steps we choose are a little different from above.
2229          * A) To reduce MSR operations, we don't run step 1) as they
2230          *    are already cleared before this function is called;
2231          * B) Call x86_perf_event_update to save PMCx before configuring
2232          *    PERFEVTSELx with magic number;
2233          * C) With step 5), we do clear only when the PERFEVTSELx is
2234          *    not used currently.
2235          * D) Call x86_perf_event_set_period to restore PMCx;
2236          */
2237
2238         /* We always operate 4 pairs of PERF Counters */
2239         for (i = 0; i < 4; i++) {
2240                 event = cpuc->events[i];
2241                 if (event)
2242                         x86_perf_event_update(event);
2243         }
2244
2245         for (i = 0; i < 4; i++) {
2246                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2247                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2248         }
2249
2250         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2251         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2252
2253         for (i = 0; i < 4; i++) {
2254                 event = cpuc->events[i];
2255
2256                 if (event) {
2257                         x86_perf_event_set_period(event);
2258                         __x86_pmu_enable_event(&event->hw,
2259                                         ARCH_PERFMON_EVENTSEL_ENABLE);
2260                 } else
2261                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2262         }
2263 }
2264
2265 static void intel_pmu_nhm_enable_all(int added)
2266 {
2267         if (added)
2268                 intel_pmu_nhm_workaround();
2269         intel_pmu_enable_all(added);
2270 }
2271
2272 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2273 {
2274         u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2275
2276         if (cpuc->tfa_shadow != val) {
2277                 cpuc->tfa_shadow = val;
2278                 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2279         }
2280 }
2281
2282 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2283 {
2284         /*
2285          * We're going to use PMC3, make sure TFA is set before we touch it.
2286          */
2287         if (cntr == 3)
2288                 intel_set_tfa(cpuc, true);
2289 }
2290
2291 static void intel_tfa_pmu_enable_all(int added)
2292 {
2293         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2294
2295         /*
2296          * If we find PMC3 is no longer used when we enable the PMU, we can
2297          * clear TFA.
2298          */
2299         if (!test_bit(3, cpuc->active_mask))
2300                 intel_set_tfa(cpuc, false);
2301
2302         intel_pmu_enable_all(added);
2303 }
2304
2305 static inline u64 intel_pmu_get_status(void)
2306 {
2307         u64 status;
2308
2309         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2310
2311         return status;
2312 }
2313
2314 static inline void intel_pmu_ack_status(u64 ack)
2315 {
2316         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2317 }
2318
2319 static inline bool event_is_checkpointed(struct perf_event *event)
2320 {
2321         return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2322 }
2323
2324 static inline void intel_set_masks(struct perf_event *event, int idx)
2325 {
2326         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2327
2328         if (event->attr.exclude_host)
2329                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2330         if (event->attr.exclude_guest)
2331                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2332         if (event_is_checkpointed(event))
2333                 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2334 }
2335
2336 static inline void intel_clear_masks(struct perf_event *event, int idx)
2337 {
2338         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2339
2340         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2341         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2342         __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2343 }
2344
2345 static void intel_pmu_disable_fixed(struct perf_event *event)
2346 {
2347         struct hw_perf_event *hwc = &event->hw;
2348         u64 ctrl_val, mask;
2349         int idx = hwc->idx;
2350
2351         if (is_topdown_idx(idx)) {
2352                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2353
2354                 /*
2355                  * When there are other active TopDown events,
2356                  * don't disable the fixed counter 3.
2357                  */
2358                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2359                         return;
2360                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2361         }
2362
2363         intel_clear_masks(event, idx);
2364
2365         mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2366         rdmsrl(hwc->config_base, ctrl_val);
2367         ctrl_val &= ~mask;
2368         wrmsrl(hwc->config_base, ctrl_val);
2369 }
2370
2371 static void intel_pmu_disable_event(struct perf_event *event)
2372 {
2373         struct hw_perf_event *hwc = &event->hw;
2374         int idx = hwc->idx;
2375
2376         switch (idx) {
2377         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2378                 intel_clear_masks(event, idx);
2379                 x86_pmu_disable_event(event);
2380                 break;
2381         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2382         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2383                 intel_pmu_disable_fixed(event);
2384                 break;
2385         case INTEL_PMC_IDX_FIXED_BTS:
2386                 intel_pmu_disable_bts();
2387                 intel_pmu_drain_bts_buffer();
2388                 return;
2389         case INTEL_PMC_IDX_FIXED_VLBR:
2390                 intel_clear_masks(event, idx);
2391                 break;
2392         default:
2393                 intel_clear_masks(event, idx);
2394                 pr_warn("Failed to disable the event with invalid index %d\n",
2395                         idx);
2396                 return;
2397         }
2398
2399         /*
2400          * Needs to be called after x86_pmu_disable_event,
2401          * so we don't trigger the event without PEBS bit set.
2402          */
2403         if (unlikely(event->attr.precise_ip))
2404                 intel_pmu_pebs_disable(event);
2405 }
2406
2407 static void intel_pmu_del_event(struct perf_event *event)
2408 {
2409         if (needs_branch_stack(event))
2410                 intel_pmu_lbr_del(event);
2411         if (event->attr.precise_ip)
2412                 intel_pmu_pebs_del(event);
2413 }
2414
2415 static int icl_set_topdown_event_period(struct perf_event *event)
2416 {
2417         struct hw_perf_event *hwc = &event->hw;
2418         s64 left = local64_read(&hwc->period_left);
2419
2420         /*
2421          * The values in PERF_METRICS MSR are derived from fixed counter 3.
2422          * Software should start both registers, PERF_METRICS and fixed
2423          * counter 3, from zero.
2424          * Clear PERF_METRICS and Fixed counter 3 in initialization.
2425          * After that, both MSRs will be cleared for each read.
2426          * Don't need to clear them again.
2427          */
2428         if (left == x86_pmu.max_period) {
2429                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2430                 wrmsrl(MSR_PERF_METRICS, 0);
2431                 hwc->saved_slots = 0;
2432                 hwc->saved_metric = 0;
2433         }
2434
2435         if ((hwc->saved_slots) && is_slots_event(event)) {
2436                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2437                 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2438         }
2439
2440         perf_event_update_userpage(event);
2441
2442         return 0;
2443 }
2444
2445 static int adl_set_topdown_event_period(struct perf_event *event)
2446 {
2447         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2448
2449         if (pmu->cpu_type != hybrid_big)
2450                 return 0;
2451
2452         return icl_set_topdown_event_period(event);
2453 }
2454
2455 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2456 {
2457         u32 val;
2458
2459         /*
2460          * The metric is reported as an 8bit integer fraction
2461          * summing up to 0xff.
2462          * slots-in-metric = (Metric / 0xff) * slots
2463          */
2464         val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2465         return  mul_u64_u32_div(slots, val, 0xff);
2466 }
2467
2468 static u64 icl_get_topdown_value(struct perf_event *event,
2469                                        u64 slots, u64 metrics)
2470 {
2471         int idx = event->hw.idx;
2472         u64 delta;
2473
2474         if (is_metric_idx(idx))
2475                 delta = icl_get_metrics_event_value(metrics, slots, idx);
2476         else
2477                 delta = slots;
2478
2479         return delta;
2480 }
2481
2482 static void __icl_update_topdown_event(struct perf_event *event,
2483                                        u64 slots, u64 metrics,
2484                                        u64 last_slots, u64 last_metrics)
2485 {
2486         u64 delta, last = 0;
2487
2488         delta = icl_get_topdown_value(event, slots, metrics);
2489         if (last_slots)
2490                 last = icl_get_topdown_value(event, last_slots, last_metrics);
2491
2492         /*
2493          * The 8bit integer fraction of metric may be not accurate,
2494          * especially when the changes is very small.
2495          * For example, if only a few bad_spec happens, the fraction
2496          * may be reduced from 1 to 0. If so, the bad_spec event value
2497          * will be 0 which is definitely less than the last value.
2498          * Avoid update event->count for this case.
2499          */
2500         if (delta > last) {
2501                 delta -= last;
2502                 local64_add(delta, &event->count);
2503         }
2504 }
2505
2506 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2507                                       u64 metrics, int metric_end)
2508 {
2509         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2510         struct perf_event *other;
2511         int idx;
2512
2513         event->hw.saved_slots = slots;
2514         event->hw.saved_metric = metrics;
2515
2516         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2517                 if (!is_topdown_idx(idx))
2518                         continue;
2519                 other = cpuc->events[idx];
2520                 other->hw.saved_slots = slots;
2521                 other->hw.saved_metric = metrics;
2522         }
2523 }
2524
2525 /*
2526  * Update all active Topdown events.
2527  *
2528  * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2529  * modify by a NMI. PMU has to be disabled before calling this function.
2530  */
2531
2532 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2533 {
2534         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2535         struct perf_event *other;
2536         u64 slots, metrics;
2537         bool reset = true;
2538         int idx;
2539
2540         /* read Fixed counter 3 */
2541         rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2542         if (!slots)
2543                 return 0;
2544
2545         /* read PERF_METRICS */
2546         rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2547
2548         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2549                 if (!is_topdown_idx(idx))
2550                         continue;
2551                 other = cpuc->events[idx];
2552                 __icl_update_topdown_event(other, slots, metrics,
2553                                            event ? event->hw.saved_slots : 0,
2554                                            event ? event->hw.saved_metric : 0);
2555         }
2556
2557         /*
2558          * Check and update this event, which may have been cleared
2559          * in active_mask e.g. x86_pmu_stop()
2560          */
2561         if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2562                 __icl_update_topdown_event(event, slots, metrics,
2563                                            event->hw.saved_slots,
2564                                            event->hw.saved_metric);
2565
2566                 /*
2567                  * In x86_pmu_stop(), the event is cleared in active_mask first,
2568                  * then drain the delta, which indicates context switch for
2569                  * counting.
2570                  * Save metric and slots for context switch.
2571                  * Don't need to reset the PERF_METRICS and Fixed counter 3.
2572                  * Because the values will be restored in next schedule in.
2573                  */
2574                 update_saved_topdown_regs(event, slots, metrics, metric_end);
2575                 reset = false;
2576         }
2577
2578         if (reset) {
2579                 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2580                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2581                 wrmsrl(MSR_PERF_METRICS, 0);
2582                 if (event)
2583                         update_saved_topdown_regs(event, 0, 0, metric_end);
2584         }
2585
2586         return slots;
2587 }
2588
2589 static u64 icl_update_topdown_event(struct perf_event *event)
2590 {
2591         return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2592                                                  x86_pmu.num_topdown_events - 1);
2593 }
2594
2595 static u64 adl_update_topdown_event(struct perf_event *event)
2596 {
2597         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2598
2599         if (pmu->cpu_type != hybrid_big)
2600                 return 0;
2601
2602         return icl_update_topdown_event(event);
2603 }
2604
2605
2606 static void intel_pmu_read_topdown_event(struct perf_event *event)
2607 {
2608         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2609
2610         /* Only need to call update_topdown_event() once for group read. */
2611         if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2612             !is_slots_event(event))
2613                 return;
2614
2615         perf_pmu_disable(event->pmu);
2616         x86_pmu.update_topdown_event(event);
2617         perf_pmu_enable(event->pmu);
2618 }
2619
2620 static void intel_pmu_read_event(struct perf_event *event)
2621 {
2622         if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2623                 intel_pmu_auto_reload_read(event);
2624         else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2625                 intel_pmu_read_topdown_event(event);
2626         else
2627                 x86_perf_event_update(event);
2628 }
2629
2630 static void intel_pmu_enable_fixed(struct perf_event *event)
2631 {
2632         struct hw_perf_event *hwc = &event->hw;
2633         u64 ctrl_val, mask, bits = 0;
2634         int idx = hwc->idx;
2635
2636         if (is_topdown_idx(idx)) {
2637                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2638                 /*
2639                  * When there are other active TopDown events,
2640                  * don't enable the fixed counter 3 again.
2641                  */
2642                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2643                         return;
2644
2645                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2646         }
2647
2648         intel_set_masks(event, idx);
2649
2650         /*
2651          * Enable IRQ generation (0x8), if not PEBS,
2652          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2653          * if requested:
2654          */
2655         if (!event->attr.precise_ip)
2656                 bits |= 0x8;
2657         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2658                 bits |= 0x2;
2659         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2660                 bits |= 0x1;
2661
2662         /*
2663          * ANY bit is supported in v3 and up
2664          */
2665         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2666                 bits |= 0x4;
2667
2668         idx -= INTEL_PMC_IDX_FIXED;
2669         bits <<= (idx * 4);
2670         mask = 0xfULL << (idx * 4);
2671
2672         if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2673                 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2674                 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2675         }
2676
2677         rdmsrl(hwc->config_base, ctrl_val);
2678         ctrl_val &= ~mask;
2679         ctrl_val |= bits;
2680         wrmsrl(hwc->config_base, ctrl_val);
2681 }
2682
2683 static void intel_pmu_enable_event(struct perf_event *event)
2684 {
2685         struct hw_perf_event *hwc = &event->hw;
2686         int idx = hwc->idx;
2687
2688         if (unlikely(event->attr.precise_ip))
2689                 intel_pmu_pebs_enable(event);
2690
2691         switch (idx) {
2692         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2693                 intel_set_masks(event, idx);
2694                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2695                 break;
2696         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2697         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2698                 intel_pmu_enable_fixed(event);
2699                 break;
2700         case INTEL_PMC_IDX_FIXED_BTS:
2701                 if (!__this_cpu_read(cpu_hw_events.enabled))
2702                         return;
2703                 intel_pmu_enable_bts(hwc->config);
2704                 break;
2705         case INTEL_PMC_IDX_FIXED_VLBR:
2706                 intel_set_masks(event, idx);
2707                 break;
2708         default:
2709                 pr_warn("Failed to enable the event with invalid index %d\n",
2710                         idx);
2711         }
2712 }
2713
2714 static void intel_pmu_add_event(struct perf_event *event)
2715 {
2716         if (event->attr.precise_ip)
2717                 intel_pmu_pebs_add(event);
2718         if (needs_branch_stack(event))
2719                 intel_pmu_lbr_add(event);
2720 }
2721
2722 /*
2723  * Save and restart an expired event. Called by NMI contexts,
2724  * so it has to be careful about preempting normal event ops:
2725  */
2726 int intel_pmu_save_and_restart(struct perf_event *event)
2727 {
2728         x86_perf_event_update(event);
2729         /*
2730          * For a checkpointed counter always reset back to 0.  This
2731          * avoids a situation where the counter overflows, aborts the
2732          * transaction and is then set back to shortly before the
2733          * overflow, and overflows and aborts again.
2734          */
2735         if (unlikely(event_is_checkpointed(event))) {
2736                 /* No race with NMIs because the counter should not be armed */
2737                 wrmsrl(event->hw.event_base, 0);
2738                 local64_set(&event->hw.prev_count, 0);
2739         }
2740         return x86_perf_event_set_period(event);
2741 }
2742
2743 static void intel_pmu_reset(void)
2744 {
2745         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2746         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2747         int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2748         int num_counters = hybrid(cpuc->pmu, num_counters);
2749         unsigned long flags;
2750         int idx;
2751
2752         if (!num_counters)
2753                 return;
2754
2755         local_irq_save(flags);
2756
2757         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2758
2759         for (idx = 0; idx < num_counters; idx++) {
2760                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2761                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
2762         }
2763         for (idx = 0; idx < num_counters_fixed; idx++) {
2764                 if (fixed_counter_disabled(idx, cpuc->pmu))
2765                         continue;
2766                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2767         }
2768
2769         if (ds)
2770                 ds->bts_index = ds->bts_buffer_base;
2771
2772         /* Ack all overflows and disable fixed counters */
2773         if (x86_pmu.version >= 2) {
2774                 intel_pmu_ack_status(intel_pmu_get_status());
2775                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2776         }
2777
2778         /* Reset LBRs and LBR freezing */
2779         if (x86_pmu.lbr_nr) {
2780                 update_debugctlmsr(get_debugctlmsr() &
2781                         ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2782         }
2783
2784         local_irq_restore(flags);
2785 }
2786
2787 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2788 {
2789         struct perf_sample_data data;
2790         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2791         struct perf_guest_info_callbacks *guest_cbs;
2792         int bit;
2793         int handled = 0;
2794         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2795
2796         inc_irq_stat(apic_perf_irqs);
2797
2798         /*
2799          * Ignore a range of extra bits in status that do not indicate
2800          * overflow by themselves.
2801          */
2802         status &= ~(GLOBAL_STATUS_COND_CHG |
2803                     GLOBAL_STATUS_ASIF |
2804                     GLOBAL_STATUS_LBRS_FROZEN);
2805         if (!status)
2806                 return 0;
2807         /*
2808          * In case multiple PEBS events are sampled at the same time,
2809          * it is possible to have GLOBAL_STATUS bit 62 set indicating
2810          * PEBS buffer overflow and also seeing at most 3 PEBS counters
2811          * having their bits set in the status register. This is a sign
2812          * that there was at least one PEBS record pending at the time
2813          * of the PMU interrupt. PEBS counters must only be processed
2814          * via the drain_pebs() calls and not via the regular sample
2815          * processing loop coming after that the function, otherwise
2816          * phony regular samples may be generated in the sampling buffer
2817          * not marked with the EXACT tag. Another possibility is to have
2818          * one PEBS event and at least one non-PEBS event which overflows
2819          * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2820          * not be set, yet the overflow status bit for the PEBS counter will
2821          * be on Skylake.
2822          *
2823          * To avoid this problem, we systematically ignore the PEBS-enabled
2824          * counters from the GLOBAL_STATUS mask and we always process PEBS
2825          * events via drain_pebs().
2826          */
2827         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2828                 status &= ~cpuc->pebs_enabled;
2829         else
2830                 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2831
2832         /*
2833          * PEBS overflow sets bit 62 in the global status register
2834          */
2835         if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2836                 u64 pebs_enabled = cpuc->pebs_enabled;
2837
2838                 handled++;
2839                 x86_pmu.drain_pebs(regs, &data);
2840                 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2841
2842                 /*
2843                  * PMI throttle may be triggered, which stops the PEBS event.
2844                  * Although cpuc->pebs_enabled is updated accordingly, the
2845                  * MSR_IA32_PEBS_ENABLE is not updated. Because the
2846                  * cpuc->enabled has been forced to 0 in PMI.
2847                  * Update the MSR if pebs_enabled is changed.
2848                  */
2849                 if (pebs_enabled != cpuc->pebs_enabled)
2850                         wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2851         }
2852
2853         /*
2854          * Intel PT
2855          */
2856         if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2857                 handled++;
2858
2859                 guest_cbs = perf_get_guest_cbs();
2860                 if (unlikely(guest_cbs && guest_cbs->is_in_guest() &&
2861                              guest_cbs->handle_intel_pt_intr))
2862                         guest_cbs->handle_intel_pt_intr();
2863                 else
2864                         intel_pt_interrupt();
2865         }
2866
2867         /*
2868          * Intel Perf metrics
2869          */
2870         if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2871                 handled++;
2872                 if (x86_pmu.update_topdown_event)
2873                         x86_pmu.update_topdown_event(NULL);
2874         }
2875
2876         /*
2877          * Checkpointed counters can lead to 'spurious' PMIs because the
2878          * rollback caused by the PMI will have cleared the overflow status
2879          * bit. Therefore always force probe these counters.
2880          */
2881         status |= cpuc->intel_cp_status;
2882
2883         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2884                 struct perf_event *event = cpuc->events[bit];
2885
2886                 handled++;
2887
2888                 if (!test_bit(bit, cpuc->active_mask))
2889                         continue;
2890
2891                 if (!intel_pmu_save_and_restart(event))
2892                         continue;
2893
2894                 perf_sample_data_init(&data, 0, event->hw.last_period);
2895
2896                 if (has_branch_stack(event))
2897                         data.br_stack = &cpuc->lbr_stack;
2898
2899                 if (perf_event_overflow(event, &data, regs))
2900                         x86_pmu_stop(event, 0);
2901         }
2902
2903         return handled;
2904 }
2905
2906 /*
2907  * This handler is triggered by the local APIC, so the APIC IRQ handling
2908  * rules apply:
2909  */
2910 static int intel_pmu_handle_irq(struct pt_regs *regs)
2911 {
2912         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2913         bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
2914         bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
2915         int loops;
2916         u64 status;
2917         int handled;
2918         int pmu_enabled;
2919
2920         /*
2921          * Save the PMU state.
2922          * It needs to be restored when leaving the handler.
2923          */
2924         pmu_enabled = cpuc->enabled;
2925         /*
2926          * In general, the early ACK is only applied for old platforms.
2927          * For the big core starts from Haswell, the late ACK should be
2928          * applied.
2929          * For the small core after Tremont, we have to do the ACK right
2930          * before re-enabling counters, which is in the middle of the
2931          * NMI handler.
2932          */
2933         if (!late_ack && !mid_ack)
2934                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2935         intel_bts_disable_local();
2936         cpuc->enabled = 0;
2937         __intel_pmu_disable_all();
2938         handled = intel_pmu_drain_bts_buffer();
2939         handled += intel_bts_interrupt();
2940         status = intel_pmu_get_status();
2941         if (!status)
2942                 goto done;
2943
2944         loops = 0;
2945 again:
2946         intel_pmu_lbr_read();
2947         intel_pmu_ack_status(status);
2948         if (++loops > 100) {
2949                 static bool warned;
2950
2951                 if (!warned) {
2952                         WARN(1, "perfevents: irq loop stuck!\n");
2953                         perf_event_print_debug();
2954                         warned = true;
2955                 }
2956                 intel_pmu_reset();
2957                 goto done;
2958         }
2959
2960         handled += handle_pmi_common(regs, status);
2961
2962         /*
2963          * Repeat if there is more work to be done:
2964          */
2965         status = intel_pmu_get_status();
2966         if (status)
2967                 goto again;
2968
2969 done:
2970         if (mid_ack)
2971                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2972         /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2973         cpuc->enabled = pmu_enabled;
2974         if (pmu_enabled)
2975                 __intel_pmu_enable_all(0, true);
2976         intel_bts_enable_local();
2977
2978         /*
2979          * Only unmask the NMI after the overflow counters
2980          * have been reset. This avoids spurious NMIs on
2981          * Haswell CPUs.
2982          */
2983         if (late_ack)
2984                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2985         return handled;
2986 }
2987
2988 static struct event_constraint *
2989 intel_bts_constraints(struct perf_event *event)
2990 {
2991         if (unlikely(intel_pmu_has_bts(event)))
2992                 return &bts_constraint;
2993
2994         return NULL;
2995 }
2996
2997 /*
2998  * Note: matches a fake event, like Fixed2.
2999  */
3000 static struct event_constraint *
3001 intel_vlbr_constraints(struct perf_event *event)
3002 {
3003         struct event_constraint *c = &vlbr_constraint;
3004
3005         if (unlikely(constraint_match(c, event->hw.config))) {
3006                 event->hw.flags |= c->flags;
3007                 return c;
3008         }
3009
3010         return NULL;
3011 }
3012
3013 static int intel_alt_er(struct cpu_hw_events *cpuc,
3014                         int idx, u64 config)
3015 {
3016         struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3017         int alt_idx = idx;
3018
3019         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3020                 return idx;
3021
3022         if (idx == EXTRA_REG_RSP_0)
3023                 alt_idx = EXTRA_REG_RSP_1;
3024
3025         if (idx == EXTRA_REG_RSP_1)
3026                 alt_idx = EXTRA_REG_RSP_0;
3027
3028         if (config & ~extra_regs[alt_idx].valid_mask)
3029                 return idx;
3030
3031         return alt_idx;
3032 }
3033
3034 static void intel_fixup_er(struct perf_event *event, int idx)
3035 {
3036         struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3037         event->hw.extra_reg.idx = idx;
3038
3039         if (idx == EXTRA_REG_RSP_0) {
3040                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3041                 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3042                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3043         } else if (idx == EXTRA_REG_RSP_1) {
3044                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3045                 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3046                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3047         }
3048 }
3049
3050 /*
3051  * manage allocation of shared extra msr for certain events
3052  *
3053  * sharing can be:
3054  * per-cpu: to be shared between the various events on a single PMU
3055  * per-core: per-cpu + shared by HT threads
3056  */
3057 static struct event_constraint *
3058 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3059                                    struct perf_event *event,
3060                                    struct hw_perf_event_extra *reg)
3061 {
3062         struct event_constraint *c = &emptyconstraint;
3063         struct er_account *era;
3064         unsigned long flags;
3065         int idx = reg->idx;
3066
3067         /*
3068          * reg->alloc can be set due to existing state, so for fake cpuc we
3069          * need to ignore this, otherwise we might fail to allocate proper fake
3070          * state for this extra reg constraint. Also see the comment below.
3071          */
3072         if (reg->alloc && !cpuc->is_fake)
3073                 return NULL; /* call x86_get_event_constraint() */
3074
3075 again:
3076         era = &cpuc->shared_regs->regs[idx];
3077         /*
3078          * we use spin_lock_irqsave() to avoid lockdep issues when
3079          * passing a fake cpuc
3080          */
3081         raw_spin_lock_irqsave(&era->lock, flags);
3082
3083         if (!atomic_read(&era->ref) || era->config == reg->config) {
3084
3085                 /*
3086                  * If its a fake cpuc -- as per validate_{group,event}() we
3087                  * shouldn't touch event state and we can avoid doing so
3088                  * since both will only call get_event_constraints() once
3089                  * on each event, this avoids the need for reg->alloc.
3090                  *
3091                  * Not doing the ER fixup will only result in era->reg being
3092                  * wrong, but since we won't actually try and program hardware
3093                  * this isn't a problem either.
3094                  */
3095                 if (!cpuc->is_fake) {
3096                         if (idx != reg->idx)
3097                                 intel_fixup_er(event, idx);
3098
3099                         /*
3100                          * x86_schedule_events() can call get_event_constraints()
3101                          * multiple times on events in the case of incremental
3102                          * scheduling(). reg->alloc ensures we only do the ER
3103                          * allocation once.
3104                          */
3105                         reg->alloc = 1;
3106                 }
3107
3108                 /* lock in msr value */
3109                 era->config = reg->config;
3110                 era->reg = reg->reg;
3111
3112                 /* one more user */
3113                 atomic_inc(&era->ref);
3114
3115                 /*
3116                  * need to call x86_get_event_constraint()
3117                  * to check if associated event has constraints
3118                  */
3119                 c = NULL;
3120         } else {
3121                 idx = intel_alt_er(cpuc, idx, reg->config);
3122                 if (idx != reg->idx) {
3123                         raw_spin_unlock_irqrestore(&era->lock, flags);
3124                         goto again;
3125                 }
3126         }
3127         raw_spin_unlock_irqrestore(&era->lock, flags);
3128
3129         return c;
3130 }
3131
3132 static void
3133 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3134                                    struct hw_perf_event_extra *reg)
3135 {
3136         struct er_account *era;
3137
3138         /*
3139          * Only put constraint if extra reg was actually allocated. Also takes
3140          * care of event which do not use an extra shared reg.
3141          *
3142          * Also, if this is a fake cpuc we shouldn't touch any event state
3143          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3144          * either since it'll be thrown out.
3145          */
3146         if (!reg->alloc || cpuc->is_fake)
3147                 return;
3148
3149         era = &cpuc->shared_regs->regs[reg->idx];
3150
3151         /* one fewer user */
3152         atomic_dec(&era->ref);
3153
3154         /* allocate again next time */
3155         reg->alloc = 0;
3156 }
3157
3158 static struct event_constraint *
3159 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3160                               struct perf_event *event)
3161 {
3162         struct event_constraint *c = NULL, *d;
3163         struct hw_perf_event_extra *xreg, *breg;
3164
3165         xreg = &event->hw.extra_reg;
3166         if (xreg->idx != EXTRA_REG_NONE) {
3167                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3168                 if (c == &emptyconstraint)
3169                         return c;
3170         }
3171         breg = &event->hw.branch_reg;
3172         if (breg->idx != EXTRA_REG_NONE) {
3173                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3174                 if (d == &emptyconstraint) {
3175                         __intel_shared_reg_put_constraints(cpuc, xreg);
3176                         c = d;
3177                 }
3178         }
3179         return c;
3180 }
3181
3182 struct event_constraint *
3183 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3184                           struct perf_event *event)
3185 {
3186         struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3187         struct event_constraint *c;
3188
3189         if (event_constraints) {
3190                 for_each_event_constraint(c, event_constraints) {
3191                         if (constraint_match(c, event->hw.config)) {
3192                                 event->hw.flags |= c->flags;
3193                                 return c;
3194                         }
3195                 }
3196         }
3197
3198         return &hybrid_var(cpuc->pmu, unconstrained);
3199 }
3200
3201 static struct event_constraint *
3202 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3203                             struct perf_event *event)
3204 {
3205         struct event_constraint *c;
3206
3207         c = intel_vlbr_constraints(event);
3208         if (c)
3209                 return c;
3210
3211         c = intel_bts_constraints(event);
3212         if (c)
3213                 return c;
3214
3215         c = intel_shared_regs_constraints(cpuc, event);
3216         if (c)
3217                 return c;
3218
3219         c = intel_pebs_constraints(event);
3220         if (c)
3221                 return c;
3222
3223         return x86_get_event_constraints(cpuc, idx, event);
3224 }
3225
3226 static void
3227 intel_start_scheduling(struct cpu_hw_events *cpuc)
3228 {
3229         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3230         struct intel_excl_states *xl;
3231         int tid = cpuc->excl_thread_id;
3232
3233         /*
3234          * nothing needed if in group validation mode
3235          */
3236         if (cpuc->is_fake || !is_ht_workaround_enabled())
3237                 return;
3238
3239         /*
3240          * no exclusion needed
3241          */
3242         if (WARN_ON_ONCE(!excl_cntrs))
3243                 return;
3244
3245         xl = &excl_cntrs->states[tid];
3246
3247         xl->sched_started = true;
3248         /*
3249          * lock shared state until we are done scheduling
3250          * in stop_event_scheduling()
3251          * makes scheduling appear as a transaction
3252          */
3253         raw_spin_lock(&excl_cntrs->lock);
3254 }
3255
3256 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3257 {
3258         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3259         struct event_constraint *c = cpuc->event_constraint[idx];
3260         struct intel_excl_states *xl;
3261         int tid = cpuc->excl_thread_id;
3262
3263         if (cpuc->is_fake || !is_ht_workaround_enabled())
3264                 return;
3265
3266         if (WARN_ON_ONCE(!excl_cntrs))
3267                 return;
3268
3269         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3270                 return;
3271
3272         xl = &excl_cntrs->states[tid];
3273
3274         lockdep_assert_held(&excl_cntrs->lock);
3275
3276         if (c->flags & PERF_X86_EVENT_EXCL)
3277                 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3278         else
3279                 xl->state[cntr] = INTEL_EXCL_SHARED;
3280 }
3281
3282 static void
3283 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3284 {
3285         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3286         struct intel_excl_states *xl;
3287         int tid = cpuc->excl_thread_id;
3288
3289         /*
3290          * nothing needed if in group validation mode
3291          */
3292         if (cpuc->is_fake || !is_ht_workaround_enabled())
3293                 return;
3294         /*
3295          * no exclusion needed
3296          */
3297         if (WARN_ON_ONCE(!excl_cntrs))
3298                 return;
3299
3300         xl = &excl_cntrs->states[tid];
3301
3302         xl->sched_started = false;
3303         /*
3304          * release shared state lock (acquired in intel_start_scheduling())
3305          */
3306         raw_spin_unlock(&excl_cntrs->lock);
3307 }
3308
3309 static struct event_constraint *
3310 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3311 {
3312         WARN_ON_ONCE(!cpuc->constraint_list);
3313
3314         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3315                 struct event_constraint *cx;
3316
3317                 /*
3318                  * grab pre-allocated constraint entry
3319                  */
3320                 cx = &cpuc->constraint_list[idx];
3321
3322                 /*
3323                  * initialize dynamic constraint
3324                  * with static constraint
3325                  */
3326                 *cx = *c;
3327
3328                 /*
3329                  * mark constraint as dynamic
3330                  */
3331                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3332                 c = cx;
3333         }
3334
3335         return c;
3336 }
3337
3338 static struct event_constraint *
3339 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3340                            int idx, struct event_constraint *c)
3341 {
3342         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3343         struct intel_excl_states *xlo;
3344         int tid = cpuc->excl_thread_id;
3345         int is_excl, i, w;
3346
3347         /*
3348          * validating a group does not require
3349          * enforcing cross-thread  exclusion
3350          */
3351         if (cpuc->is_fake || !is_ht_workaround_enabled())
3352                 return c;
3353
3354         /*
3355          * no exclusion needed
3356          */
3357         if (WARN_ON_ONCE(!excl_cntrs))
3358                 return c;
3359
3360         /*
3361          * because we modify the constraint, we need
3362          * to make a copy. Static constraints come
3363          * from static const tables.
3364          *
3365          * only needed when constraint has not yet
3366          * been cloned (marked dynamic)
3367          */
3368         c = dyn_constraint(cpuc, c, idx);
3369
3370         /*
3371          * From here on, the constraint is dynamic.
3372          * Either it was just allocated above, or it
3373          * was allocated during a earlier invocation
3374          * of this function
3375          */
3376
3377         /*
3378          * state of sibling HT
3379          */
3380         xlo = &excl_cntrs->states[tid ^ 1];
3381
3382         /*
3383          * event requires exclusive counter access
3384          * across HT threads
3385          */
3386         is_excl = c->flags & PERF_X86_EVENT_EXCL;
3387         if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3388                 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3389                 if (!cpuc->n_excl++)
3390                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3391         }
3392
3393         /*
3394          * Modify static constraint with current dynamic
3395          * state of thread
3396          *
3397          * EXCLUSIVE: sibling counter measuring exclusive event
3398          * SHARED   : sibling counter measuring non-exclusive event
3399          * UNUSED   : sibling counter unused
3400          */
3401         w = c->weight;
3402         for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3403                 /*
3404                  * exclusive event in sibling counter
3405                  * our corresponding counter cannot be used
3406                  * regardless of our event
3407                  */
3408                 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3409                         __clear_bit(i, c->idxmsk);
3410                         w--;
3411                         continue;
3412                 }
3413                 /*
3414                  * if measuring an exclusive event, sibling
3415                  * measuring non-exclusive, then counter cannot
3416                  * be used
3417                  */
3418                 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3419                         __clear_bit(i, c->idxmsk);
3420                         w--;
3421                         continue;
3422                 }
3423         }
3424
3425         /*
3426          * if we return an empty mask, then switch
3427          * back to static empty constraint to avoid
3428          * the cost of freeing later on
3429          */
3430         if (!w)
3431                 c = &emptyconstraint;
3432
3433         c->weight = w;
3434
3435         return c;
3436 }
3437
3438 static struct event_constraint *
3439 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3440                             struct perf_event *event)
3441 {
3442         struct event_constraint *c1, *c2;
3443
3444         c1 = cpuc->event_constraint[idx];
3445
3446         /*
3447          * first time only
3448          * - static constraint: no change across incremental scheduling calls
3449          * - dynamic constraint: handled by intel_get_excl_constraints()
3450          */
3451         c2 = __intel_get_event_constraints(cpuc, idx, event);
3452         if (c1) {
3453                 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3454                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3455                 c1->weight = c2->weight;
3456                 c2 = c1;
3457         }
3458
3459         if (cpuc->excl_cntrs)
3460                 return intel_get_excl_constraints(cpuc, event, idx, c2);
3461
3462         return c2;
3463 }
3464
3465 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3466                 struct perf_event *event)
3467 {
3468         struct hw_perf_event *hwc = &event->hw;
3469         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3470         int tid = cpuc->excl_thread_id;
3471         struct intel_excl_states *xl;
3472
3473         /*
3474          * nothing needed if in group validation mode
3475          */
3476         if (cpuc->is_fake)
3477                 return;
3478
3479         if (WARN_ON_ONCE(!excl_cntrs))
3480                 return;
3481
3482         if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3483                 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3484                 if (!--cpuc->n_excl)
3485                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3486         }
3487
3488         /*
3489          * If event was actually assigned, then mark the counter state as
3490          * unused now.
3491          */
3492         if (hwc->idx >= 0) {
3493                 xl = &excl_cntrs->states[tid];
3494
3495                 /*
3496                  * put_constraint may be called from x86_schedule_events()
3497                  * which already has the lock held so here make locking
3498                  * conditional.
3499                  */
3500                 if (!xl->sched_started)
3501                         raw_spin_lock(&excl_cntrs->lock);
3502
3503                 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3504
3505                 if (!xl->sched_started)
3506                         raw_spin_unlock(&excl_cntrs->lock);
3507         }
3508 }
3509
3510 static void
3511 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3512                                         struct perf_event *event)
3513 {
3514         struct hw_perf_event_extra *reg;
3515
3516         reg = &event->hw.extra_reg;
3517         if (reg->idx != EXTRA_REG_NONE)
3518                 __intel_shared_reg_put_constraints(cpuc, reg);
3519
3520         reg = &event->hw.branch_reg;
3521         if (reg->idx != EXTRA_REG_NONE)
3522                 __intel_shared_reg_put_constraints(cpuc, reg);
3523 }
3524
3525 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3526                                         struct perf_event *event)
3527 {
3528         intel_put_shared_regs_event_constraints(cpuc, event);
3529
3530         /*
3531          * is PMU has exclusive counter restrictions, then
3532          * all events are subject to and must call the
3533          * put_excl_constraints() routine
3534          */
3535         if (cpuc->excl_cntrs)
3536                 intel_put_excl_constraints(cpuc, event);
3537 }
3538
3539 static void intel_pebs_aliases_core2(struct perf_event *event)
3540 {
3541         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3542                 /*
3543                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3544                  * (0x003c) so that we can use it with PEBS.
3545                  *
3546                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3547                  * PEBS capable. However we can use INST_RETIRED.ANY_P
3548                  * (0x00c0), which is a PEBS capable event, to get the same
3549                  * count.
3550                  *
3551                  * INST_RETIRED.ANY_P counts the number of cycles that retires
3552                  * CNTMASK instructions. By setting CNTMASK to a value (16)
3553                  * larger than the maximum number of instructions that can be
3554                  * retired per cycle (4) and then inverting the condition, we
3555                  * count all cycles that retire 16 or less instructions, which
3556                  * is every cycle.
3557                  *
3558                  * Thereby we gain a PEBS capable cycle counter.
3559                  */
3560                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3561
3562                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3563                 event->hw.config = alt_config;
3564         }
3565 }
3566
3567 static void intel_pebs_aliases_snb(struct perf_event *event)
3568 {
3569         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3570                 /*
3571                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3572                  * (0x003c) so that we can use it with PEBS.
3573                  *
3574                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3575                  * PEBS capable. However we can use UOPS_RETIRED.ALL
3576                  * (0x01c2), which is a PEBS capable event, to get the same
3577                  * count.
3578                  *
3579                  * UOPS_RETIRED.ALL counts the number of cycles that retires
3580                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3581                  * larger than the maximum number of micro-ops that can be
3582                  * retired per cycle (4) and then inverting the condition, we
3583                  * count all cycles that retire 16 or less micro-ops, which
3584                  * is every cycle.
3585                  *
3586                  * Thereby we gain a PEBS capable cycle counter.
3587                  */
3588                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3589
3590                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3591                 event->hw.config = alt_config;
3592         }
3593 }
3594
3595 static void intel_pebs_aliases_precdist(struct perf_event *event)
3596 {
3597         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3598                 /*
3599                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3600                  * (0x003c) so that we can use it with PEBS.
3601                  *
3602                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3603                  * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3604                  * (0x01c0), which is a PEBS capable event, to get the same
3605                  * count.
3606                  *
3607                  * The PREC_DIST event has special support to minimize sample
3608                  * shadowing effects. One drawback is that it can be
3609                  * only programmed on counter 1, but that seems like an
3610                  * acceptable trade off.
3611                  */
3612                 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3613
3614                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3615                 event->hw.config = alt_config;
3616         }
3617 }
3618
3619 static void intel_pebs_aliases_ivb(struct perf_event *event)
3620 {
3621         if (event->attr.precise_ip < 3)
3622                 return intel_pebs_aliases_snb(event);
3623         return intel_pebs_aliases_precdist(event);
3624 }
3625
3626 static void intel_pebs_aliases_skl(struct perf_event *event)
3627 {
3628         if (event->attr.precise_ip < 3)
3629                 return intel_pebs_aliases_core2(event);
3630         return intel_pebs_aliases_precdist(event);
3631 }
3632
3633 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3634 {
3635         unsigned long flags = x86_pmu.large_pebs_flags;
3636
3637         if (event->attr.use_clockid)
3638                 flags &= ~PERF_SAMPLE_TIME;
3639         if (!event->attr.exclude_kernel)
3640                 flags &= ~PERF_SAMPLE_REGS_USER;
3641         if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3642                 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3643         return flags;
3644 }
3645
3646 static int intel_pmu_bts_config(struct perf_event *event)
3647 {
3648         struct perf_event_attr *attr = &event->attr;
3649
3650         if (unlikely(intel_pmu_has_bts(event))) {
3651                 /* BTS is not supported by this architecture. */
3652                 if (!x86_pmu.bts_active)
3653                         return -EOPNOTSUPP;
3654
3655                 /* BTS is currently only allowed for user-mode. */
3656                 if (!attr->exclude_kernel)
3657                         return -EOPNOTSUPP;
3658
3659                 /* BTS is not allowed for precise events. */
3660                 if (attr->precise_ip)
3661                         return -EOPNOTSUPP;
3662
3663                 /* disallow bts if conflicting events are present */
3664                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3665                         return -EBUSY;
3666
3667                 event->destroy = hw_perf_lbr_event_destroy;
3668         }
3669
3670         return 0;
3671 }
3672
3673 static int core_pmu_hw_config(struct perf_event *event)
3674 {
3675         int ret = x86_pmu_hw_config(event);
3676
3677         if (ret)
3678                 return ret;
3679
3680         return intel_pmu_bts_config(event);
3681 }
3682
3683 #define INTEL_TD_METRIC_AVAILABLE_MAX   (INTEL_TD_METRIC_RETIRING + \
3684                                          ((x86_pmu.num_topdown_events - 1) << 8))
3685
3686 static bool is_available_metric_event(struct perf_event *event)
3687 {
3688         return is_metric_event(event) &&
3689                 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3690 }
3691
3692 static inline bool is_mem_loads_event(struct perf_event *event)
3693 {
3694         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3695 }
3696
3697 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3698 {
3699         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3700 }
3701
3702 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3703 {
3704         if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3705                 return false;
3706
3707         if (is_hybrid())
3708                 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big;
3709
3710         return true;
3711 }
3712
3713 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3714 {
3715         union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3716
3717         return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3718 }
3719
3720 static int intel_pmu_hw_config(struct perf_event *event)
3721 {
3722         int ret = x86_pmu_hw_config(event);
3723
3724         if (ret)
3725                 return ret;
3726
3727         ret = intel_pmu_bts_config(event);
3728         if (ret)
3729                 return ret;
3730
3731         if (event->attr.precise_ip) {
3732                 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3733                         return -EINVAL;
3734
3735                 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3736                         event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3737                         if (!(event->attr.sample_type &
3738                               ~intel_pmu_large_pebs_flags(event))) {
3739                                 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3740                                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3741                         }
3742                 }
3743                 if (x86_pmu.pebs_aliases)
3744                         x86_pmu.pebs_aliases(event);
3745
3746                 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3747                         event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3748         }
3749
3750         if (needs_branch_stack(event)) {
3751                 ret = intel_pmu_setup_lbr_filter(event);
3752                 if (ret)
3753                         return ret;
3754                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3755
3756                 /*
3757                  * BTS is set up earlier in this path, so don't account twice
3758                  */
3759                 if (!unlikely(intel_pmu_has_bts(event))) {
3760                         /* disallow lbr if conflicting events are present */
3761                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3762                                 return -EBUSY;
3763
3764                         event->destroy = hw_perf_lbr_event_destroy;
3765                 }
3766         }
3767
3768         if (event->attr.aux_output) {
3769                 if (!event->attr.precise_ip)
3770                         return -EINVAL;
3771
3772                 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3773         }
3774
3775         if ((event->attr.type == PERF_TYPE_HARDWARE) ||
3776             (event->attr.type == PERF_TYPE_HW_CACHE))
3777                 return 0;
3778
3779         /*
3780          * Config Topdown slots and metric events
3781          *
3782          * The slots event on Fixed Counter 3 can support sampling,
3783          * which will be handled normally in x86_perf_event_update().
3784          *
3785          * Metric events don't support sampling and require being paired
3786          * with a slots event as group leader. When the slots event
3787          * is used in a metrics group, it too cannot support sampling.
3788          */
3789         if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
3790                 if (event->attr.config1 || event->attr.config2)
3791                         return -EINVAL;
3792
3793                 /*
3794                  * The TopDown metrics events and slots event don't
3795                  * support any filters.
3796                  */
3797                 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3798                         return -EINVAL;
3799
3800                 if (is_available_metric_event(event)) {
3801                         struct perf_event *leader = event->group_leader;
3802
3803                         /* The metric events don't support sampling. */
3804                         if (is_sampling_event(event))
3805                                 return -EINVAL;
3806
3807                         /* The metric events require a slots group leader. */
3808                         if (!is_slots_event(leader))
3809                                 return -EINVAL;
3810
3811                         /*
3812                          * The leader/SLOTS must not be a sampling event for
3813                          * metric use; hardware requires it starts at 0 when used
3814                          * in conjunction with MSR_PERF_METRICS.
3815                          */
3816                         if (is_sampling_event(leader))
3817                                 return -EINVAL;
3818
3819                         event->event_caps |= PERF_EV_CAP_SIBLING;
3820                         /*
3821                          * Only once we have a METRICs sibling do we
3822                          * need TopDown magic.
3823                          */
3824                         leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3825                         event->hw.flags  |= PERF_X86_EVENT_TOPDOWN;
3826                 }
3827         }
3828
3829         /*
3830          * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3831          * doesn't function quite right. As a work-around it needs to always be
3832          * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3833          * The actual count of this second event is irrelevant it just needs
3834          * to be active to make the first event function correctly.
3835          *
3836          * In a group, the auxiliary event must be in front of the load latency
3837          * event. The rule is to simplify the implementation of the check.
3838          * That's because perf cannot have a complete group at the moment.
3839          */
3840         if (require_mem_loads_aux_event(event) &&
3841             (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3842             is_mem_loads_event(event)) {
3843                 struct perf_event *leader = event->group_leader;
3844                 struct perf_event *sibling = NULL;
3845
3846                 if (!is_mem_loads_aux_event(leader)) {
3847                         for_each_sibling_event(sibling, leader) {
3848                                 if (is_mem_loads_aux_event(sibling))
3849                                         break;
3850                         }
3851                         if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
3852                                 return -ENODATA;
3853                 }
3854         }
3855
3856         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3857                 return 0;
3858
3859         if (x86_pmu.version < 3)
3860                 return -EINVAL;
3861
3862         ret = perf_allow_cpu(&event->attr);
3863         if (ret)
3864                 return ret;
3865
3866         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3867
3868         return 0;
3869 }
3870
3871 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3872 {
3873         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3874         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3875         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3876
3877         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3878         arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3879         arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3880         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3881                 arr[0].guest &= ~cpuc->pebs_enabled;
3882         else
3883                 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3884         *nr = 1;
3885
3886         if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3887                 /*
3888                  * If PMU counter has PEBS enabled it is not enough to
3889                  * disable counter on a guest entry since PEBS memory
3890                  * write can overshoot guest entry and corrupt guest
3891                  * memory. Disabling PEBS solves the problem.
3892                  *
3893                  * Don't do this if the CPU already enforces it.
3894                  */
3895                 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3896                 arr[1].host = cpuc->pebs_enabled;
3897                 arr[1].guest = 0;
3898                 *nr = 2;
3899         }
3900
3901         return arr;
3902 }
3903
3904 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3905 {
3906         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3907         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3908         int idx;
3909
3910         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
3911                 struct perf_event *event = cpuc->events[idx];
3912
3913                 arr[idx].msr = x86_pmu_config_addr(idx);
3914                 arr[idx].host = arr[idx].guest = 0;
3915
3916                 if (!test_bit(idx, cpuc->active_mask))
3917                         continue;
3918
3919                 arr[idx].host = arr[idx].guest =
3920                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3921
3922                 if (event->attr.exclude_host)
3923                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3924                 else if (event->attr.exclude_guest)
3925                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3926         }
3927
3928         *nr = x86_pmu.num_counters;
3929         return arr;
3930 }
3931
3932 static void core_pmu_enable_event(struct perf_event *event)
3933 {
3934         if (!event->attr.exclude_host)
3935                 x86_pmu_enable_event(event);
3936 }
3937
3938 static void core_pmu_enable_all(int added)
3939 {
3940         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3941         int idx;
3942
3943         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3944                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3945
3946                 if (!test_bit(idx, cpuc->active_mask) ||
3947                                 cpuc->events[idx]->attr.exclude_host)
3948                         continue;
3949
3950                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3951         }
3952 }
3953
3954 static int hsw_hw_config(struct perf_event *event)
3955 {
3956         int ret = intel_pmu_hw_config(event);
3957
3958         if (ret)
3959                 return ret;
3960         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3961                 return 0;
3962         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3963
3964         /*
3965          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3966          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3967          * this combination.
3968          */
3969         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3970              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3971               event->attr.precise_ip > 0))
3972                 return -EOPNOTSUPP;
3973
3974         if (event_is_checkpointed(event)) {
3975                 /*
3976                  * Sampling of checkpointed events can cause situations where
3977                  * the CPU constantly aborts because of a overflow, which is
3978                  * then checkpointed back and ignored. Forbid checkpointing
3979                  * for sampling.
3980                  *
3981                  * But still allow a long sampling period, so that perf stat
3982                  * from KVM works.
3983                  */
3984                 if (event->attr.sample_period > 0 &&
3985                     event->attr.sample_period < 0x7fffffff)
3986                         return -EOPNOTSUPP;
3987         }
3988         return 0;
3989 }
3990
3991 static struct event_constraint counter0_constraint =
3992                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3993
3994 static struct event_constraint counter2_constraint =
3995                         EVENT_CONSTRAINT(0, 0x4, 0);
3996
3997 static struct event_constraint fixed0_constraint =
3998                         FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3999
4000 static struct event_constraint fixed0_counter0_constraint =
4001                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4002
4003 static struct event_constraint *
4004 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4005                           struct perf_event *event)
4006 {
4007         struct event_constraint *c;
4008
4009         c = intel_get_event_constraints(cpuc, idx, event);
4010
4011         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4012         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4013                 if (c->idxmsk64 & (1U << 2))
4014                         return &counter2_constraint;
4015                 return &emptyconstraint;
4016         }
4017
4018         return c;
4019 }
4020
4021 static struct event_constraint *
4022 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4023                           struct perf_event *event)
4024 {
4025         /*
4026          * Fixed counter 0 has less skid.
4027          * Force instruction:ppp in Fixed counter 0
4028          */
4029         if ((event->attr.precise_ip == 3) &&
4030             constraint_match(&fixed0_constraint, event->hw.config))
4031                 return &fixed0_constraint;
4032
4033         return hsw_get_event_constraints(cpuc, idx, event);
4034 }
4035
4036 static struct event_constraint *
4037 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4038                           struct perf_event *event)
4039 {
4040         struct event_constraint *c;
4041
4042         c = icl_get_event_constraints(cpuc, idx, event);
4043
4044         /*
4045          * The :ppp indicates the Precise Distribution (PDist) facility, which
4046          * is only supported on the GP counter 0. If a :ppp event which is not
4047          * available on the GP counter 0, error out.
4048          * Exception: Instruction PDIR is only available on the fixed counter 0.
4049          */
4050         if ((event->attr.precise_ip == 3) &&
4051             !constraint_match(&fixed0_constraint, event->hw.config)) {
4052                 if (c->idxmsk64 & BIT_ULL(0))
4053                         return &counter0_constraint;
4054
4055                 return &emptyconstraint;
4056         }
4057
4058         return c;
4059 }
4060
4061 static struct event_constraint *
4062 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4063                           struct perf_event *event)
4064 {
4065         struct event_constraint *c;
4066
4067         /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4068         if (event->attr.precise_ip == 3)
4069                 return &counter0_constraint;
4070
4071         c = intel_get_event_constraints(cpuc, idx, event);
4072
4073         return c;
4074 }
4075
4076 static struct event_constraint *
4077 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4078                           struct perf_event *event)
4079 {
4080         struct event_constraint *c;
4081
4082         /*
4083          * :ppp means to do reduced skid PEBS,
4084          * which is available on PMC0 and fixed counter 0.
4085          */
4086         if (event->attr.precise_ip == 3) {
4087                 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4088                 if (constraint_match(&fixed0_constraint, event->hw.config))
4089                         return &fixed0_counter0_constraint;
4090
4091                 return &counter0_constraint;
4092         }
4093
4094         c = intel_get_event_constraints(cpuc, idx, event);
4095
4096         return c;
4097 }
4098
4099 static bool allow_tsx_force_abort = true;
4100
4101 static struct event_constraint *
4102 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4103                           struct perf_event *event)
4104 {
4105         struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4106
4107         /*
4108          * Without TFA we must not use PMC3.
4109          */
4110         if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4111                 c = dyn_constraint(cpuc, c, idx);
4112                 c->idxmsk64 &= ~(1ULL << 3);
4113                 c->weight--;
4114         }
4115
4116         return c;
4117 }
4118
4119 static struct event_constraint *
4120 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4121                           struct perf_event *event)
4122 {
4123         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4124
4125         if (pmu->cpu_type == hybrid_big)
4126                 return spr_get_event_constraints(cpuc, idx, event);
4127         else if (pmu->cpu_type == hybrid_small)
4128                 return tnt_get_event_constraints(cpuc, idx, event);
4129
4130         WARN_ON(1);
4131         return &emptyconstraint;
4132 }
4133
4134 static int adl_hw_config(struct perf_event *event)
4135 {
4136         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4137
4138         if (pmu->cpu_type == hybrid_big)
4139                 return hsw_hw_config(event);
4140         else if (pmu->cpu_type == hybrid_small)
4141                 return intel_pmu_hw_config(event);
4142
4143         WARN_ON(1);
4144         return -EOPNOTSUPP;
4145 }
4146
4147 static u8 adl_get_hybrid_cpu_type(void)
4148 {
4149         return hybrid_big;
4150 }
4151
4152 /*
4153  * Broadwell:
4154  *
4155  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4156  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4157  * the two to enforce a minimum period of 128 (the smallest value that has bits
4158  * 0-5 cleared and >= 100).
4159  *
4160  * Because of how the code in x86_perf_event_set_period() works, the truncation
4161  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4162  * to make up for the 'lost' events due to carrying the 'error' in period_left.
4163  *
4164  * Therefore the effective (average) period matches the requested period,
4165  * despite coarser hardware granularity.
4166  */
4167 static u64 bdw_limit_period(struct perf_event *event, u64 left)
4168 {
4169         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4170                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
4171                 if (left < 128)
4172                         left = 128;
4173                 left &= ~0x3fULL;
4174         }
4175         return left;
4176 }
4177
4178 static u64 nhm_limit_period(struct perf_event *event, u64 left)
4179 {
4180         return max(left, 32ULL);
4181 }
4182
4183 static u64 spr_limit_period(struct perf_event *event, u64 left)
4184 {
4185         if (event->attr.precise_ip == 3)
4186                 return max(left, 128ULL);
4187
4188         return left;
4189 }
4190
4191 PMU_FORMAT_ATTR(event,  "config:0-7"    );
4192 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
4193 PMU_FORMAT_ATTR(edge,   "config:18"     );
4194 PMU_FORMAT_ATTR(pc,     "config:19"     );
4195 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
4196 PMU_FORMAT_ATTR(inv,    "config:23"     );
4197 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
4198 PMU_FORMAT_ATTR(in_tx,  "config:32");
4199 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4200
4201 static struct attribute *intel_arch_formats_attr[] = {
4202         &format_attr_event.attr,
4203         &format_attr_umask.attr,
4204         &format_attr_edge.attr,
4205         &format_attr_pc.attr,
4206         &format_attr_inv.attr,
4207         &format_attr_cmask.attr,
4208         NULL,
4209 };
4210
4211 ssize_t intel_event_sysfs_show(char *page, u64 config)
4212 {
4213         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4214
4215         return x86_event_sysfs_show(page, config, event);
4216 }
4217
4218 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4219 {
4220         struct intel_shared_regs *regs;
4221         int i;
4222
4223         regs = kzalloc_node(sizeof(struct intel_shared_regs),
4224                             GFP_KERNEL, cpu_to_node(cpu));
4225         if (regs) {
4226                 /*
4227                  * initialize the locks to keep lockdep happy
4228                  */
4229                 for (i = 0; i < EXTRA_REG_MAX; i++)
4230                         raw_spin_lock_init(&regs->regs[i].lock);
4231
4232                 regs->core_id = -1;
4233         }
4234         return regs;
4235 }
4236
4237 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4238 {
4239         struct intel_excl_cntrs *c;
4240
4241         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4242                          GFP_KERNEL, cpu_to_node(cpu));
4243         if (c) {
4244                 raw_spin_lock_init(&c->lock);
4245                 c->core_id = -1;
4246         }
4247         return c;
4248 }
4249
4250
4251 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4252 {
4253         cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4254
4255         if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4256                 cpuc->shared_regs = allocate_shared_regs(cpu);
4257                 if (!cpuc->shared_regs)
4258                         goto err;
4259         }
4260
4261         if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4262                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4263
4264                 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4265                 if (!cpuc->constraint_list)
4266                         goto err_shared_regs;
4267         }
4268
4269         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4270                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4271                 if (!cpuc->excl_cntrs)
4272                         goto err_constraint_list;
4273
4274                 cpuc->excl_thread_id = 0;
4275         }
4276
4277         return 0;
4278
4279 err_constraint_list:
4280         kfree(cpuc->constraint_list);
4281         cpuc->constraint_list = NULL;
4282
4283 err_shared_regs:
4284         kfree(cpuc->shared_regs);
4285         cpuc->shared_regs = NULL;
4286
4287 err:
4288         return -ENOMEM;
4289 }
4290
4291 static int intel_pmu_cpu_prepare(int cpu)
4292 {
4293         return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4294 }
4295
4296 static void flip_smm_bit(void *data)
4297 {
4298         unsigned long set = *(unsigned long *)data;
4299
4300         if (set > 0) {
4301                 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4302                             DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4303         } else {
4304                 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4305                               DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4306         }
4307 }
4308
4309 static bool init_hybrid_pmu(int cpu)
4310 {
4311         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4312         u8 cpu_type = get_this_hybrid_cpu_type();
4313         struct x86_hybrid_pmu *pmu = NULL;
4314         int i;
4315
4316         if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
4317                 cpu_type = x86_pmu.get_hybrid_cpu_type();
4318
4319         for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
4320                 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) {
4321                         pmu = &x86_pmu.hybrid_pmu[i];
4322                         break;
4323                 }
4324         }
4325         if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
4326                 cpuc->pmu = NULL;
4327                 return false;
4328         }
4329
4330         /* Only check and dump the PMU information for the first CPU */
4331         if (!cpumask_empty(&pmu->supported_cpus))
4332                 goto end;
4333
4334         if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed))
4335                 return false;
4336
4337         pr_info("%s PMU driver: ", pmu->name);
4338
4339         if (pmu->intel_cap.pebs_output_pt_available)
4340                 pr_cont("PEBS-via-PT ");
4341
4342         pr_cont("\n");
4343
4344         x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed,
4345                              pmu->intel_ctrl);
4346
4347 end:
4348         cpumask_set_cpu(cpu, &pmu->supported_cpus);
4349         cpuc->pmu = &pmu->pmu;
4350
4351         x86_pmu_update_cpu_context(&pmu->pmu, cpu);
4352
4353         return true;
4354 }
4355
4356 static void intel_pmu_cpu_starting(int cpu)
4357 {
4358         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4359         int core_id = topology_core_id(cpu);
4360         int i;
4361
4362         if (is_hybrid() && !init_hybrid_pmu(cpu))
4363                 return;
4364
4365         init_debug_store_on_cpu(cpu);
4366         /*
4367          * Deal with CPUs that don't clear their LBRs on power-up.
4368          */
4369         intel_pmu_lbr_reset();
4370
4371         cpuc->lbr_sel = NULL;
4372
4373         if (x86_pmu.flags & PMU_FL_TFA) {
4374                 WARN_ON_ONCE(cpuc->tfa_shadow);
4375                 cpuc->tfa_shadow = ~0ULL;
4376                 intel_set_tfa(cpuc, false);
4377         }
4378
4379         if (x86_pmu.version > 1)
4380                 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4381
4382         /*
4383          * Disable perf metrics if any added CPU doesn't support it.
4384          *
4385          * Turn off the check for a hybrid architecture, because the
4386          * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
4387          * the architecture features. The perf metrics is a model-specific
4388          * feature for now. The corresponding bit should always be 0 on
4389          * a hybrid platform, e.g., Alder Lake.
4390          */
4391         if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
4392                 union perf_capabilities perf_cap;
4393
4394                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4395                 if (!perf_cap.perf_metrics) {
4396                         x86_pmu.intel_cap.perf_metrics = 0;
4397                         x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4398                 }
4399         }
4400
4401         if (!cpuc->shared_regs)
4402                 return;
4403
4404         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4405                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4406                         struct intel_shared_regs *pc;
4407
4408                         pc = per_cpu(cpu_hw_events, i).shared_regs;
4409                         if (pc && pc->core_id == core_id) {
4410                                 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4411                                 cpuc->shared_regs = pc;
4412                                 break;
4413                         }
4414                 }
4415                 cpuc->shared_regs->core_id = core_id;
4416                 cpuc->shared_regs->refcnt++;
4417         }
4418
4419         if (x86_pmu.lbr_sel_map)
4420                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4421
4422         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4423                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4424                         struct cpu_hw_events *sibling;
4425                         struct intel_excl_cntrs *c;
4426
4427                         sibling = &per_cpu(cpu_hw_events, i);
4428                         c = sibling->excl_cntrs;
4429                         if (c && c->core_id == core_id) {
4430                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4431                                 cpuc->excl_cntrs = c;
4432                                 if (!sibling->excl_thread_id)
4433                                         cpuc->excl_thread_id = 1;
4434                                 break;
4435                         }
4436                 }
4437                 cpuc->excl_cntrs->core_id = core_id;
4438                 cpuc->excl_cntrs->refcnt++;
4439         }
4440 }
4441
4442 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4443 {
4444         struct intel_excl_cntrs *c;
4445
4446         c = cpuc->excl_cntrs;
4447         if (c) {
4448                 if (c->core_id == -1 || --c->refcnt == 0)
4449                         kfree(c);
4450                 cpuc->excl_cntrs = NULL;
4451         }
4452
4453         kfree(cpuc->constraint_list);
4454         cpuc->constraint_list = NULL;
4455 }
4456
4457 static void intel_pmu_cpu_dying(int cpu)
4458 {
4459         fini_debug_store_on_cpu(cpu);
4460 }
4461
4462 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4463 {
4464         struct intel_shared_regs *pc;
4465
4466         pc = cpuc->shared_regs;
4467         if (pc) {
4468                 if (pc->core_id == -1 || --pc->refcnt == 0)
4469                         kfree(pc);
4470                 cpuc->shared_regs = NULL;
4471         }
4472
4473         free_excl_cntrs(cpuc);
4474 }
4475
4476 static void intel_pmu_cpu_dead(int cpu)
4477 {
4478         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4479
4480         intel_cpuc_finish(cpuc);
4481
4482         if (is_hybrid() && cpuc->pmu)
4483                 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
4484 }
4485
4486 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4487                                  bool sched_in)
4488 {
4489         intel_pmu_pebs_sched_task(ctx, sched_in);
4490         intel_pmu_lbr_sched_task(ctx, sched_in);
4491 }
4492
4493 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4494                                     struct perf_event_context *next)
4495 {
4496         intel_pmu_lbr_swap_task_ctx(prev, next);
4497 }
4498
4499 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4500 {
4501         return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4502 }
4503
4504 static int intel_pmu_aux_output_match(struct perf_event *event)
4505 {
4506         if (!x86_pmu.intel_cap.pebs_output_pt_available)
4507                 return 0;
4508
4509         return is_intel_pt_event(event);
4510 }
4511
4512 static int intel_pmu_filter_match(struct perf_event *event)
4513 {
4514         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4515         unsigned int cpu = smp_processor_id();
4516
4517         return cpumask_test_cpu(cpu, &pmu->supported_cpus);
4518 }
4519
4520 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4521
4522 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4523
4524 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4525
4526 static struct attribute *intel_arch3_formats_attr[] = {
4527         &format_attr_event.attr,
4528         &format_attr_umask.attr,
4529         &format_attr_edge.attr,
4530         &format_attr_pc.attr,
4531         &format_attr_any.attr,
4532         &format_attr_inv.attr,
4533         &format_attr_cmask.attr,
4534         NULL,
4535 };
4536
4537 static struct attribute *hsw_format_attr[] = {
4538         &format_attr_in_tx.attr,
4539         &format_attr_in_tx_cp.attr,
4540         &format_attr_offcore_rsp.attr,
4541         &format_attr_ldlat.attr,
4542         NULL
4543 };
4544
4545 static struct attribute *nhm_format_attr[] = {
4546         &format_attr_offcore_rsp.attr,
4547         &format_attr_ldlat.attr,
4548         NULL
4549 };
4550
4551 static struct attribute *slm_format_attr[] = {
4552         &format_attr_offcore_rsp.attr,
4553         NULL
4554 };
4555
4556 static struct attribute *skl_format_attr[] = {
4557         &format_attr_frontend.attr,
4558         NULL,
4559 };
4560
4561 static __initconst const struct x86_pmu core_pmu = {
4562         .name                   = "core",
4563         .handle_irq             = x86_pmu_handle_irq,
4564         .disable_all            = x86_pmu_disable_all,
4565         .enable_all             = core_pmu_enable_all,
4566         .enable                 = core_pmu_enable_event,
4567         .disable                = x86_pmu_disable_event,
4568         .hw_config              = core_pmu_hw_config,
4569         .schedule_events        = x86_schedule_events,
4570         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4571         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4572         .event_map              = intel_pmu_event_map,
4573         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4574         .apic                   = 1,
4575         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4576
4577         /*
4578          * Intel PMCs cannot be accessed sanely above 32-bit width,
4579          * so we install an artificial 1<<31 period regardless of
4580          * the generic event period:
4581          */
4582         .max_period             = (1ULL<<31) - 1,
4583         .get_event_constraints  = intel_get_event_constraints,
4584         .put_event_constraints  = intel_put_event_constraints,
4585         .event_constraints      = intel_core_event_constraints,
4586         .guest_get_msrs         = core_guest_get_msrs,
4587         .format_attrs           = intel_arch_formats_attr,
4588         .events_sysfs_show      = intel_event_sysfs_show,
4589
4590         /*
4591          * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4592          * together with PMU version 1 and thus be using core_pmu with
4593          * shared_regs. We need following callbacks here to allocate
4594          * it properly.
4595          */
4596         .cpu_prepare            = intel_pmu_cpu_prepare,
4597         .cpu_starting           = intel_pmu_cpu_starting,
4598         .cpu_dying              = intel_pmu_cpu_dying,
4599         .cpu_dead               = intel_pmu_cpu_dead,
4600
4601         .check_period           = intel_pmu_check_period,
4602
4603         .lbr_reset              = intel_pmu_lbr_reset_64,
4604         .lbr_read               = intel_pmu_lbr_read_64,
4605         .lbr_save               = intel_pmu_lbr_save,
4606         .lbr_restore            = intel_pmu_lbr_restore,
4607 };
4608
4609 static __initconst const struct x86_pmu intel_pmu = {
4610         .name                   = "Intel",
4611         .handle_irq             = intel_pmu_handle_irq,
4612         .disable_all            = intel_pmu_disable_all,
4613         .enable_all             = intel_pmu_enable_all,
4614         .enable                 = intel_pmu_enable_event,
4615         .disable                = intel_pmu_disable_event,
4616         .add                    = intel_pmu_add_event,
4617         .del                    = intel_pmu_del_event,
4618         .read                   = intel_pmu_read_event,
4619         .hw_config              = intel_pmu_hw_config,
4620         .schedule_events        = x86_schedule_events,
4621         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4622         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4623         .event_map              = intel_pmu_event_map,
4624         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4625         .apic                   = 1,
4626         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4627         /*
4628          * Intel PMCs cannot be accessed sanely above 32 bit width,
4629          * so we install an artificial 1<<31 period regardless of
4630          * the generic event period:
4631          */
4632         .max_period             = (1ULL << 31) - 1,
4633         .get_event_constraints  = intel_get_event_constraints,
4634         .put_event_constraints  = intel_put_event_constraints,
4635         .pebs_aliases           = intel_pebs_aliases_core2,
4636
4637         .format_attrs           = intel_arch3_formats_attr,
4638         .events_sysfs_show      = intel_event_sysfs_show,
4639
4640         .cpu_prepare            = intel_pmu_cpu_prepare,
4641         .cpu_starting           = intel_pmu_cpu_starting,
4642         .cpu_dying              = intel_pmu_cpu_dying,
4643         .cpu_dead               = intel_pmu_cpu_dead,
4644
4645         .guest_get_msrs         = intel_guest_get_msrs,
4646         .sched_task             = intel_pmu_sched_task,
4647         .swap_task_ctx          = intel_pmu_swap_task_ctx,
4648
4649         .check_period           = intel_pmu_check_period,
4650
4651         .aux_output_match       = intel_pmu_aux_output_match,
4652
4653         .lbr_reset              = intel_pmu_lbr_reset_64,
4654         .lbr_read               = intel_pmu_lbr_read_64,
4655         .lbr_save               = intel_pmu_lbr_save,
4656         .lbr_restore            = intel_pmu_lbr_restore,
4657
4658         /*
4659          * SMM has access to all 4 rings and while traditionally SMM code only
4660          * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
4661          *
4662          * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
4663          * between SMM or not, this results in what should be pure userspace
4664          * counters including SMM data.
4665          *
4666          * This is a clear privilege issue, therefore globally disable
4667          * counting SMM by default.
4668          */
4669         .attr_freeze_on_smi     = 1,
4670 };
4671
4672 static __init void intel_clovertown_quirk(void)
4673 {
4674         /*
4675          * PEBS is unreliable due to:
4676          *
4677          *   AJ67  - PEBS may experience CPL leaks
4678          *   AJ68  - PEBS PMI may be delayed by one event
4679          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4680          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4681          *
4682          * AJ67 could be worked around by restricting the OS/USR flags.
4683          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4684          *
4685          * AJ106 could possibly be worked around by not allowing LBR
4686          *       usage from PEBS, including the fixup.
4687          * AJ68  could possibly be worked around by always programming
4688          *       a pebs_event_reset[0] value and coping with the lost events.
4689          *
4690          * But taken together it might just make sense to not enable PEBS on
4691          * these chips.
4692          */
4693         pr_warn("PEBS disabled due to CPU errata\n");
4694         x86_pmu.pebs = 0;
4695         x86_pmu.pebs_constraints = NULL;
4696 }
4697
4698 static const struct x86_cpu_desc isolation_ucodes[] = {
4699         INTEL_CPU_DESC(INTEL_FAM6_HASWELL,               3, 0x0000001f),
4700         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,             1, 0x0000001e),
4701         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,             1, 0x00000015),
4702         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             2, 0x00000037),
4703         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             4, 0x0000000a),
4704         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,             4, 0x00000023),
4705         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,           1, 0x00000014),
4706         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           2, 0x00000010),
4707         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           3, 0x07000009),
4708         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           4, 0x0f000009),
4709         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           5, 0x0e000002),
4710         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,           1, 0x0b000014),
4711         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             3, 0x00000021),
4712         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             4, 0x00000000),
4713         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             5, 0x00000000),
4714         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             6, 0x00000000),
4715         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             7, 0x00000000),
4716         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,            11, 0x00000000),
4717         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L,             3, 0x0000007c),
4718         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE,               3, 0x0000007c),
4719         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,              9, 0x0000004e),
4720         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,            9, 0x0000004e),
4721         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           10, 0x0000004e),
4722         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           11, 0x0000004e),
4723         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           12, 0x0000004e),
4724         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             10, 0x0000004e),
4725         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             11, 0x0000004e),
4726         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             12, 0x0000004e),
4727         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             13, 0x0000004e),
4728         {}
4729 };
4730
4731 static void intel_check_pebs_isolation(void)
4732 {
4733         x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4734 }
4735
4736 static __init void intel_pebs_isolation_quirk(void)
4737 {
4738         WARN_ON_ONCE(x86_pmu.check_microcode);
4739         x86_pmu.check_microcode = intel_check_pebs_isolation;
4740         intel_check_pebs_isolation();
4741 }
4742
4743 static const struct x86_cpu_desc pebs_ucodes[] = {
4744         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE,          7, 0x00000028),
4745         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        6, 0x00000618),
4746         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        7, 0x0000070c),
4747         {}
4748 };
4749
4750 static bool intel_snb_pebs_broken(void)
4751 {
4752         return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4753 }
4754
4755 static void intel_snb_check_microcode(void)
4756 {
4757         if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4758                 return;
4759
4760         /*
4761          * Serialized by the microcode lock..
4762          */
4763         if (x86_pmu.pebs_broken) {
4764                 pr_info("PEBS enabled due to microcode update\n");
4765                 x86_pmu.pebs_broken = 0;
4766         } else {
4767                 pr_info("PEBS disabled due to CPU errata/*(DEBLOBBED)*/\n");
4768                 x86_pmu.pebs_broken = 1;
4769         }
4770 }
4771
4772 static bool is_lbr_from(unsigned long msr)
4773 {
4774         unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4775
4776         return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4777 }
4778
4779 /*
4780  * Under certain circumstances, access certain MSR may cause #GP.
4781  * The function tests if the input MSR can be safely accessed.
4782  */
4783 static bool check_msr(unsigned long msr, u64 mask)
4784 {
4785         u64 val_old, val_new, val_tmp;
4786
4787         /*
4788          * Disable the check for real HW, so we don't
4789          * mess with potentially enabled registers:
4790          */
4791         if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4792                 return true;
4793
4794         /*
4795          * Read the current value, change it and read it back to see if it
4796          * matches, this is needed to detect certain hardware emulators
4797          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4798          */
4799         if (rdmsrl_safe(msr, &val_old))
4800                 return false;
4801
4802         /*
4803          * Only change the bits which can be updated by wrmsrl.
4804          */
4805         val_tmp = val_old ^ mask;
4806
4807         if (is_lbr_from(msr))
4808                 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4809
4810         if (wrmsrl_safe(msr, val_tmp) ||
4811             rdmsrl_safe(msr, &val_new))
4812                 return false;
4813
4814         /*
4815          * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4816          * should equal rdmsrl()'s even with the quirk.
4817          */
4818         if (val_new != val_tmp)
4819                 return false;
4820
4821         if (is_lbr_from(msr))
4822                 val_old = lbr_from_signext_quirk_wr(val_old);
4823
4824         /* Here it's sure that the MSR can be safely accessed.
4825          * Restore the old value and return.
4826          */
4827         wrmsrl(msr, val_old);
4828
4829         return true;
4830 }
4831
4832 static __init void intel_sandybridge_quirk(void)
4833 {
4834         x86_pmu.check_microcode = intel_snb_check_microcode;
4835         cpus_read_lock();
4836         intel_snb_check_microcode();
4837         cpus_read_unlock();
4838 }
4839
4840 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4841         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4842         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4843         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4844         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4845         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4846         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4847         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4848 };
4849
4850 static __init void intel_arch_events_quirk(void)
4851 {
4852         int bit;
4853
4854         /* disable event that reported as not present by cpuid */
4855         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4856                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4857                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4858                         intel_arch_events_map[bit].name);
4859         }
4860 }
4861
4862 static __init void intel_nehalem_quirk(void)
4863 {
4864         union cpuid10_ebx ebx;
4865
4866         ebx.full = x86_pmu.events_maskl;
4867         if (ebx.split.no_branch_misses_retired) {
4868                 /*
4869                  * Erratum AAJ80 detected, we work it around by using
4870                  * the BR_MISP_EXEC.ANY event. This will over-count
4871                  * branch-misses, but it's still much better than the
4872                  * architectural event which is often completely bogus:
4873                  */
4874                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4875                 ebx.split.no_branch_misses_retired = 0;
4876                 x86_pmu.events_maskl = ebx.full;
4877                 pr_info("CPU erratum AAJ80 worked around\n");
4878         }
4879 }
4880
4881 /*
4882  * enable software workaround for errata:
4883  * SNB: BJ122
4884  * IVB: BV98
4885  * HSW: HSD29
4886  *
4887  * Only needed when HT is enabled. However detecting
4888  * if HT is enabled is difficult (model specific). So instead,
4889  * we enable the workaround in the early boot, and verify if
4890  * it is needed in a later initcall phase once we have valid
4891  * topology information to check if HT is actually enabled
4892  */
4893 static __init void intel_ht_bug(void)
4894 {
4895         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4896
4897         x86_pmu.start_scheduling = intel_start_scheduling;
4898         x86_pmu.commit_scheduling = intel_commit_scheduling;
4899         x86_pmu.stop_scheduling = intel_stop_scheduling;
4900 }
4901
4902 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
4903 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
4904
4905 /* Haswell special events */
4906 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
4907 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
4908 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
4909 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
4910 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
4911 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
4912 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
4913 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
4914 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
4915 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
4916 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
4917 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
4918
4919 static struct attribute *hsw_events_attrs[] = {
4920         EVENT_PTR(td_slots_issued),
4921         EVENT_PTR(td_slots_retired),
4922         EVENT_PTR(td_fetch_bubbles),
4923         EVENT_PTR(td_total_slots),
4924         EVENT_PTR(td_total_slots_scale),
4925         EVENT_PTR(td_recovery_bubbles),
4926         EVENT_PTR(td_recovery_bubbles_scale),
4927         NULL
4928 };
4929
4930 static struct attribute *hsw_mem_events_attrs[] = {
4931         EVENT_PTR(mem_ld_hsw),
4932         EVENT_PTR(mem_st_hsw),
4933         NULL,
4934 };
4935
4936 static struct attribute *hsw_tsx_events_attrs[] = {
4937         EVENT_PTR(tx_start),
4938         EVENT_PTR(tx_commit),
4939         EVENT_PTR(tx_abort),
4940         EVENT_PTR(tx_capacity),
4941         EVENT_PTR(tx_conflict),
4942         EVENT_PTR(el_start),
4943         EVENT_PTR(el_commit),
4944         EVENT_PTR(el_abort),
4945         EVENT_PTR(el_capacity),
4946         EVENT_PTR(el_conflict),
4947         EVENT_PTR(cycles_t),
4948         EVENT_PTR(cycles_ct),
4949         NULL
4950 };
4951
4952 EVENT_ATTR_STR(tx-capacity-read,  tx_capacity_read,  "event=0x54,umask=0x80");
4953 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4954 EVENT_ATTR_STR(el-capacity-read,  el_capacity_read,  "event=0x54,umask=0x80");
4955 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4956
4957 static struct attribute *icl_events_attrs[] = {
4958         EVENT_PTR(mem_ld_hsw),
4959         EVENT_PTR(mem_st_hsw),
4960         NULL,
4961 };
4962
4963 static struct attribute *icl_td_events_attrs[] = {
4964         EVENT_PTR(slots),
4965         EVENT_PTR(td_retiring),
4966         EVENT_PTR(td_bad_spec),
4967         EVENT_PTR(td_fe_bound),
4968         EVENT_PTR(td_be_bound),
4969         NULL,
4970 };
4971
4972 static struct attribute *icl_tsx_events_attrs[] = {
4973         EVENT_PTR(tx_start),
4974         EVENT_PTR(tx_abort),
4975         EVENT_PTR(tx_commit),
4976         EVENT_PTR(tx_capacity_read),
4977         EVENT_PTR(tx_capacity_write),
4978         EVENT_PTR(tx_conflict),
4979         EVENT_PTR(el_start),
4980         EVENT_PTR(el_abort),
4981         EVENT_PTR(el_commit),
4982         EVENT_PTR(el_capacity_read),
4983         EVENT_PTR(el_capacity_write),
4984         EVENT_PTR(el_conflict),
4985         EVENT_PTR(cycles_t),
4986         EVENT_PTR(cycles_ct),
4987         NULL,
4988 };
4989
4990
4991 EVENT_ATTR_STR(mem-stores,      mem_st_spr,     "event=0xcd,umask=0x2");
4992 EVENT_ATTR_STR(mem-loads-aux,   mem_ld_aux,     "event=0x03,umask=0x82");
4993
4994 static struct attribute *spr_events_attrs[] = {
4995         EVENT_PTR(mem_ld_hsw),
4996         EVENT_PTR(mem_st_spr),
4997         EVENT_PTR(mem_ld_aux),
4998         NULL,
4999 };
5000
5001 static struct attribute *spr_td_events_attrs[] = {
5002         EVENT_PTR(slots),
5003         EVENT_PTR(td_retiring),
5004         EVENT_PTR(td_bad_spec),
5005         EVENT_PTR(td_fe_bound),
5006         EVENT_PTR(td_be_bound),
5007         EVENT_PTR(td_heavy_ops),
5008         EVENT_PTR(td_br_mispredict),
5009         EVENT_PTR(td_fetch_lat),
5010         EVENT_PTR(td_mem_bound),
5011         NULL,
5012 };
5013
5014 static struct attribute *spr_tsx_events_attrs[] = {
5015         EVENT_PTR(tx_start),
5016         EVENT_PTR(tx_abort),
5017         EVENT_PTR(tx_commit),
5018         EVENT_PTR(tx_capacity_read),
5019         EVENT_PTR(tx_capacity_write),
5020         EVENT_PTR(tx_conflict),
5021         EVENT_PTR(cycles_t),
5022         EVENT_PTR(cycles_ct),
5023         NULL,
5024 };
5025
5026 static ssize_t freeze_on_smi_show(struct device *cdev,
5027                                   struct device_attribute *attr,
5028                                   char *buf)
5029 {
5030         return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5031 }
5032
5033 static DEFINE_MUTEX(freeze_on_smi_mutex);
5034
5035 static ssize_t freeze_on_smi_store(struct device *cdev,
5036                                    struct device_attribute *attr,
5037                                    const char *buf, size_t count)
5038 {
5039         unsigned long val;
5040         ssize_t ret;
5041
5042         ret = kstrtoul(buf, 0, &val);
5043         if (ret)
5044                 return ret;
5045
5046         if (val > 1)
5047                 return -EINVAL;
5048
5049         mutex_lock(&freeze_on_smi_mutex);
5050
5051         if (x86_pmu.attr_freeze_on_smi == val)
5052                 goto done;
5053
5054         x86_pmu.attr_freeze_on_smi = val;
5055
5056         cpus_read_lock();
5057         on_each_cpu(flip_smm_bit, &val, 1);
5058         cpus_read_unlock();
5059 done:
5060         mutex_unlock(&freeze_on_smi_mutex);
5061
5062         return count;
5063 }
5064
5065 static void update_tfa_sched(void *ignored)
5066 {
5067         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5068
5069         /*
5070          * check if PMC3 is used
5071          * and if so force schedule out for all event types all contexts
5072          */
5073         if (test_bit(3, cpuc->active_mask))
5074                 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5075 }
5076
5077 static ssize_t show_sysctl_tfa(struct device *cdev,
5078                               struct device_attribute *attr,
5079                               char *buf)
5080 {
5081         return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5082 }
5083
5084 static ssize_t set_sysctl_tfa(struct device *cdev,
5085                               struct device_attribute *attr,
5086                               const char *buf, size_t count)
5087 {
5088         bool val;
5089         ssize_t ret;
5090
5091         ret = kstrtobool(buf, &val);
5092         if (ret)
5093                 return ret;
5094
5095         /* no change */
5096         if (val == allow_tsx_force_abort)
5097                 return count;
5098
5099         allow_tsx_force_abort = val;
5100
5101         cpus_read_lock();
5102         on_each_cpu(update_tfa_sched, NULL, 1);
5103         cpus_read_unlock();
5104
5105         return count;
5106 }
5107
5108
5109 static DEVICE_ATTR_RW(freeze_on_smi);
5110
5111 static ssize_t branches_show(struct device *cdev,
5112                              struct device_attribute *attr,
5113                              char *buf)
5114 {
5115         return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5116 }
5117
5118 static DEVICE_ATTR_RO(branches);
5119
5120 static struct attribute *lbr_attrs[] = {
5121         &dev_attr_branches.attr,
5122         NULL
5123 };
5124
5125 static char pmu_name_str[30];
5126
5127 static ssize_t pmu_name_show(struct device *cdev,
5128                              struct device_attribute *attr,
5129                              char *buf)
5130 {
5131         return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
5132 }
5133
5134 static DEVICE_ATTR_RO(pmu_name);
5135
5136 static struct attribute *intel_pmu_caps_attrs[] = {
5137        &dev_attr_pmu_name.attr,
5138        NULL
5139 };
5140
5141 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5142                    show_sysctl_tfa,
5143                    set_sysctl_tfa);
5144
5145 static struct attribute *intel_pmu_attrs[] = {
5146         &dev_attr_freeze_on_smi.attr,
5147         &dev_attr_allow_tsx_force_abort.attr,
5148         NULL,
5149 };
5150
5151 static umode_t
5152 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5153 {
5154         return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5155 }
5156
5157 static umode_t
5158 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5159 {
5160         return x86_pmu.pebs ? attr->mode : 0;
5161 }
5162
5163 static umode_t
5164 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5165 {
5166         return x86_pmu.lbr_nr ? attr->mode : 0;
5167 }
5168
5169 static umode_t
5170 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5171 {
5172         return x86_pmu.version >= 2 ? attr->mode : 0;
5173 }
5174
5175 static umode_t
5176 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5177 {
5178         if (attr == &dev_attr_allow_tsx_force_abort.attr)
5179                 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5180
5181         return attr->mode;
5182 }
5183
5184 static struct attribute_group group_events_td  = {
5185         .name = "events",
5186 };
5187
5188 static struct attribute_group group_events_mem = {
5189         .name       = "events",
5190         .is_visible = pebs_is_visible,
5191 };
5192
5193 static struct attribute_group group_events_tsx = {
5194         .name       = "events",
5195         .is_visible = tsx_is_visible,
5196 };
5197
5198 static struct attribute_group group_caps_gen = {
5199         .name  = "caps",
5200         .attrs = intel_pmu_caps_attrs,
5201 };
5202
5203 static struct attribute_group group_caps_lbr = {
5204         .name       = "caps",
5205         .attrs      = lbr_attrs,
5206         .is_visible = lbr_is_visible,
5207 };
5208
5209 static struct attribute_group group_format_extra = {
5210         .name       = "format",
5211         .is_visible = exra_is_visible,
5212 };
5213
5214 static struct attribute_group group_format_extra_skl = {
5215         .name       = "format",
5216         .is_visible = exra_is_visible,
5217 };
5218
5219 static struct attribute_group group_default = {
5220         .attrs      = intel_pmu_attrs,
5221         .is_visible = default_is_visible,
5222 };
5223
5224 static const struct attribute_group *attr_update[] = {
5225         &group_events_td,
5226         &group_events_mem,
5227         &group_events_tsx,
5228         &group_caps_gen,
5229         &group_caps_lbr,
5230         &group_format_extra,
5231         &group_format_extra_skl,
5232         &group_default,
5233         NULL,
5234 };
5235
5236 EVENT_ATTR_STR_HYBRID(slots,                 slots_adl,        "event=0x00,umask=0x4",                       hybrid_big);
5237 EVENT_ATTR_STR_HYBRID(topdown-retiring,      td_retiring_adl,  "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
5238 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,      td_bad_spec_adl,  "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
5239 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,      td_fe_bound_adl,  "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
5240 EVENT_ATTR_STR_HYBRID(topdown-be-bound,      td_be_bound_adl,  "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
5241 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops,     td_heavy_ops_adl, "event=0x00,umask=0x84",                      hybrid_big);
5242 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl,    "event=0x00,umask=0x85",                      hybrid_big);
5243 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat,     td_fetch_lat_adl, "event=0x00,umask=0x86",                      hybrid_big);
5244 EVENT_ATTR_STR_HYBRID(topdown-mem-bound,     td_mem_bound_adl, "event=0x00,umask=0x87",                      hybrid_big);
5245
5246 static struct attribute *adl_hybrid_events_attrs[] = {
5247         EVENT_PTR(slots_adl),
5248         EVENT_PTR(td_retiring_adl),
5249         EVENT_PTR(td_bad_spec_adl),
5250         EVENT_PTR(td_fe_bound_adl),
5251         EVENT_PTR(td_be_bound_adl),
5252         EVENT_PTR(td_heavy_ops_adl),
5253         EVENT_PTR(td_br_mis_adl),
5254         EVENT_PTR(td_fetch_lat_adl),
5255         EVENT_PTR(td_mem_bound_adl),
5256         NULL,
5257 };
5258
5259 /* Must be in IDX order */
5260 EVENT_ATTR_STR_HYBRID(mem-loads,     mem_ld_adl,     "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
5261 EVENT_ATTR_STR_HYBRID(mem-stores,    mem_st_adl,     "event=0xd0,umask=0x6;event=0xcd,umask=0x2",                 hybrid_big_small);
5262 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82",                                     hybrid_big);
5263
5264 static struct attribute *adl_hybrid_mem_attrs[] = {
5265         EVENT_PTR(mem_ld_adl),
5266         EVENT_PTR(mem_st_adl),
5267         EVENT_PTR(mem_ld_aux_adl),
5268         NULL,
5269 };
5270
5271 EVENT_ATTR_STR_HYBRID(tx-start,          tx_start_adl,          "event=0xc9,umask=0x1",          hybrid_big);
5272 EVENT_ATTR_STR_HYBRID(tx-commit,         tx_commit_adl,         "event=0xc9,umask=0x2",          hybrid_big);
5273 EVENT_ATTR_STR_HYBRID(tx-abort,          tx_abort_adl,          "event=0xc9,umask=0x4",          hybrid_big);
5274 EVENT_ATTR_STR_HYBRID(tx-conflict,       tx_conflict_adl,       "event=0x54,umask=0x1",          hybrid_big);
5275 EVENT_ATTR_STR_HYBRID(cycles-t,          cycles_t_adl,          "event=0x3c,in_tx=1",            hybrid_big);
5276 EVENT_ATTR_STR_HYBRID(cycles-ct,         cycles_ct_adl,         "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
5277 EVENT_ATTR_STR_HYBRID(tx-capacity-read,  tx_capacity_read_adl,  "event=0x54,umask=0x80",         hybrid_big);
5278 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2",          hybrid_big);
5279
5280 static struct attribute *adl_hybrid_tsx_attrs[] = {
5281         EVENT_PTR(tx_start_adl),
5282         EVENT_PTR(tx_abort_adl),
5283         EVENT_PTR(tx_commit_adl),
5284         EVENT_PTR(tx_capacity_read_adl),
5285         EVENT_PTR(tx_capacity_write_adl),
5286         EVENT_PTR(tx_conflict_adl),
5287         EVENT_PTR(cycles_t_adl),
5288         EVENT_PTR(cycles_ct_adl),
5289         NULL,
5290 };
5291
5292 FORMAT_ATTR_HYBRID(in_tx,       hybrid_big);
5293 FORMAT_ATTR_HYBRID(in_tx_cp,    hybrid_big);
5294 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
5295 FORMAT_ATTR_HYBRID(ldlat,       hybrid_big_small);
5296 FORMAT_ATTR_HYBRID(frontend,    hybrid_big);
5297
5298 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
5299         FORMAT_HYBRID_PTR(in_tx),
5300         FORMAT_HYBRID_PTR(in_tx_cp),
5301         FORMAT_HYBRID_PTR(offcore_rsp),
5302         FORMAT_HYBRID_PTR(ldlat),
5303         FORMAT_HYBRID_PTR(frontend),
5304         NULL,
5305 };
5306
5307 static struct attribute *adl_hybrid_extra_attr[] = {
5308         FORMAT_HYBRID_PTR(offcore_rsp),
5309         FORMAT_HYBRID_PTR(ldlat),
5310         FORMAT_HYBRID_PTR(frontend),
5311         NULL,
5312 };
5313
5314 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
5315 {
5316         struct device *dev = kobj_to_dev(kobj);
5317         struct x86_hybrid_pmu *pmu =
5318                 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5319         struct perf_pmu_events_hybrid_attr *pmu_attr =
5320                 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
5321
5322         return pmu->cpu_type & pmu_attr->pmu_type;
5323 }
5324
5325 static umode_t hybrid_events_is_visible(struct kobject *kobj,
5326                                         struct attribute *attr, int i)
5327 {
5328         return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
5329 }
5330
5331 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
5332 {
5333         int cpu = cpumask_first(&pmu->supported_cpus);
5334
5335         return (cpu >= nr_cpu_ids) ? -1 : cpu;
5336 }
5337
5338 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
5339                                      struct attribute *attr, int i)
5340 {
5341         struct device *dev = kobj_to_dev(kobj);
5342         struct x86_hybrid_pmu *pmu =
5343                  container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5344         int cpu = hybrid_find_supported_cpu(pmu);
5345
5346         return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
5347 }
5348
5349 static umode_t hybrid_format_is_visible(struct kobject *kobj,
5350                                         struct attribute *attr, int i)
5351 {
5352         struct device *dev = kobj_to_dev(kobj);
5353         struct x86_hybrid_pmu *pmu =
5354                 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5355         struct perf_pmu_format_hybrid_attr *pmu_attr =
5356                 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
5357         int cpu = hybrid_find_supported_cpu(pmu);
5358
5359         return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0;
5360 }
5361
5362 static struct attribute_group hybrid_group_events_td  = {
5363         .name           = "events",
5364         .is_visible     = hybrid_events_is_visible,
5365 };
5366
5367 static struct attribute_group hybrid_group_events_mem = {
5368         .name           = "events",
5369         .is_visible     = hybrid_events_is_visible,
5370 };
5371
5372 static struct attribute_group hybrid_group_events_tsx = {
5373         .name           = "events",
5374         .is_visible     = hybrid_tsx_is_visible,
5375 };
5376
5377 static struct attribute_group hybrid_group_format_extra = {
5378         .name           = "format",
5379         .is_visible     = hybrid_format_is_visible,
5380 };
5381
5382 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
5383                                           struct device_attribute *attr,
5384                                           char *buf)
5385 {
5386         struct x86_hybrid_pmu *pmu =
5387                 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5388
5389         return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
5390 }
5391
5392 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
5393 static struct attribute *intel_hybrid_cpus_attrs[] = {
5394         &dev_attr_cpus.attr,
5395         NULL,
5396 };
5397
5398 static struct attribute_group hybrid_group_cpus = {
5399         .attrs          = intel_hybrid_cpus_attrs,
5400 };
5401
5402 static const struct attribute_group *hybrid_attr_update[] = {
5403         &hybrid_group_events_td,
5404         &hybrid_group_events_mem,
5405         &hybrid_group_events_tsx,
5406         &group_caps_gen,
5407         &group_caps_lbr,
5408         &hybrid_group_format_extra,
5409         &group_default,
5410         &hybrid_group_cpus,
5411         NULL,
5412 };
5413
5414 static struct attribute *empty_attrs;
5415
5416 static void intel_pmu_check_num_counters(int *num_counters,
5417                                          int *num_counters_fixed,
5418                                          u64 *intel_ctrl, u64 fixed_mask)
5419 {
5420         if (*num_counters > INTEL_PMC_MAX_GENERIC) {
5421                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5422                      *num_counters, INTEL_PMC_MAX_GENERIC);
5423                 *num_counters = INTEL_PMC_MAX_GENERIC;
5424         }
5425         *intel_ctrl = (1ULL << *num_counters) - 1;
5426
5427         if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5428                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5429                      *num_counters_fixed, INTEL_PMC_MAX_FIXED);
5430                 *num_counters_fixed = INTEL_PMC_MAX_FIXED;
5431         }
5432
5433         *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED;
5434 }
5435
5436 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5437                                               int num_counters,
5438                                               int num_counters_fixed,
5439                                               u64 intel_ctrl)
5440 {
5441         struct event_constraint *c;
5442
5443         if (!event_constraints)
5444                 return;
5445
5446         /*
5447          * event on fixed counter2 (REF_CYCLES) only works on this
5448          * counter, so do not extend mask to generic counters
5449          */
5450         for_each_event_constraint(c, event_constraints) {
5451                 /*
5452                  * Don't extend the topdown slots and metrics
5453                  * events to the generic counters.
5454                  */
5455                 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5456                         /*
5457                          * Disable topdown slots and metrics events,
5458                          * if slots event is not in CPUID.
5459                          */
5460                         if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
5461                                 c->idxmsk64 = 0;
5462                         c->weight = hweight64(c->idxmsk64);
5463                         continue;
5464                 }
5465
5466                 if (c->cmask == FIXED_EVENT_FLAGS) {
5467                         /* Disabled fixed counters which are not in CPUID */
5468                         c->idxmsk64 &= intel_ctrl;
5469
5470                         /*
5471                          * Don't extend the pseudo-encoding to the
5472                          * generic counters
5473                          */
5474                         if (!use_fixed_pseudo_encoding(c->code))
5475                                 c->idxmsk64 |= (1ULL << num_counters) - 1;
5476                 }
5477                 c->idxmsk64 &=
5478                         ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed));
5479                 c->weight = hweight64(c->idxmsk64);
5480         }
5481 }
5482
5483 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
5484 {
5485         struct extra_reg *er;
5486
5487         /*
5488          * Access extra MSR may cause #GP under certain circumstances.
5489          * E.g. KVM doesn't support offcore event
5490          * Check all extra_regs here.
5491          */
5492         if (!extra_regs)
5493                 return;
5494
5495         for (er = extra_regs; er->msr; er++) {
5496                 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5497                 /* Disable LBR select mapping */
5498                 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5499                         x86_pmu.lbr_sel_map = NULL;
5500         }
5501 }
5502
5503 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask)
5504 {
5505         struct x86_hybrid_pmu *pmu;
5506         int i;
5507
5508         for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5509                 pmu = &x86_pmu.hybrid_pmu[i];
5510
5511                 intel_pmu_check_num_counters(&pmu->num_counters,
5512                                              &pmu->num_counters_fixed,
5513                                              &pmu->intel_ctrl,
5514                                              fixed_mask);
5515
5516                 if (pmu->intel_cap.perf_metrics) {
5517                         pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5518                         pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS;
5519                 }
5520
5521                 if (pmu->intel_cap.pebs_output_pt_available)
5522                         pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
5523
5524                 intel_pmu_check_event_constraints(pmu->event_constraints,
5525                                                   pmu->num_counters,
5526                                                   pmu->num_counters_fixed,
5527                                                   pmu->intel_ctrl);
5528
5529                 intel_pmu_check_extra_regs(pmu->extra_regs);
5530         }
5531 }
5532
5533 __init int intel_pmu_init(void)
5534 {
5535         struct attribute **extra_skl_attr = &empty_attrs;
5536         struct attribute **extra_attr = &empty_attrs;
5537         struct attribute **td_attr    = &empty_attrs;
5538         struct attribute **mem_attr   = &empty_attrs;
5539         struct attribute **tsx_attr   = &empty_attrs;
5540         union cpuid10_edx edx;
5541         union cpuid10_eax eax;
5542         union cpuid10_ebx ebx;
5543         unsigned int fixed_mask;
5544         bool pmem = false;
5545         int version, i;
5546         char *name;
5547         struct x86_hybrid_pmu *pmu;
5548
5549         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
5550                 switch (boot_cpu_data.x86) {
5551                 case 0x6:
5552                         return p6_pmu_init();
5553                 case 0xb:
5554                         return knc_pmu_init();
5555                 case 0xf:
5556                         return p4_pmu_init();
5557                 }
5558                 return -ENODEV;
5559         }
5560
5561         /*
5562          * Check whether the Architectural PerfMon supports
5563          * Branch Misses Retired hw_event or not.
5564          */
5565         cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
5566         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
5567                 return -ENODEV;
5568
5569         version = eax.split.version_id;
5570         if (version < 2)
5571                 x86_pmu = core_pmu;
5572         else
5573                 x86_pmu = intel_pmu;
5574
5575         x86_pmu.version                 = version;
5576         x86_pmu.num_counters            = eax.split.num_counters;
5577         x86_pmu.cntval_bits             = eax.split.bit_width;
5578         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
5579
5580         x86_pmu.events_maskl            = ebx.full;
5581         x86_pmu.events_mask_len         = eax.split.mask_length;
5582
5583         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
5584
5585         /*
5586          * Quirk: v2 perfmon does not report fixed-purpose events, so
5587          * assume at least 3 events, when not running in a hypervisor:
5588          */
5589         if (version > 1 && version < 5) {
5590                 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
5591
5592                 x86_pmu.num_counters_fixed =
5593                         max((int)edx.split.num_counters_fixed, assume);
5594
5595                 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
5596         } else if (version >= 5)
5597                 x86_pmu.num_counters_fixed = fls(fixed_mask);
5598
5599         if (boot_cpu_has(X86_FEATURE_PDCM)) {
5600                 u64 capabilities;
5601
5602                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
5603                 x86_pmu.intel_cap.capabilities = capabilities;
5604         }
5605
5606         if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
5607                 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
5608                 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
5609         }
5610
5611         if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
5612                 intel_pmu_arch_lbr_init();
5613
5614         intel_ds_init();
5615
5616         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5617
5618         if (version >= 5) {
5619                 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5620                 if (x86_pmu.intel_cap.anythread_deprecated)
5621                         pr_cont(" AnyThread deprecated, ");
5622         }
5623
5624         /*
5625          * Install the hw-cache-events table:
5626          */
5627         switch (boot_cpu_data.x86_model) {
5628         case INTEL_FAM6_CORE_YONAH:
5629                 pr_cont("Core events, ");
5630                 name = "core";
5631                 break;
5632
5633         case INTEL_FAM6_CORE2_MEROM:
5634                 x86_add_quirk(intel_clovertown_quirk);
5635                 fallthrough;
5636
5637         case INTEL_FAM6_CORE2_MEROM_L:
5638         case INTEL_FAM6_CORE2_PENRYN:
5639         case INTEL_FAM6_CORE2_DUNNINGTON:
5640                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5641                        sizeof(hw_cache_event_ids));
5642
5643                 intel_pmu_lbr_init_core();
5644
5645                 x86_pmu.event_constraints = intel_core2_event_constraints;
5646                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5647                 pr_cont("Core2 events, ");
5648                 name = "core2";
5649                 break;
5650
5651         case INTEL_FAM6_NEHALEM:
5652         case INTEL_FAM6_NEHALEM_EP:
5653         case INTEL_FAM6_NEHALEM_EX:
5654                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5655                        sizeof(hw_cache_event_ids));
5656                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5657                        sizeof(hw_cache_extra_regs));
5658
5659                 intel_pmu_lbr_init_nhm();
5660
5661                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5662                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5663                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5664                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5665                 x86_pmu.limit_period = nhm_limit_period;
5666
5667                 mem_attr = nhm_mem_events_attrs;
5668
5669                 /* UOPS_ISSUED.STALLED_CYCLES */
5670                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5671                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5672                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5673                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5674                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5675
5676                 intel_pmu_pebs_data_source_nhm();
5677                 x86_add_quirk(intel_nehalem_quirk);
5678                 x86_pmu.pebs_no_tlb = 1;
5679                 extra_attr = nhm_format_attr;
5680
5681                 pr_cont("Nehalem events, ");
5682                 name = "nehalem";
5683                 break;
5684
5685         case INTEL_FAM6_ATOM_BONNELL:
5686         case INTEL_FAM6_ATOM_BONNELL_MID:
5687         case INTEL_FAM6_ATOM_SALTWELL:
5688         case INTEL_FAM6_ATOM_SALTWELL_MID:
5689         case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5690                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5691                        sizeof(hw_cache_event_ids));
5692
5693                 intel_pmu_lbr_init_atom();
5694
5695                 x86_pmu.event_constraints = intel_gen_event_constraints;
5696                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5697                 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5698                 pr_cont("Atom events, ");
5699                 name = "bonnell";
5700                 break;
5701
5702         case INTEL_FAM6_ATOM_SILVERMONT:
5703         case INTEL_FAM6_ATOM_SILVERMONT_D:
5704         case INTEL_FAM6_ATOM_SILVERMONT_MID:
5705         case INTEL_FAM6_ATOM_AIRMONT:
5706         case INTEL_FAM6_ATOM_AIRMONT_MID:
5707                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5708                         sizeof(hw_cache_event_ids));
5709                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5710                        sizeof(hw_cache_extra_regs));
5711
5712                 intel_pmu_lbr_init_slm();
5713
5714                 x86_pmu.event_constraints = intel_slm_event_constraints;
5715                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5716                 x86_pmu.extra_regs = intel_slm_extra_regs;
5717                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5718                 td_attr = slm_events_attrs;
5719                 extra_attr = slm_format_attr;
5720                 pr_cont("Silvermont events, ");
5721                 name = "silvermont";
5722                 break;
5723
5724         case INTEL_FAM6_ATOM_GOLDMONT:
5725         case INTEL_FAM6_ATOM_GOLDMONT_D:
5726                 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5727                        sizeof(hw_cache_event_ids));
5728                 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5729                        sizeof(hw_cache_extra_regs));
5730
5731                 intel_pmu_lbr_init_skl();
5732
5733                 x86_pmu.event_constraints = intel_slm_event_constraints;
5734                 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5735                 x86_pmu.extra_regs = intel_glm_extra_regs;
5736                 /*
5737                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5738                  * for precise cycles.
5739                  * :pp is identical to :ppp
5740                  */
5741                 x86_pmu.pebs_aliases = NULL;
5742                 x86_pmu.pebs_prec_dist = true;
5743                 x86_pmu.lbr_pt_coexist = true;
5744                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5745                 td_attr = glm_events_attrs;
5746                 extra_attr = slm_format_attr;
5747                 pr_cont("Goldmont events, ");
5748                 name = "goldmont";
5749                 break;
5750
5751         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5752                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5753                        sizeof(hw_cache_event_ids));
5754                 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5755                        sizeof(hw_cache_extra_regs));
5756
5757                 intel_pmu_lbr_init_skl();
5758
5759                 x86_pmu.event_constraints = intel_slm_event_constraints;
5760                 x86_pmu.extra_regs = intel_glm_extra_regs;
5761                 /*
5762                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5763                  * for precise cycles.
5764                  */
5765                 x86_pmu.pebs_aliases = NULL;
5766                 x86_pmu.pebs_prec_dist = true;
5767                 x86_pmu.lbr_pt_coexist = true;
5768                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5769                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5770                 x86_pmu.get_event_constraints = glp_get_event_constraints;
5771                 td_attr = glm_events_attrs;
5772                 /* Goldmont Plus has 4-wide pipeline */
5773                 event_attr_td_total_slots_scale_glm.event_str = "4";
5774                 extra_attr = slm_format_attr;
5775                 pr_cont("Goldmont plus events, ");
5776                 name = "goldmont_plus";
5777                 break;
5778
5779         case INTEL_FAM6_ATOM_TREMONT_D:
5780         case INTEL_FAM6_ATOM_TREMONT:
5781         case INTEL_FAM6_ATOM_TREMONT_L:
5782                 x86_pmu.late_ack = true;
5783                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5784                        sizeof(hw_cache_event_ids));
5785                 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5786                        sizeof(hw_cache_extra_regs));
5787                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5788
5789                 intel_pmu_lbr_init_skl();
5790
5791                 x86_pmu.event_constraints = intel_slm_event_constraints;
5792                 x86_pmu.extra_regs = intel_tnt_extra_regs;
5793                 /*
5794                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5795                  * for precise cycles.
5796                  */
5797                 x86_pmu.pebs_aliases = NULL;
5798                 x86_pmu.pebs_prec_dist = true;
5799                 x86_pmu.lbr_pt_coexist = true;
5800                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5801                 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5802                 td_attr = tnt_events_attrs;
5803                 extra_attr = slm_format_attr;
5804                 pr_cont("Tremont events, ");
5805                 name = "Tremont";
5806                 break;
5807
5808         case INTEL_FAM6_WESTMERE:
5809         case INTEL_FAM6_WESTMERE_EP:
5810         case INTEL_FAM6_WESTMERE_EX:
5811                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5812                        sizeof(hw_cache_event_ids));
5813                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5814                        sizeof(hw_cache_extra_regs));
5815
5816                 intel_pmu_lbr_init_nhm();
5817
5818                 x86_pmu.event_constraints = intel_westmere_event_constraints;
5819                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5820                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5821                 x86_pmu.extra_regs = intel_westmere_extra_regs;
5822                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5823
5824                 mem_attr = nhm_mem_events_attrs;
5825
5826                 /* UOPS_ISSUED.STALLED_CYCLES */
5827                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5828                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5829                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5830                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5831                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5832
5833                 intel_pmu_pebs_data_source_nhm();
5834                 extra_attr = nhm_format_attr;
5835                 pr_cont("Westmere events, ");
5836                 name = "westmere";
5837                 break;
5838
5839         case INTEL_FAM6_SANDYBRIDGE:
5840         case INTEL_FAM6_SANDYBRIDGE_X:
5841                 x86_add_quirk(intel_sandybridge_quirk);
5842                 x86_add_quirk(intel_ht_bug);
5843                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5844                        sizeof(hw_cache_event_ids));
5845                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5846                        sizeof(hw_cache_extra_regs));
5847
5848                 intel_pmu_lbr_init_snb();
5849
5850                 x86_pmu.event_constraints = intel_snb_event_constraints;
5851                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5852                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5853                 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5854                         x86_pmu.extra_regs = intel_snbep_extra_regs;
5855                 else
5856                         x86_pmu.extra_regs = intel_snb_extra_regs;
5857
5858
5859                 /* all extra regs are per-cpu when HT is on */
5860                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5861                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5862
5863                 td_attr  = snb_events_attrs;
5864                 mem_attr = snb_mem_events_attrs;
5865
5866                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5867                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5868                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5869                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5870                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5871                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5872
5873                 extra_attr = nhm_format_attr;
5874
5875                 pr_cont("SandyBridge events, ");
5876                 name = "sandybridge";
5877                 break;
5878
5879         case INTEL_FAM6_IVYBRIDGE:
5880         case INTEL_FAM6_IVYBRIDGE_X:
5881                 x86_add_quirk(intel_ht_bug);
5882                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5883                        sizeof(hw_cache_event_ids));
5884                 /* dTLB-load-misses on IVB is different than SNB */
5885                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5886
5887                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5888                        sizeof(hw_cache_extra_regs));
5889
5890                 intel_pmu_lbr_init_snb();
5891
5892                 x86_pmu.event_constraints = intel_ivb_event_constraints;
5893                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5894                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5895                 x86_pmu.pebs_prec_dist = true;
5896                 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5897                         x86_pmu.extra_regs = intel_snbep_extra_regs;
5898                 else
5899                         x86_pmu.extra_regs = intel_snb_extra_regs;
5900                 /* all extra regs are per-cpu when HT is on */
5901                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5902                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5903
5904                 td_attr  = snb_events_attrs;
5905                 mem_attr = snb_mem_events_attrs;
5906
5907                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5908                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5909                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5910
5911                 extra_attr = nhm_format_attr;
5912
5913                 pr_cont("IvyBridge events, ");
5914                 name = "ivybridge";
5915                 break;
5916
5917
5918         case INTEL_FAM6_HASWELL:
5919         case INTEL_FAM6_HASWELL_X:
5920         case INTEL_FAM6_HASWELL_L:
5921         case INTEL_FAM6_HASWELL_G:
5922                 x86_add_quirk(intel_ht_bug);
5923                 x86_add_quirk(intel_pebs_isolation_quirk);
5924                 x86_pmu.late_ack = true;
5925                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5926                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5927
5928                 intel_pmu_lbr_init_hsw();
5929
5930                 x86_pmu.event_constraints = intel_hsw_event_constraints;
5931                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
5932                 x86_pmu.extra_regs = intel_snbep_extra_regs;
5933                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5934                 x86_pmu.pebs_prec_dist = true;
5935                 /* all extra regs are per-cpu when HT is on */
5936                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5937                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5938
5939                 x86_pmu.hw_config = hsw_hw_config;
5940                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5941                 x86_pmu.lbr_double_abort = true;
5942                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5943                         hsw_format_attr : nhm_format_attr;
5944                 td_attr  = hsw_events_attrs;
5945                 mem_attr = hsw_mem_events_attrs;
5946                 tsx_attr = hsw_tsx_events_attrs;
5947                 pr_cont("Haswell events, ");
5948                 name = "haswell";
5949                 break;
5950
5951         case INTEL_FAM6_BROADWELL:
5952         case INTEL_FAM6_BROADWELL_D:
5953         case INTEL_FAM6_BROADWELL_G:
5954         case INTEL_FAM6_BROADWELL_X:
5955                 x86_add_quirk(intel_pebs_isolation_quirk);
5956                 x86_pmu.late_ack = true;
5957                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5958                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5959
5960                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
5961                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
5962                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
5963                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
5964                                                                           HSW_SNOOP_DRAM;
5965                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
5966                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5967                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
5968                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5969
5970                 intel_pmu_lbr_init_hsw();
5971
5972                 x86_pmu.event_constraints = intel_bdw_event_constraints;
5973                 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
5974                 x86_pmu.extra_regs = intel_snbep_extra_regs;
5975                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5976                 x86_pmu.pebs_prec_dist = true;
5977                 /* all extra regs are per-cpu when HT is on */
5978                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5979                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5980
5981                 x86_pmu.hw_config = hsw_hw_config;
5982                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5983                 x86_pmu.limit_period = bdw_limit_period;
5984                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5985                         hsw_format_attr : nhm_format_attr;
5986                 td_attr  = hsw_events_attrs;
5987                 mem_attr = hsw_mem_events_attrs;
5988                 tsx_attr = hsw_tsx_events_attrs;
5989                 pr_cont("Broadwell events, ");
5990                 name = "broadwell";
5991                 break;
5992
5993         case INTEL_FAM6_XEON_PHI_KNL:
5994         case INTEL_FAM6_XEON_PHI_KNM:
5995                 memcpy(hw_cache_event_ids,
5996                        slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5997                 memcpy(hw_cache_extra_regs,
5998                        knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5999                 intel_pmu_lbr_init_knl();
6000
6001                 x86_pmu.event_constraints = intel_slm_event_constraints;
6002                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6003                 x86_pmu.extra_regs = intel_knl_extra_regs;
6004
6005                 /* all extra regs are per-cpu when HT is on */
6006                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6007                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6008                 extra_attr = slm_format_attr;
6009                 pr_cont("Knights Landing/Mill events, ");
6010                 name = "knights-landing";
6011                 break;
6012
6013         case INTEL_FAM6_SKYLAKE_X:
6014                 pmem = true;
6015                 fallthrough;
6016         case INTEL_FAM6_SKYLAKE_L:
6017         case INTEL_FAM6_SKYLAKE:
6018         case INTEL_FAM6_KABYLAKE_L:
6019         case INTEL_FAM6_KABYLAKE:
6020         case INTEL_FAM6_COMETLAKE_L:
6021         case INTEL_FAM6_COMETLAKE:
6022                 x86_add_quirk(intel_pebs_isolation_quirk);
6023                 x86_pmu.late_ack = true;
6024                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6025                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6026                 intel_pmu_lbr_init_skl();
6027
6028                 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
6029                 event_attr_td_recovery_bubbles.event_str_noht =
6030                         "event=0xd,umask=0x1,cmask=1";
6031                 event_attr_td_recovery_bubbles.event_str_ht =
6032                         "event=0xd,umask=0x1,cmask=1,any=1";
6033
6034                 x86_pmu.event_constraints = intel_skl_event_constraints;
6035                 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6036                 x86_pmu.extra_regs = intel_skl_extra_regs;
6037                 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6038                 x86_pmu.pebs_prec_dist = true;
6039                 /* all extra regs are per-cpu when HT is on */
6040                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6041                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6042
6043                 x86_pmu.hw_config = hsw_hw_config;
6044                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6045                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6046                         hsw_format_attr : nhm_format_attr;
6047                 extra_skl_attr = skl_format_attr;
6048                 td_attr  = hsw_events_attrs;
6049                 mem_attr = hsw_mem_events_attrs;
6050                 tsx_attr = hsw_tsx_events_attrs;
6051                 intel_pmu_pebs_data_source_skl(pmem);
6052
6053                 /*
6054                  * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
6055                  * TSX force abort hooks are not required on these systems. Only deploy
6056                  * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
6057                  */
6058                 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
6059                    !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
6060                         x86_pmu.flags |= PMU_FL_TFA;
6061                         x86_pmu.get_event_constraints = tfa_get_event_constraints;
6062                         x86_pmu.enable_all = intel_tfa_pmu_enable_all;
6063                         x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
6064                 }
6065
6066                 pr_cont("Skylake events, ");
6067                 name = "skylake";
6068                 break;
6069
6070         case INTEL_FAM6_ICELAKE_X:
6071         case INTEL_FAM6_ICELAKE_D:
6072                 pmem = true;
6073                 fallthrough;
6074         case INTEL_FAM6_ICELAKE_L:
6075         case INTEL_FAM6_ICELAKE:
6076         case INTEL_FAM6_TIGERLAKE_L:
6077         case INTEL_FAM6_TIGERLAKE:
6078         case INTEL_FAM6_ROCKETLAKE:
6079                 x86_pmu.late_ack = true;
6080                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6081                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6082                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6083                 intel_pmu_lbr_init_skl();
6084
6085                 x86_pmu.event_constraints = intel_icl_event_constraints;
6086                 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
6087                 x86_pmu.extra_regs = intel_icl_extra_regs;
6088                 x86_pmu.pebs_aliases = NULL;
6089                 x86_pmu.pebs_prec_dist = true;
6090                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6091                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6092
6093                 x86_pmu.hw_config = hsw_hw_config;
6094                 x86_pmu.get_event_constraints = icl_get_event_constraints;
6095                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6096                         hsw_format_attr : nhm_format_attr;
6097                 extra_skl_attr = skl_format_attr;
6098                 mem_attr = icl_events_attrs;
6099                 td_attr = icl_td_events_attrs;
6100                 tsx_attr = icl_tsx_events_attrs;
6101                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6102                 x86_pmu.lbr_pt_coexist = true;
6103                 intel_pmu_pebs_data_source_skl(pmem);
6104                 x86_pmu.num_topdown_events = 4;
6105                 x86_pmu.update_topdown_event = icl_update_topdown_event;
6106                 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
6107                 pr_cont("Icelake events, ");
6108                 name = "icelake";
6109                 break;
6110
6111         case INTEL_FAM6_SAPPHIRERAPIDS_X:
6112         case INTEL_FAM6_EMERALDRAPIDS_X:
6113                 pmem = true;
6114                 x86_pmu.late_ack = true;
6115                 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6116                 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6117
6118                 x86_pmu.event_constraints = intel_spr_event_constraints;
6119                 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
6120                 x86_pmu.extra_regs = intel_spr_extra_regs;
6121                 x86_pmu.limit_period = spr_limit_period;
6122                 x86_pmu.pebs_aliases = NULL;
6123                 x86_pmu.pebs_prec_dist = true;
6124                 x86_pmu.pebs_block = true;
6125                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6126                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6127                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6128                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6129                 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6130
6131                 x86_pmu.hw_config = hsw_hw_config;
6132                 x86_pmu.get_event_constraints = spr_get_event_constraints;
6133                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6134                         hsw_format_attr : nhm_format_attr;
6135                 extra_skl_attr = skl_format_attr;
6136                 mem_attr = spr_events_attrs;
6137                 td_attr = spr_td_events_attrs;
6138                 tsx_attr = spr_tsx_events_attrs;
6139                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6140                 x86_pmu.lbr_pt_coexist = true;
6141                 intel_pmu_pebs_data_source_skl(pmem);
6142                 x86_pmu.num_topdown_events = 8;
6143                 x86_pmu.update_topdown_event = icl_update_topdown_event;
6144                 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
6145                 pr_cont("Sapphire Rapids events, ");
6146                 name = "sapphire_rapids";
6147                 break;
6148
6149         case INTEL_FAM6_ALDERLAKE:
6150         case INTEL_FAM6_ALDERLAKE_L:
6151                 /*
6152                  * Alder Lake has 2 types of CPU, core and atom.
6153                  *
6154                  * Initialize the common PerfMon capabilities here.
6155                  */
6156                 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS,
6157                                              sizeof(struct x86_hybrid_pmu),
6158                                              GFP_KERNEL);
6159                 if (!x86_pmu.hybrid_pmu)
6160                         return -ENOMEM;
6161                 static_branch_enable(&perf_is_hybrid);
6162                 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS;
6163
6164                 x86_pmu.pebs_aliases = NULL;
6165                 x86_pmu.pebs_prec_dist = true;
6166                 x86_pmu.pebs_block = true;
6167                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6168                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6169                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6170                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6171                 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6172                 x86_pmu.lbr_pt_coexist = true;
6173                 intel_pmu_pebs_data_source_skl(false);
6174                 x86_pmu.num_topdown_events = 8;
6175                 x86_pmu.update_topdown_event = adl_update_topdown_event;
6176                 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period;
6177
6178                 x86_pmu.filter_match = intel_pmu_filter_match;
6179                 x86_pmu.get_event_constraints = adl_get_event_constraints;
6180                 x86_pmu.hw_config = adl_hw_config;
6181                 x86_pmu.limit_period = spr_limit_period;
6182                 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
6183                 /*
6184                  * The rtm_abort_event is used to check whether to enable GPRs
6185                  * for the RTM abort event. Atom doesn't have the RTM abort
6186                  * event. There is no harmful to set it in the common
6187                  * x86_pmu.rtm_abort_event.
6188                  */
6189                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6190
6191                 td_attr = adl_hybrid_events_attrs;
6192                 mem_attr = adl_hybrid_mem_attrs;
6193                 tsx_attr = adl_hybrid_tsx_attrs;
6194                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6195                         adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
6196
6197                 /* Initialize big core specific PerfMon capabilities.*/
6198                 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
6199                 pmu->name = "cpu_core";
6200                 pmu->cpu_type = hybrid_big;
6201                 pmu->late_ack = true;
6202                 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
6203                         pmu->num_counters = x86_pmu.num_counters + 2;
6204                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1;
6205                 } else {
6206                         pmu->num_counters = x86_pmu.num_counters;
6207                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6208                 }
6209
6210                 /*
6211                  * Quirk: For some Alder Lake machine, when all E-cores are disabled in
6212                  * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
6213                  * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
6214                  * mistakenly add extra counters for P-cores. Correct the number of
6215                  * counters here.
6216                  */
6217                 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) {
6218                         pmu->num_counters = x86_pmu.num_counters;
6219                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6220                 }
6221
6222                 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
6223                 pmu->unconstrained = (struct event_constraint)
6224                                         __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6225                                                            0, pmu->num_counters, 0, 0);
6226                 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6227                 pmu->intel_cap.perf_metrics = 1;
6228                 pmu->intel_cap.pebs_output_pt_available = 0;
6229
6230                 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6231                 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6232                 pmu->event_constraints = intel_spr_event_constraints;
6233                 pmu->pebs_constraints = intel_spr_pebs_event_constraints;
6234                 pmu->extra_regs = intel_spr_extra_regs;
6235
6236                 /* Initialize Atom core specific PerfMon capabilities.*/
6237                 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
6238                 pmu->name = "cpu_atom";
6239                 pmu->cpu_type = hybrid_small;
6240                 pmu->mid_ack = true;
6241                 pmu->num_counters = x86_pmu.num_counters;
6242                 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6243                 pmu->max_pebs_events = x86_pmu.max_pebs_events;
6244                 pmu->unconstrained = (struct event_constraint)
6245                                         __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6246                                                            0, pmu->num_counters, 0, 0);
6247                 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6248                 pmu->intel_cap.perf_metrics = 0;
6249                 pmu->intel_cap.pebs_output_pt_available = 1;
6250
6251                 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6252                 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6253                 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6254                 pmu->event_constraints = intel_slm_event_constraints;
6255                 pmu->pebs_constraints = intel_grt_pebs_event_constraints;
6256                 pmu->extra_regs = intel_grt_extra_regs;
6257                 pr_cont("Alderlake Hybrid events, ");
6258                 name = "alderlake_hybrid";
6259                 break;
6260
6261         default:
6262                 switch (x86_pmu.version) {
6263                 case 1:
6264                         x86_pmu.event_constraints = intel_v1_event_constraints;
6265                         pr_cont("generic architected perfmon v1, ");
6266                         name = "generic_arch_v1";
6267                         break;
6268                 default:
6269                         /*
6270                          * default constraints for v2 and up
6271                          */
6272                         x86_pmu.event_constraints = intel_gen_event_constraints;
6273                         pr_cont("generic architected perfmon, ");
6274                         name = "generic_arch_v2+";
6275                         break;
6276                 }
6277         }
6278
6279         snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
6280
6281         if (!is_hybrid()) {
6282                 group_events_td.attrs  = td_attr;
6283                 group_events_mem.attrs = mem_attr;
6284                 group_events_tsx.attrs = tsx_attr;
6285                 group_format_extra.attrs = extra_attr;
6286                 group_format_extra_skl.attrs = extra_skl_attr;
6287
6288                 x86_pmu.attr_update = attr_update;
6289         } else {
6290                 hybrid_group_events_td.attrs  = td_attr;
6291                 hybrid_group_events_mem.attrs = mem_attr;
6292                 hybrid_group_events_tsx.attrs = tsx_attr;
6293                 hybrid_group_format_extra.attrs = extra_attr;
6294
6295                 x86_pmu.attr_update = hybrid_attr_update;
6296         }
6297
6298         intel_pmu_check_num_counters(&x86_pmu.num_counters,
6299                                      &x86_pmu.num_counters_fixed,
6300                                      &x86_pmu.intel_ctrl,
6301                                      (u64)fixed_mask);
6302
6303         /* AnyThread may be deprecated on arch perfmon v5 or later */
6304         if (x86_pmu.intel_cap.anythread_deprecated)
6305                 x86_pmu.format_attrs = intel_arch_formats_attr;
6306
6307         intel_pmu_check_event_constraints(x86_pmu.event_constraints,
6308                                           x86_pmu.num_counters,
6309                                           x86_pmu.num_counters_fixed,
6310                                           x86_pmu.intel_ctrl);
6311         /*
6312          * Access LBR MSR may cause #GP under certain circumstances.
6313          * E.g. KVM doesn't support LBR MSR
6314          * Check all LBT MSR here.
6315          * Disable LBR access if any LBR MSRs can not be accessed.
6316          */
6317         if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
6318                 x86_pmu.lbr_nr = 0;
6319         for (i = 0; i < x86_pmu.lbr_nr; i++) {
6320                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
6321                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
6322                         x86_pmu.lbr_nr = 0;
6323         }
6324
6325         if (x86_pmu.lbr_nr)
6326                 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
6327
6328         intel_pmu_check_extra_regs(x86_pmu.extra_regs);
6329
6330         /* Support full width counters using alternative MSR range */
6331         if (x86_pmu.intel_cap.full_width_write) {
6332                 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
6333                 x86_pmu.perfctr = MSR_IA32_PMC0;
6334                 pr_cont("full-width counters, ");
6335         }
6336
6337         if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
6338                 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
6339
6340         if (is_hybrid())
6341                 intel_pmu_check_hybrid_pmus((u64)fixed_mask);
6342
6343         return 0;
6344 }
6345
6346 /*
6347  * HT bug: phase 2 init
6348  * Called once we have valid topology information to check
6349  * whether or not HT is enabled
6350  * If HT is off, then we disable the workaround
6351  */
6352 static __init int fixup_ht_bug(void)
6353 {
6354         int c;
6355         /*
6356          * problem not present on this CPU model, nothing to do
6357          */
6358         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
6359                 return 0;
6360
6361         if (topology_max_smt_threads() > 1) {
6362                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
6363                 return 0;
6364         }
6365
6366         cpus_read_lock();
6367
6368         hardlockup_detector_perf_stop();
6369
6370         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
6371
6372         x86_pmu.start_scheduling = NULL;
6373         x86_pmu.commit_scheduling = NULL;
6374         x86_pmu.stop_scheduling = NULL;
6375
6376         hardlockup_detector_perf_restart();
6377
6378         for_each_online_cpu(c)
6379                 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
6380
6381         cpus_read_unlock();
6382         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
6383         return 0;
6384 }
6385 subsys_initcall(fixup_ht_bug)