2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
33 #include <asm/stacktrace.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
42 #include <asm/unwind.h>
44 #include "perf_event.h"
46 struct x86_pmu x86_pmu __read_mostly;
48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX]
60 [PERF_COUNT_HW_CACHE_OP_MAX]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX];
64 * Propagate event elapsed time into the generic event.
65 * Can only be executed on the CPU where the event is active.
66 * Returns the delta events processed.
68 u64 x86_perf_event_update(struct perf_event *event)
70 struct hw_perf_event *hwc = &event->hw;
71 int shift = 64 - x86_pmu.cntval_bits;
72 u64 prev_raw_count, new_raw_count;
76 if (idx == INTEL_PMC_IDX_FIXED_BTS)
80 * Careful: an NMI might modify the previous event value.
82 * Our tactic to handle this is to first atomically read and
83 * exchange a new raw count - then add that new-prev delta
84 * count to the generic event atomically:
87 prev_raw_count = local64_read(&hwc->prev_count);
88 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
91 new_raw_count) != prev_raw_count)
95 * Now we have the new raw value and have updated the prev
96 * timestamp already. We can now calculate the elapsed delta
97 * (event-)time and add that to the generic event.
99 * Careful, not all hw sign-extends above the physical width
102 delta = (new_raw_count << shift) - (prev_raw_count << shift);
105 local64_add(delta, &event->count);
106 local64_sub(delta, &hwc->period_left);
108 return new_raw_count;
112 * Find and validate any extra registers to set up.
114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
116 struct hw_perf_event_extra *reg;
117 struct extra_reg *er;
119 reg = &event->hw.extra_reg;
121 if (!x86_pmu.extra_regs)
124 for (er = x86_pmu.extra_regs; er->msr; er++) {
125 if (er->event != (config & er->config_mask))
127 if (event->attr.config1 & ~er->valid_mask)
129 /* Check if the extra msrs can be safely accessed*/
130 if (!er->extra_msr_access)
134 reg->config = event->attr.config1;
141 static atomic_t active_events;
142 static atomic_t pmc_refcount;
143 static DEFINE_MUTEX(pmc_reserve_mutex);
145 #ifdef CONFIG_X86_LOCAL_APIC
147 static bool reserve_pmc_hardware(void)
151 for (i = 0; i < x86_pmu.num_counters; i++) {
152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
156 for (i = 0; i < x86_pmu.num_counters; i++) {
157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
164 for (i--; i >= 0; i--)
165 release_evntsel_nmi(x86_pmu_config_addr(i));
167 i = x86_pmu.num_counters;
170 for (i--; i >= 0; i--)
171 release_perfctr_nmi(x86_pmu_event_addr(i));
176 static void release_pmc_hardware(void)
180 for (i = 0; i < x86_pmu.num_counters; i++) {
181 release_perfctr_nmi(x86_pmu_event_addr(i));
182 release_evntsel_nmi(x86_pmu_config_addr(i));
188 static bool reserve_pmc_hardware(void) { return true; }
189 static void release_pmc_hardware(void) {}
193 static bool check_hw_exists(void)
195 u64 val, val_fail = -1, val_new= ~0;
196 int i, reg, reg_fail = -1, ret = 0;
201 * Check to see if the BIOS enabled any of the counters, if so
204 for (i = 0; i < x86_pmu.num_counters; i++) {
205 reg = x86_pmu_config_addr(i);
206 ret = rdmsrl_safe(reg, &val);
209 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
218 if (x86_pmu.num_counters_fixed) {
219 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
220 ret = rdmsrl_safe(reg, &val);
223 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
224 if (val & (0x03 << i*4)) {
233 * If all the counters are enabled, the below test will always
234 * fail. The tools will also become useless in this scenario.
235 * Just fail and disable the hardware counters.
238 if (reg_safe == -1) {
244 * Read the current value, change it and read it back to see if it
245 * matches, this is needed to detect certain hardware emulators
246 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
248 reg = x86_pmu_event_addr(reg_safe);
249 if (rdmsrl_safe(reg, &val))
252 ret = wrmsrl_safe(reg, val);
253 ret |= rdmsrl_safe(reg, &val_new);
254 if (ret || val != val_new)
258 * We still allow the PMU driver to operate:
261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
262 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
270 pr_cont("PMU not available due to virtualization, using software events only.\n");
272 pr_cont("Broken PMU hardware detected, using software events only.\n");
273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
280 static void hw_perf_event_destroy(struct perf_event *event)
282 x86_release_hardware();
283 atomic_dec(&active_events);
286 void hw_perf_lbr_event_destroy(struct perf_event *event)
288 hw_perf_event_destroy(event);
290 /* undo the lbr/bts event accounting */
291 x86_del_exclusive(x86_lbr_exclusive_lbr);
294 static inline int x86_pmu_initialized(void)
296 return x86_pmu.handle_irq != NULL;
300 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
302 struct perf_event_attr *attr = &event->attr;
303 unsigned int cache_type, cache_op, cache_result;
306 config = attr->config;
308 cache_type = (config >> 0) & 0xff;
309 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
311 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
313 cache_op = (config >> 8) & 0xff;
314 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
316 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
318 cache_result = (config >> 16) & 0xff;
319 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
321 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
323 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
332 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
333 return x86_pmu_extra_regs(val, event);
336 int x86_reserve_hardware(void)
340 if (!atomic_inc_not_zero(&pmc_refcount)) {
341 mutex_lock(&pmc_reserve_mutex);
342 if (atomic_read(&pmc_refcount) == 0) {
343 if (!reserve_pmc_hardware())
346 reserve_ds_buffers();
349 atomic_inc(&pmc_refcount);
350 mutex_unlock(&pmc_reserve_mutex);
356 void x86_release_hardware(void)
358 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
359 release_pmc_hardware();
360 release_ds_buffers();
361 mutex_unlock(&pmc_reserve_mutex);
366 * Check if we can create event of a certain type (that no conflicting events
369 int x86_add_exclusive(unsigned int what)
374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
375 * LBR and BTS are still mutually exclusive.
377 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
380 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
381 mutex_lock(&pmc_reserve_mutex);
382 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
383 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
386 atomic_inc(&x86_pmu.lbr_exclusive[what]);
387 mutex_unlock(&pmc_reserve_mutex);
391 atomic_inc(&active_events);
395 mutex_unlock(&pmc_reserve_mutex);
399 void x86_del_exclusive(unsigned int what)
401 atomic_dec(&active_events);
404 * See the comment in x86_add_exclusive().
406 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
409 atomic_dec(&x86_pmu.lbr_exclusive[what]);
412 int x86_setup_perfctr(struct perf_event *event)
414 struct perf_event_attr *attr = &event->attr;
415 struct hw_perf_event *hwc = &event->hw;
418 if (!is_sampling_event(event)) {
419 hwc->sample_period = x86_pmu.max_period;
420 hwc->last_period = hwc->sample_period;
421 local64_set(&hwc->period_left, hwc->sample_period);
424 if (attr->type == PERF_TYPE_RAW)
425 return x86_pmu_extra_regs(event->attr.config, event);
427 if (attr->type == PERF_TYPE_HW_CACHE)
428 return set_ext_hw_attr(hwc, event);
430 if (attr->config >= x86_pmu.max_events)
433 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
438 config = x86_pmu.event_map(attr->config);
446 hwc->config |= config;
452 * check that branch_sample_type is compatible with
453 * settings needed for precise_ip > 1 which implies
454 * using the LBR to capture ALL taken branches at the
455 * priv levels of the measurement
457 static inline int precise_br_compat(struct perf_event *event)
459 u64 m = event->attr.branch_sample_type;
462 /* must capture all branches */
463 if (!(m & PERF_SAMPLE_BRANCH_ANY))
466 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
468 if (!event->attr.exclude_user)
469 b |= PERF_SAMPLE_BRANCH_USER;
471 if (!event->attr.exclude_kernel)
472 b |= PERF_SAMPLE_BRANCH_KERNEL;
475 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
481 int x86_pmu_max_precise(void)
485 /* Support for constant skid */
486 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
489 /* Support for IP fixup */
490 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
493 if (x86_pmu.pebs_prec_dist)
499 int x86_pmu_hw_config(struct perf_event *event)
501 if (event->attr.precise_ip) {
502 int precise = x86_pmu_max_precise();
504 if (event->attr.precise_ip > precise)
507 /* There's no sense in having PEBS for non sampling events: */
508 if (!is_sampling_event(event))
512 * check that PEBS LBR correction does not conflict with
513 * whatever the user is asking with attr->branch_sample_type
515 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
516 u64 *br_type = &event->attr.branch_sample_type;
518 if (has_branch_stack(event)) {
519 if (!precise_br_compat(event))
522 /* branch_sample_type is compatible */
526 * user did not specify branch_sample_type
528 * For PEBS fixups, we capture all
529 * the branches at the priv level of the
532 *br_type = PERF_SAMPLE_BRANCH_ANY;
534 if (!event->attr.exclude_user)
535 *br_type |= PERF_SAMPLE_BRANCH_USER;
537 if (!event->attr.exclude_kernel)
538 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
542 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
543 event->attach_state |= PERF_ATTACH_TASK_DATA;
547 * (keep 'enabled' bit clear for now)
549 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
552 * Count user and OS events unless requested not to
554 if (!event->attr.exclude_user)
555 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
556 if (!event->attr.exclude_kernel)
557 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
559 if (event->attr.type == PERF_TYPE_RAW)
560 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
562 if (event->attr.sample_period && x86_pmu.limit_period) {
563 if (x86_pmu.limit_period(event, event->attr.sample_period) >
564 event->attr.sample_period)
568 /* sample_regs_user never support XMM registers */
569 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
572 * Besides the general purpose registers, XMM registers may
573 * be collected in PEBS on some platforms, e.g. Icelake
575 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
576 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
579 if (!event->attr.precise_ip)
583 return x86_setup_perfctr(event);
587 * Setup the hardware configuration for a given attr_type
589 static int __x86_pmu_event_init(struct perf_event *event)
593 if (!x86_pmu_initialized())
596 err = x86_reserve_hardware();
600 atomic_inc(&active_events);
601 event->destroy = hw_perf_event_destroy;
604 event->hw.last_cpu = -1;
605 event->hw.last_tag = ~0ULL;
608 event->hw.extra_reg.idx = EXTRA_REG_NONE;
609 event->hw.branch_reg.idx = EXTRA_REG_NONE;
611 return x86_pmu.hw_config(event);
614 void x86_pmu_disable_all(void)
616 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
619 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
622 if (!test_bit(idx, cpuc->active_mask))
624 rdmsrl(x86_pmu_config_addr(idx), val);
625 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
627 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
628 wrmsrl(x86_pmu_config_addr(idx), val);
633 * There may be PMI landing after enabled=0. The PMI hitting could be before or
636 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
637 * It will not be re-enabled in the NMI handler again, because enabled=0. After
638 * handling the NMI, disable_all will be called, which will not change the
639 * state either. If PMI hits after disable_all, the PMU is already disabled
640 * before entering NMI handler. The NMI handler will not change the state
643 * So either situation is harmless.
645 static void x86_pmu_disable(struct pmu *pmu)
647 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
649 if (!x86_pmu_initialized())
659 x86_pmu.disable_all();
662 void x86_pmu_enable_all(int added)
664 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
667 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
668 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
670 if (!test_bit(idx, cpuc->active_mask))
673 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
677 static struct pmu pmu;
679 static inline int is_x86_event(struct perf_event *event)
681 return event->pmu == &pmu;
684 struct pmu *x86_get_pmu(void)
689 * Event scheduler state:
691 * Assign events iterating over all events and counters, beginning
692 * with events with least weights first. Keep the current iterator
693 * state in struct sched_state.
697 int event; /* event index */
698 int counter; /* counter index */
699 int unassigned; /* number of events to be assigned left */
700 int nr_gp; /* number of GP counters used */
701 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
704 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
705 #define SCHED_STATES_MAX 2
712 struct event_constraint **constraints;
713 struct sched_state state;
714 struct sched_state saved[SCHED_STATES_MAX];
718 * Initialize interator that runs through all events and counters.
720 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
721 int num, int wmin, int wmax, int gpmax)
725 memset(sched, 0, sizeof(*sched));
726 sched->max_events = num;
727 sched->max_weight = wmax;
728 sched->max_gp = gpmax;
729 sched->constraints = constraints;
731 for (idx = 0; idx < num; idx++) {
732 if (constraints[idx]->weight == wmin)
736 sched->state.event = idx; /* start with min weight */
737 sched->state.weight = wmin;
738 sched->state.unassigned = num;
741 static void perf_sched_save_state(struct perf_sched *sched)
743 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
746 sched->saved[sched->saved_states] = sched->state;
747 sched->saved_states++;
750 static bool perf_sched_restore_state(struct perf_sched *sched)
752 if (!sched->saved_states)
755 sched->saved_states--;
756 sched->state = sched->saved[sched->saved_states];
758 /* continue with next counter: */
759 clear_bit(sched->state.counter++, sched->state.used);
765 * Select a counter for the current event to schedule. Return true on
768 static bool __perf_sched_find_counter(struct perf_sched *sched)
770 struct event_constraint *c;
773 if (!sched->state.unassigned)
776 if (sched->state.event >= sched->max_events)
779 c = sched->constraints[sched->state.event];
780 /* Prefer fixed purpose counters */
781 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
782 idx = INTEL_PMC_IDX_FIXED;
783 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
784 if (!__test_and_set_bit(idx, sched->state.used))
789 /* Grab the first unused counter starting with idx */
790 idx = sched->state.counter;
791 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
792 if (!__test_and_set_bit(idx, sched->state.used)) {
793 if (sched->state.nr_gp++ >= sched->max_gp)
803 sched->state.counter = idx;
806 perf_sched_save_state(sched);
811 static bool perf_sched_find_counter(struct perf_sched *sched)
813 while (!__perf_sched_find_counter(sched)) {
814 if (!perf_sched_restore_state(sched))
822 * Go through all unassigned events and find the next one to schedule.
823 * Take events with the least weight first. Return true on success.
825 static bool perf_sched_next_event(struct perf_sched *sched)
827 struct event_constraint *c;
829 if (!sched->state.unassigned || !--sched->state.unassigned)
834 sched->state.event++;
835 if (sched->state.event >= sched->max_events) {
837 sched->state.event = 0;
838 sched->state.weight++;
839 if (sched->state.weight > sched->max_weight)
842 c = sched->constraints[sched->state.event];
843 } while (c->weight != sched->state.weight);
845 sched->state.counter = 0; /* start with first counter */
851 * Assign a counter for each event.
853 int perf_assign_events(struct event_constraint **constraints, int n,
854 int wmin, int wmax, int gpmax, int *assign)
856 struct perf_sched sched;
858 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
861 if (!perf_sched_find_counter(&sched))
864 assign[sched.state.event] = sched.state.counter;
865 } while (perf_sched_next_event(&sched));
867 return sched.state.unassigned;
869 EXPORT_SYMBOL_GPL(perf_assign_events);
871 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
873 struct event_constraint *c;
874 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
875 struct perf_event *e;
876 int n0, i, wmin, wmax, unsched = 0;
877 struct hw_perf_event *hwc;
879 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
882 * Compute the number of events already present; see x86_pmu_add(),
883 * validate_group() and x86_pmu_commit_txn(). For the former two
884 * cpuc->n_events hasn't been updated yet, while for the latter
885 * cpuc->n_txn contains the number of events added in the current
889 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
892 if (x86_pmu.start_scheduling)
893 x86_pmu.start_scheduling(cpuc);
895 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
896 c = cpuc->event_constraint[i];
899 * Previously scheduled events should have a cached constraint,
900 * while new events should not have one.
902 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
905 * Request constraints for new events; or for those events that
906 * have a dynamic constraint -- for those the constraint can
907 * change due to external factors (sibling state, allow_tfa).
909 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
910 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
911 cpuc->event_constraint[i] = c;
914 wmin = min(wmin, c->weight);
915 wmax = max(wmax, c->weight);
919 * fastpath, try to reuse previous register
921 for (i = 0; i < n; i++) {
922 hwc = &cpuc->event_list[i]->hw;
923 c = cpuc->event_constraint[i];
929 /* constraint still honored */
930 if (!test_bit(hwc->idx, c->idxmsk))
933 /* not already used */
934 if (test_bit(hwc->idx, used_mask))
937 __set_bit(hwc->idx, used_mask);
939 assign[i] = hwc->idx;
944 int gpmax = x86_pmu.num_counters;
947 * Do not allow scheduling of more than half the available
950 * This helps avoid counter starvation of sibling thread by
951 * ensuring at most half the counters cannot be in exclusive
952 * mode. There is no designated counters for the limits. Any
953 * N/2 counters can be used. This helps with events with
954 * specific counter constraints.
956 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
957 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
960 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
961 wmax, gpmax, assign);
965 * In case of success (unsched = 0), mark events as committed,
966 * so we do not put_constraint() in case new events are added
967 * and fail to be scheduled
969 * We invoke the lower level commit callback to lock the resource
971 * We do not need to do all of this in case we are called to
972 * validate an event group (assign == NULL)
974 if (!unsched && assign) {
975 for (i = 0; i < n; i++) {
976 e = cpuc->event_list[i];
977 if (x86_pmu.commit_scheduling)
978 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
981 for (i = n0; i < n; i++) {
982 e = cpuc->event_list[i];
985 * release events that failed scheduling
987 if (x86_pmu.put_event_constraints)
988 x86_pmu.put_event_constraints(cpuc, e);
990 cpuc->event_constraint[i] = NULL;
994 if (x86_pmu.stop_scheduling)
995 x86_pmu.stop_scheduling(cpuc);
997 return unsched ? -EINVAL : 0;
1001 * dogrp: true if must collect siblings events (group)
1002 * returns total number of events and error code
1004 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1006 struct perf_event *event;
1009 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1011 /* current number of events already accepted */
1013 if (!cpuc->n_events)
1014 cpuc->pebs_output = 0;
1016 if (!cpuc->is_fake && leader->attr.precise_ip) {
1018 * For PEBS->PT, if !aux_event, the group leader (PT) went
1019 * away, the group was broken down and this singleton event
1020 * can't schedule any more.
1022 if (is_pebs_pt(leader) && !leader->aux_event)
1026 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1028 if (cpuc->pebs_output &&
1029 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1032 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1035 if (is_x86_event(leader)) {
1038 cpuc->event_list[n] = leader;
1044 for_each_sibling_event(event, leader) {
1045 if (!is_x86_event(event) ||
1046 event->state <= PERF_EVENT_STATE_OFF)
1052 cpuc->event_list[n] = event;
1058 static inline void x86_assign_hw_event(struct perf_event *event,
1059 struct cpu_hw_events *cpuc, int i)
1061 struct hw_perf_event *hwc = &event->hw;
1063 hwc->idx = cpuc->assign[i];
1064 hwc->last_cpu = smp_processor_id();
1065 hwc->last_tag = ++cpuc->tags[i];
1067 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
1068 hwc->config_base = 0;
1069 hwc->event_base = 0;
1070 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1071 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1072 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1073 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1075 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1076 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1077 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1082 * x86_perf_rdpmc_index - Return PMC counter used for event
1083 * @event: the perf_event to which the PMC counter was assigned
1085 * The counter assigned to this performance event may change if interrupts
1086 * are enabled. This counter should thus never be used while interrupts are
1087 * enabled. Before this function is used to obtain the assigned counter the
1088 * event should be checked for validity using, for example,
1089 * perf_event_read_local(), within the same interrupt disabled section in
1090 * which this counter is planned to be used.
1092 * Return: The index of the performance monitoring counter assigned to
1095 int x86_perf_rdpmc_index(struct perf_event *event)
1097 lockdep_assert_irqs_disabled();
1099 return event->hw.event_base_rdpmc;
1102 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1103 struct cpu_hw_events *cpuc,
1106 return hwc->idx == cpuc->assign[i] &&
1107 hwc->last_cpu == smp_processor_id() &&
1108 hwc->last_tag == cpuc->tags[i];
1111 static void x86_pmu_start(struct perf_event *event, int flags);
1113 static void x86_pmu_enable(struct pmu *pmu)
1115 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1116 struct perf_event *event;
1117 struct hw_perf_event *hwc;
1118 int i, added = cpuc->n_added;
1120 if (!x86_pmu_initialized())
1126 if (cpuc->n_added) {
1127 int n_running = cpuc->n_events - cpuc->n_added;
1129 * apply assignment obtained either from
1130 * hw_perf_group_sched_in() or x86_pmu_enable()
1132 * step1: save events moving to new counters
1134 for (i = 0; i < n_running; i++) {
1135 event = cpuc->event_list[i];
1139 * we can avoid reprogramming counter if:
1140 * - assigned same counter as last time
1141 * - running on same CPU as last time
1142 * - no other event has used the counter since
1144 if (hwc->idx == -1 ||
1145 match_prev_assignment(hwc, cpuc, i))
1149 * Ensure we don't accidentally enable a stopped
1150 * counter simply because we rescheduled.
1152 if (hwc->state & PERF_HES_STOPPED)
1153 hwc->state |= PERF_HES_ARCH;
1155 x86_pmu_stop(event, PERF_EF_UPDATE);
1159 * step2: reprogram moved events into new counters
1161 for (i = 0; i < cpuc->n_events; i++) {
1162 event = cpuc->event_list[i];
1165 if (!match_prev_assignment(hwc, cpuc, i))
1166 x86_assign_hw_event(event, cpuc, i);
1167 else if (i < n_running)
1170 if (hwc->state & PERF_HES_ARCH)
1173 x86_pmu_start(event, PERF_EF_RELOAD);
1176 perf_events_lapic_init();
1182 x86_pmu.enable_all(added);
1185 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1188 * Set the next IRQ period, based on the hwc->period_left value.
1189 * To be called with the event disabled in hw:
1191 int x86_perf_event_set_period(struct perf_event *event)
1193 struct hw_perf_event *hwc = &event->hw;
1194 s64 left = local64_read(&hwc->period_left);
1195 s64 period = hwc->sample_period;
1196 int ret = 0, idx = hwc->idx;
1198 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1202 * If we are way outside a reasonable range then just skip forward:
1204 if (unlikely(left <= -period)) {
1206 local64_set(&hwc->period_left, left);
1207 hwc->last_period = period;
1211 if (unlikely(left <= 0)) {
1213 local64_set(&hwc->period_left, left);
1214 hwc->last_period = period;
1218 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1220 if (unlikely(left < 2))
1223 if (left > x86_pmu.max_period)
1224 left = x86_pmu.max_period;
1226 if (x86_pmu.limit_period)
1227 left = x86_pmu.limit_period(event, left);
1229 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1232 * The hw event starts counting from this event offset,
1233 * mark it to be able to extra future deltas:
1235 local64_set(&hwc->prev_count, (u64)-left);
1237 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1240 * Due to erratum on certan cpu we need
1241 * a second write to be sure the register
1242 * is updated properly
1244 if (x86_pmu.perfctr_second_write) {
1245 wrmsrl(hwc->event_base,
1246 (u64)(-left) & x86_pmu.cntval_mask);
1249 perf_event_update_userpage(event);
1254 void x86_pmu_enable_event(struct perf_event *event)
1256 if (__this_cpu_read(cpu_hw_events.enabled))
1257 __x86_pmu_enable_event(&event->hw,
1258 ARCH_PERFMON_EVENTSEL_ENABLE);
1262 * Add a single event to the PMU.
1264 * The event is added to the group of enabled events
1265 * but only if it can be scheduled with existing events.
1267 static int x86_pmu_add(struct perf_event *event, int flags)
1269 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1270 struct hw_perf_event *hwc;
1271 int assign[X86_PMC_IDX_MAX];
1276 n0 = cpuc->n_events;
1277 ret = n = collect_events(cpuc, event, false);
1281 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1282 if (!(flags & PERF_EF_START))
1283 hwc->state |= PERF_HES_ARCH;
1286 * If group events scheduling transaction was started,
1287 * skip the schedulability test here, it will be performed
1288 * at commit time (->commit_txn) as a whole.
1290 * If commit fails, we'll call ->del() on all events
1291 * for which ->add() was called.
1293 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1296 ret = x86_pmu.schedule_events(cpuc, n, assign);
1300 * copy new assignment, now we know it is possible
1301 * will be used by hw_perf_enable()
1303 memcpy(cpuc->assign, assign, n*sizeof(int));
1307 * Commit the collect_events() state. See x86_pmu_del() and
1311 cpuc->n_added += n - n0;
1312 cpuc->n_txn += n - n0;
1316 * This is before x86_pmu_enable() will call x86_pmu_start(),
1317 * so we enable LBRs before an event needs them etc..
1327 static void x86_pmu_start(struct perf_event *event, int flags)
1329 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1330 int idx = event->hw.idx;
1332 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1335 if (WARN_ON_ONCE(idx == -1))
1338 if (flags & PERF_EF_RELOAD) {
1339 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1340 x86_perf_event_set_period(event);
1343 event->hw.state = 0;
1345 cpuc->events[idx] = event;
1346 __set_bit(idx, cpuc->active_mask);
1347 __set_bit(idx, cpuc->running);
1348 x86_pmu.enable(event);
1349 perf_event_update_userpage(event);
1352 void perf_event_print_debug(void)
1354 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1356 struct cpu_hw_events *cpuc;
1357 unsigned long flags;
1360 if (!x86_pmu.num_counters)
1363 local_irq_save(flags);
1365 cpu = smp_processor_id();
1366 cpuc = &per_cpu(cpu_hw_events, cpu);
1368 if (x86_pmu.version >= 2) {
1369 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1370 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1371 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1372 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1375 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1376 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1377 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1378 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1379 if (x86_pmu.pebs_constraints) {
1380 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1381 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1383 if (x86_pmu.lbr_nr) {
1384 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1385 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1388 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1390 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1391 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1392 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1394 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1396 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1397 cpu, idx, pmc_ctrl);
1398 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1399 cpu, idx, pmc_count);
1400 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1401 cpu, idx, prev_left);
1403 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1404 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1406 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1407 cpu, idx, pmc_count);
1409 local_irq_restore(flags);
1412 void x86_pmu_stop(struct perf_event *event, int flags)
1414 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1415 struct hw_perf_event *hwc = &event->hw;
1417 if (test_bit(hwc->idx, cpuc->active_mask)) {
1418 x86_pmu.disable(event);
1419 __clear_bit(hwc->idx, cpuc->active_mask);
1420 cpuc->events[hwc->idx] = NULL;
1421 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1422 hwc->state |= PERF_HES_STOPPED;
1425 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1427 * Drain the remaining delta count out of a event
1428 * that we are disabling:
1430 x86_perf_event_update(event);
1431 hwc->state |= PERF_HES_UPTODATE;
1435 static void x86_pmu_del(struct perf_event *event, int flags)
1437 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1441 * If we're called during a txn, we only need to undo x86_pmu.add.
1442 * The events never got scheduled and ->cancel_txn will truncate
1445 * XXX assumes any ->del() called during a TXN will only be on
1446 * an event added during that same TXN.
1448 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1452 * Not a TXN, therefore cleanup properly.
1454 x86_pmu_stop(event, PERF_EF_UPDATE);
1456 for (i = 0; i < cpuc->n_events; i++) {
1457 if (event == cpuc->event_list[i])
1461 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1464 /* If we have a newly added event; make sure to decrease n_added. */
1465 if (i >= cpuc->n_events - cpuc->n_added)
1468 if (x86_pmu.put_event_constraints)
1469 x86_pmu.put_event_constraints(cpuc, event);
1471 /* Delete the array entry. */
1472 while (++i < cpuc->n_events) {
1473 cpuc->event_list[i-1] = cpuc->event_list[i];
1474 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1476 cpuc->event_constraint[i-1] = NULL;
1479 perf_event_update_userpage(event);
1484 * This is after x86_pmu_stop(); so we disable LBRs after any
1485 * event can need them etc..
1491 int x86_pmu_handle_irq(struct pt_regs *regs)
1493 struct perf_sample_data data;
1494 struct cpu_hw_events *cpuc;
1495 struct perf_event *event;
1496 int idx, handled = 0;
1499 cpuc = this_cpu_ptr(&cpu_hw_events);
1502 * Some chipsets need to unmask the LVTPC in a particular spot
1503 * inside the nmi handler. As a result, the unmasking was pushed
1504 * into all the nmi handlers.
1506 * This generic handler doesn't seem to have any issues where the
1507 * unmasking occurs so it was left at the top.
1509 apic_write(APIC_LVTPC, APIC_DM_NMI);
1511 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1512 if (!test_bit(idx, cpuc->active_mask))
1515 event = cpuc->events[idx];
1517 val = x86_perf_event_update(event);
1518 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1525 perf_sample_data_init(&data, 0, event->hw.last_period);
1527 if (!x86_perf_event_set_period(event))
1530 if (perf_event_overflow(event, &data, regs))
1531 x86_pmu_stop(event, 0);
1535 inc_irq_stat(apic_perf_irqs);
1540 void perf_events_lapic_init(void)
1542 if (!x86_pmu.apic || !x86_pmu_initialized())
1546 * Always use NMI for PMU
1548 apic_write(APIC_LVTPC, APIC_DM_NMI);
1552 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1559 * All PMUs/events that share this PMI handler should make sure to
1560 * increment active_events for their events.
1562 if (!atomic_read(&active_events))
1565 start_clock = sched_clock();
1566 ret = x86_pmu.handle_irq(regs);
1567 finish_clock = sched_clock();
1569 perf_sample_event_took(finish_clock - start_clock);
1573 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1575 struct event_constraint emptyconstraint;
1576 struct event_constraint unconstrained;
1578 static int x86_pmu_prepare_cpu(unsigned int cpu)
1580 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1583 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1584 cpuc->kfree_on_online[i] = NULL;
1585 if (x86_pmu.cpu_prepare)
1586 return x86_pmu.cpu_prepare(cpu);
1590 static int x86_pmu_dead_cpu(unsigned int cpu)
1592 if (x86_pmu.cpu_dead)
1593 x86_pmu.cpu_dead(cpu);
1597 static int x86_pmu_online_cpu(unsigned int cpu)
1599 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1602 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1603 kfree(cpuc->kfree_on_online[i]);
1604 cpuc->kfree_on_online[i] = NULL;
1609 static int x86_pmu_starting_cpu(unsigned int cpu)
1611 if (x86_pmu.cpu_starting)
1612 x86_pmu.cpu_starting(cpu);
1616 static int x86_pmu_dying_cpu(unsigned int cpu)
1618 if (x86_pmu.cpu_dying)
1619 x86_pmu.cpu_dying(cpu);
1623 static void __init pmu_check_apic(void)
1625 if (boot_cpu_has(X86_FEATURE_APIC))
1629 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1630 pr_info("no hardware sampling interrupt available.\n");
1633 * If we have a PMU initialized but no APIC
1634 * interrupts, we cannot sample hardware
1635 * events (user-space has to fall back and
1636 * sample via a hrtimer based software event):
1638 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1642 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1647 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1649 struct perf_pmu_events_attr *pmu_attr =
1650 container_of(attr, struct perf_pmu_events_attr, attr);
1653 if (pmu_attr->id < x86_pmu.max_events)
1654 config = x86_pmu.event_map(pmu_attr->id);
1656 /* string trumps id */
1657 if (pmu_attr->event_str)
1658 return sprintf(page, "%s", pmu_attr->event_str);
1660 return x86_pmu.events_sysfs_show(page, config);
1662 EXPORT_SYMBOL_GPL(events_sysfs_show);
1664 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1667 struct perf_pmu_events_ht_attr *pmu_attr =
1668 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1671 * Report conditional events depending on Hyper-Threading.
1673 * This is overly conservative as usually the HT special
1674 * handling is not needed if the other CPU thread is idle.
1676 * Note this does not (and cannot) handle the case when thread
1677 * siblings are invisible, for example with virtualization
1678 * if they are owned by some other guest. The user tool
1679 * has to re-read when a thread sibling gets onlined later.
1681 return sprintf(page, "%s",
1682 topology_max_smt_threads() > 1 ?
1683 pmu_attr->event_str_ht :
1684 pmu_attr->event_str_noht);
1687 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1688 EVENT_ATTR(instructions, INSTRUCTIONS );
1689 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1690 EVENT_ATTR(cache-misses, CACHE_MISSES );
1691 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1692 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1693 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1694 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1695 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1696 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1698 static struct attribute *empty_attrs;
1700 static struct attribute *events_attr[] = {
1701 EVENT_PTR(CPU_CYCLES),
1702 EVENT_PTR(INSTRUCTIONS),
1703 EVENT_PTR(CACHE_REFERENCES),
1704 EVENT_PTR(CACHE_MISSES),
1705 EVENT_PTR(BRANCH_INSTRUCTIONS),
1706 EVENT_PTR(BRANCH_MISSES),
1707 EVENT_PTR(BUS_CYCLES),
1708 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1709 EVENT_PTR(STALLED_CYCLES_BACKEND),
1710 EVENT_PTR(REF_CPU_CYCLES),
1715 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1716 * out of events_attr attributes.
1719 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1721 struct perf_pmu_events_attr *pmu_attr;
1723 if (idx >= x86_pmu.max_events)
1726 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1728 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1731 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1733 .attrs = events_attr,
1734 .is_visible = is_visible,
1737 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1739 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1740 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1741 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1742 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1743 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1744 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1748 * We have whole page size to spend and just little data
1749 * to write, so we can safely use sprintf.
1751 ret = sprintf(page, "event=0x%02llx", event);
1754 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1757 ret += sprintf(page + ret, ",edge");
1760 ret += sprintf(page + ret, ",pc");
1763 ret += sprintf(page + ret, ",any");
1766 ret += sprintf(page + ret, ",inv");
1769 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1771 ret += sprintf(page + ret, "\n");
1776 static struct attribute_group x86_pmu_attr_group;
1777 static struct attribute_group x86_pmu_caps_group;
1779 static int __init init_hw_perf_events(void)
1781 struct x86_pmu_quirk *quirk;
1784 pr_info("Performance Events: ");
1786 switch (boot_cpu_data.x86_vendor) {
1787 case X86_VENDOR_INTEL:
1788 err = intel_pmu_init();
1790 case X86_VENDOR_AMD:
1791 err = amd_pmu_init();
1793 case X86_VENDOR_HYGON:
1794 err = amd_pmu_init();
1795 x86_pmu.name = "HYGON";
1801 pr_cont("no PMU driver, software events only.\n");
1807 /* sanity check that the hardware exists or is emulated */
1808 if (!check_hw_exists())
1811 pr_cont("%s PMU driver.\n", x86_pmu.name);
1813 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1815 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1818 if (!x86_pmu.intel_ctrl)
1819 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1821 perf_events_lapic_init();
1822 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1824 unconstrained = (struct event_constraint)
1825 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1826 0, x86_pmu.num_counters, 0, 0);
1828 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1830 if (!x86_pmu.events_sysfs_show)
1831 x86_pmu_events_group.attrs = &empty_attrs;
1833 pmu.attr_update = x86_pmu.attr_update;
1835 pr_info("... version: %d\n", x86_pmu.version);
1836 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1837 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1838 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1839 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1840 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1841 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1844 * Install callbacks. Core will call them for each online
1847 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
1848 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1852 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1853 "perf/x86:starting", x86_pmu_starting_cpu,
1858 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
1859 x86_pmu_online_cpu, NULL);
1863 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1870 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1872 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1874 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1877 early_initcall(init_hw_perf_events);
1879 static inline void x86_pmu_read(struct perf_event *event)
1882 return x86_pmu.read(event);
1883 x86_perf_event_update(event);
1887 * Start group events scheduling transaction
1888 * Set the flag to make pmu::enable() not perform the
1889 * schedulability test, it will be performed at commit time
1891 * We only support PERF_PMU_TXN_ADD transactions. Save the
1892 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1895 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1899 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
1901 cpuc->txn_flags = txn_flags;
1902 if (txn_flags & ~PERF_PMU_TXN_ADD)
1905 perf_pmu_disable(pmu);
1906 __this_cpu_write(cpu_hw_events.n_txn, 0);
1910 * Stop group events scheduling transaction
1911 * Clear the flag and pmu::enable() will perform the
1912 * schedulability test.
1914 static void x86_pmu_cancel_txn(struct pmu *pmu)
1916 unsigned int txn_flags;
1917 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1919 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1921 txn_flags = cpuc->txn_flags;
1922 cpuc->txn_flags = 0;
1923 if (txn_flags & ~PERF_PMU_TXN_ADD)
1927 * Truncate collected array by the number of events added in this
1928 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1930 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1931 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1932 perf_pmu_enable(pmu);
1936 * Commit group events scheduling transaction
1937 * Perform the group schedulability test as a whole
1938 * Return 0 if success
1940 * Does not cancel the transaction on failure; expects the caller to do this.
1942 static int x86_pmu_commit_txn(struct pmu *pmu)
1944 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1945 int assign[X86_PMC_IDX_MAX];
1948 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1950 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1951 cpuc->txn_flags = 0;
1957 if (!x86_pmu_initialized())
1960 ret = x86_pmu.schedule_events(cpuc, n, assign);
1965 * copy new assignment, now we know it is possible
1966 * will be used by hw_perf_enable()
1968 memcpy(cpuc->assign, assign, n*sizeof(int));
1970 cpuc->txn_flags = 0;
1971 perf_pmu_enable(pmu);
1975 * a fake_cpuc is used to validate event groups. Due to
1976 * the extra reg logic, we need to also allocate a fake
1977 * per_core and per_cpu structure. Otherwise, group events
1978 * using extra reg may conflict without the kernel being
1979 * able to catch this when the last event gets added to
1982 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1984 intel_cpuc_finish(cpuc);
1988 static struct cpu_hw_events *allocate_fake_cpuc(void)
1990 struct cpu_hw_events *cpuc;
1991 int cpu = raw_smp_processor_id();
1993 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1995 return ERR_PTR(-ENOMEM);
1998 if (intel_cpuc_prepare(cpuc, cpu))
2003 free_fake_cpuc(cpuc);
2004 return ERR_PTR(-ENOMEM);
2008 * validate that we can schedule this event
2010 static int validate_event(struct perf_event *event)
2012 struct cpu_hw_events *fake_cpuc;
2013 struct event_constraint *c;
2016 fake_cpuc = allocate_fake_cpuc();
2017 if (IS_ERR(fake_cpuc))
2018 return PTR_ERR(fake_cpuc);
2020 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2022 if (!c || !c->weight)
2025 if (x86_pmu.put_event_constraints)
2026 x86_pmu.put_event_constraints(fake_cpuc, event);
2028 free_fake_cpuc(fake_cpuc);
2034 * validate a single event group
2036 * validation include:
2037 * - check events are compatible which each other
2038 * - events do not compete for the same counter
2039 * - number of events <= number of counters
2041 * validation ensures the group can be loaded onto the
2042 * PMU if it was the only group available.
2044 static int validate_group(struct perf_event *event)
2046 struct perf_event *leader = event->group_leader;
2047 struct cpu_hw_events *fake_cpuc;
2048 int ret = -EINVAL, n;
2050 fake_cpuc = allocate_fake_cpuc();
2051 if (IS_ERR(fake_cpuc))
2052 return PTR_ERR(fake_cpuc);
2054 * the event is not yet connected with its
2055 * siblings therefore we must first collect
2056 * existing siblings, then add the new event
2057 * before we can simulate the scheduling
2059 n = collect_events(fake_cpuc, leader, true);
2063 fake_cpuc->n_events = n;
2064 n = collect_events(fake_cpuc, event, false);
2068 fake_cpuc->n_events = 0;
2069 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2072 free_fake_cpuc(fake_cpuc);
2076 static int x86_pmu_event_init(struct perf_event *event)
2081 switch (event->attr.type) {
2083 case PERF_TYPE_HARDWARE:
2084 case PERF_TYPE_HW_CACHE:
2091 err = __x86_pmu_event_init(event);
2094 * we temporarily connect event to its pmu
2095 * such that validate_group() can classify
2096 * it as an x86 event using is_x86_event()
2101 if (event->group_leader != event)
2102 err = validate_group(event);
2104 err = validate_event(event);
2110 event->destroy(event);
2111 event->destroy = NULL;
2114 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2115 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2116 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2121 static void refresh_pce(void *ignored)
2123 load_mm_cr4_irqsoff(this_cpu_read(cpu_tlbstate.loaded_mm));
2126 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2128 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2132 * This function relies on not being called concurrently in two
2133 * tasks in the same mm. Otherwise one task could observe
2134 * perf_rdpmc_allowed > 1 and return all the way back to
2135 * userspace with CR4.PCE clear while another task is still
2136 * doing on_each_cpu_mask() to propagate CR4.PCE.
2138 * For now, this can't happen because all callers hold mmap_sem
2139 * for write. If this changes, we'll need a different solution.
2141 lockdep_assert_held_write(&mm->mmap_sem);
2143 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2144 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2147 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2150 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2153 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2154 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2157 static int x86_pmu_event_idx(struct perf_event *event)
2159 int idx = event->hw.idx;
2161 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2164 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2165 idx -= INTEL_PMC_IDX_FIXED;
2172 static ssize_t get_attr_rdpmc(struct device *cdev,
2173 struct device_attribute *attr,
2176 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2179 static ssize_t set_attr_rdpmc(struct device *cdev,
2180 struct device_attribute *attr,
2181 const char *buf, size_t count)
2186 ret = kstrtoul(buf, 0, &val);
2193 if (x86_pmu.attr_rdpmc_broken)
2196 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2198 * Changing into or out of always available, aka
2199 * perf-event-bypassing mode. This path is extremely slow,
2200 * but only root can trigger it, so it's okay.
2203 static_branch_inc(&rdpmc_always_available_key);
2205 static_branch_dec(&rdpmc_always_available_key);
2206 on_each_cpu(refresh_pce, NULL, 1);
2209 x86_pmu.attr_rdpmc = val;
2214 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2216 static struct attribute *x86_pmu_attrs[] = {
2217 &dev_attr_rdpmc.attr,
2221 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2222 .attrs = x86_pmu_attrs,
2225 static ssize_t max_precise_show(struct device *cdev,
2226 struct device_attribute *attr,
2229 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2232 static DEVICE_ATTR_RO(max_precise);
2234 static struct attribute *x86_pmu_caps_attrs[] = {
2235 &dev_attr_max_precise.attr,
2239 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2241 .attrs = x86_pmu_caps_attrs,
2244 static const struct attribute_group *x86_pmu_attr_groups[] = {
2245 &x86_pmu_attr_group,
2246 &x86_pmu_format_group,
2247 &x86_pmu_events_group,
2248 &x86_pmu_caps_group,
2252 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2254 if (x86_pmu.sched_task)
2255 x86_pmu.sched_task(ctx, sched_in);
2258 void perf_check_microcode(void)
2260 if (x86_pmu.check_microcode)
2261 x86_pmu.check_microcode();
2264 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2266 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2269 if (value && x86_pmu.limit_period) {
2270 if (x86_pmu.limit_period(event, value) > value)
2277 static int x86_pmu_aux_output_match(struct perf_event *event)
2279 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2282 if (x86_pmu.aux_output_match)
2283 return x86_pmu.aux_output_match(event);
2288 static struct pmu pmu = {
2289 .pmu_enable = x86_pmu_enable,
2290 .pmu_disable = x86_pmu_disable,
2292 .attr_groups = x86_pmu_attr_groups,
2294 .event_init = x86_pmu_event_init,
2296 .event_mapped = x86_pmu_event_mapped,
2297 .event_unmapped = x86_pmu_event_unmapped,
2301 .start = x86_pmu_start,
2302 .stop = x86_pmu_stop,
2303 .read = x86_pmu_read,
2305 .start_txn = x86_pmu_start_txn,
2306 .cancel_txn = x86_pmu_cancel_txn,
2307 .commit_txn = x86_pmu_commit_txn,
2309 .event_idx = x86_pmu_event_idx,
2310 .sched_task = x86_pmu_sched_task,
2311 .task_ctx_size = sizeof(struct x86_perf_task_context),
2312 .check_period = x86_pmu_check_period,
2314 .aux_output_match = x86_pmu_aux_output_match,
2317 void arch_perf_update_userpage(struct perf_event *event,
2318 struct perf_event_mmap_page *userpg, u64 now)
2320 struct cyc2ns_data data;
2323 userpg->cap_user_time = 0;
2324 userpg->cap_user_time_zero = 0;
2325 userpg->cap_user_rdpmc =
2326 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2327 userpg->pmc_width = x86_pmu.cntval_bits;
2329 if (!using_native_sched_clock() || !sched_clock_stable())
2332 cyc2ns_read_begin(&data);
2334 offset = data.cyc2ns_offset + __sched_clock_offset;
2337 * Internal timekeeping for enabled/running/stopped times
2338 * is always in the local_clock domain.
2340 userpg->cap_user_time = 1;
2341 userpg->time_mult = data.cyc2ns_mul;
2342 userpg->time_shift = data.cyc2ns_shift;
2343 userpg->time_offset = offset - now;
2346 * cap_user_time_zero doesn't make sense when we're using a different
2347 * time base for the records.
2349 if (!event->attr.use_clockid) {
2350 userpg->cap_user_time_zero = 1;
2351 userpg->time_zero = offset;
2358 * Determine whether the regs were taken from an irq/exception handler rather
2359 * than from perf_arch_fetch_caller_regs().
2361 static bool perf_hw_regs(struct pt_regs *regs)
2363 return regs->flags & X86_EFLAGS_FIXED;
2367 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2369 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2370 struct unwind_state state;
2373 if (guest_cbs && guest_cbs->is_in_guest()) {
2374 /* TODO: We don't support guest os callchain now */
2378 if (perf_callchain_store(entry, regs->ip))
2381 if (perf_hw_regs(regs))
2382 unwind_start(&state, current, regs, NULL);
2384 unwind_start(&state, current, NULL, (void *)regs->sp);
2386 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2387 addr = unwind_get_return_address(&state);
2388 if (!addr || perf_callchain_store(entry, addr))
2394 valid_user_frame(const void __user *fp, unsigned long size)
2396 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2399 static unsigned long get_segment_base(unsigned int segment)
2401 struct desc_struct *desc;
2402 unsigned int idx = segment >> 3;
2404 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2405 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2406 struct ldt_struct *ldt;
2408 /* IRQs are off, so this synchronizes with smp_store_release */
2409 ldt = READ_ONCE(current->active_mm->context.ldt);
2410 if (!ldt || idx >= ldt->nr_entries)
2413 desc = &ldt->entries[idx];
2418 if (idx >= GDT_ENTRIES)
2421 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2424 return get_desc_base(desc);
2427 #ifdef CONFIG_IA32_EMULATION
2429 #include <linux/compat.h>
2432 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2434 /* 32-bit process in 64-bit kernel. */
2435 unsigned long ss_base, cs_base;
2436 struct stack_frame_ia32 frame;
2437 const void __user *fp;
2439 if (!test_thread_flag(TIF_IA32))
2442 cs_base = get_segment_base(regs->cs);
2443 ss_base = get_segment_base(regs->ss);
2445 fp = compat_ptr(ss_base + regs->bp);
2446 pagefault_disable();
2447 while (entry->nr < entry->max_stack) {
2448 unsigned long bytes;
2449 frame.next_frame = 0;
2450 frame.return_address = 0;
2452 if (!valid_user_frame(fp, sizeof(frame)))
2455 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2458 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2462 perf_callchain_store(entry, cs_base + frame.return_address);
2463 fp = compat_ptr(ss_base + frame.next_frame);
2470 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2477 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2479 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2480 struct stack_frame frame;
2481 const unsigned long __user *fp;
2483 if (guest_cbs && guest_cbs->is_in_guest()) {
2484 /* TODO: We don't support guest os callchain now */
2489 * We don't know what to do with VM86 stacks.. ignore them for now.
2491 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2494 fp = (unsigned long __user *)regs->bp;
2496 perf_callchain_store(entry, regs->ip);
2498 if (!nmi_uaccess_okay())
2501 if (perf_callchain_user32(regs, entry))
2504 pagefault_disable();
2505 while (entry->nr < entry->max_stack) {
2506 unsigned long bytes;
2508 frame.next_frame = NULL;
2509 frame.return_address = 0;
2511 if (!valid_user_frame(fp, sizeof(frame)))
2514 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2517 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2521 perf_callchain_store(entry, frame.return_address);
2522 fp = (void __user *)frame.next_frame;
2528 * Deal with code segment offsets for the various execution modes:
2530 * VM86 - the good olde 16 bit days, where the linear address is
2531 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2533 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2534 * to figure out what the 32bit base address is.
2536 * X32 - has TIF_X32 set, but is running in x86_64
2538 * X86_64 - CS,DS,SS,ES are all zero based.
2540 static unsigned long code_segment_base(struct pt_regs *regs)
2543 * For IA32 we look at the GDT/LDT segment base to convert the
2544 * effective IP to a linear address.
2547 #ifdef CONFIG_X86_32
2549 * If we are in VM86 mode, add the segment offset to convert to a
2552 if (regs->flags & X86_VM_MASK)
2553 return 0x10 * regs->cs;
2555 if (user_mode(regs) && regs->cs != __USER_CS)
2556 return get_segment_base(regs->cs);
2558 if (user_mode(regs) && !user_64bit_mode(regs) &&
2559 regs->cs != __USER32_CS)
2560 return get_segment_base(regs->cs);
2565 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2567 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2569 if (guest_cbs && guest_cbs->is_in_guest())
2570 return guest_cbs->get_guest_ip();
2572 return regs->ip + code_segment_base(regs);
2575 unsigned long perf_misc_flags(struct pt_regs *regs)
2577 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2580 if (guest_cbs && guest_cbs->is_in_guest()) {
2581 if (guest_cbs->is_user_mode())
2582 misc |= PERF_RECORD_MISC_GUEST_USER;
2584 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2586 if (user_mode(regs))
2587 misc |= PERF_RECORD_MISC_USER;
2589 misc |= PERF_RECORD_MISC_KERNEL;
2592 if (regs->flags & PERF_EFLAGS_EXACT)
2593 misc |= PERF_RECORD_MISC_EXACT_IP;
2598 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2600 cap->version = x86_pmu.version;
2601 cap->num_counters_gp = x86_pmu.num_counters;
2602 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2603 cap->bit_width_gp = x86_pmu.cntval_bits;
2604 cap->bit_width_fixed = x86_pmu.cntval_bits;
2605 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2606 cap->events_mask_len = x86_pmu.events_mask_len;
2608 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);