arch/x86/events/core.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/export.h>
  21 #include <linux/init.h>
  22 #include <linux/kdebug.h>
  23 #include <linux/sched.h>
  24 #include <linux/uaccess.h>
  25 #include <linux/slab.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28 #include <linux/device.h>
  29 #include <linux/nospec.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/stacktrace.h>
  33 #include <asm/nmi.h>
  34 #include <asm/smp.h>
  35 #include <asm/alternative.h>
  36 #include <asm/mmu_context.h>
  37 #include <asm/tlbflush.h>
  38 #include <asm/timer.h>
  39 #include <asm/desc.h>
  40 #include <asm/ldt.h>
  41 #include <asm/unwind.h>
  42
  43 #include "perf_event.h"
  44
  45 struct x86_pmu x86_pmu __read_mostly;
  46
  47 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  48         .enabled = 1,
  49 };
  50
  51 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  52
  53 u64 __read_mostly hw_cache_event_ids
  54                                 [PERF_COUNT_HW_CACHE_MAX]
  55                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  56                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  57 u64 __read_mostly hw_cache_extra_regs
  58                                 [PERF_COUNT_HW_CACHE_MAX]
  59                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  60                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  61
  62 /*
  63  * Propagate event elapsed time into the generic event.
  64  * Can only be executed on the CPU where the event is active.
  65  * Returns the delta events processed.
  66  */
  67 u64 x86_perf_event_update(struct perf_event *event)
  68 {
  69         struct hw_perf_event *hwc = &event->hw;
  70         int shift = 64 - x86_pmu.cntval_bits;
  71         u64 prev_raw_count, new_raw_count;
  72         int idx = hwc->idx;
  73         u64 delta;
  74
  75         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  76                 return 0;
  77
  78         /*
  79          * Careful: an NMI might modify the previous event value.
  80          *
  81          * Our tactic to handle this is to first atomically read and
  82          * exchange a new raw count - then add that new-prev delta
  83          * count to the generic event atomically:
  84          */
  85 again:
  86         prev_raw_count = local64_read(&hwc->prev_count);
  87         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  88
  89         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  90                                         new_raw_count) != prev_raw_count)
  91                 goto again;
  92
  93         /*
  94          * Now we have the new raw value and have updated the prev
  95          * timestamp already. We can now calculate the elapsed delta
  96          * (event-)time and add that to the generic event.
  97          *
  98          * Careful, not all hw sign-extends above the physical width
  99          * of the count.
 100          */
 101         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 102         delta >>= shift;
 103
 104         local64_add(delta, &event->count);
 105         local64_sub(delta, &hwc->period_left);
 106
 107         return new_raw_count;
 108 }
 109
 110 /*
 111  * Find and validate any extra registers to set up.
 112  */
 113 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 114 {
 115         struct hw_perf_event_extra *reg;
 116         struct extra_reg *er;
 117
 118         reg = &event->hw.extra_reg;
 119
 120         if (!x86_pmu.extra_regs)
 121                 return 0;
 122
 123         for (er = x86_pmu.extra_regs; er->msr; er++) {
 124                 if (er->event != (config & er->config_mask))
 125                         continue;
 126                 if (event->attr.config1 & ~er->valid_mask)
 127                         return -EINVAL;
 128                 /* Check if the extra msrs can be safely accessed*/
 129                 if (!er->extra_msr_access)
 130                         return -ENXIO;
 131
 132                 reg->idx = er->idx;
 133                 reg->config = event->attr.config1;
 134                 reg->reg = er->msr;
 135                 break;
 136         }
 137         return 0;
 138 }
 139
 140 static atomic_t active_events;
 141 static atomic_t pmc_refcount;
 142 static DEFINE_MUTEX(pmc_reserve_mutex);
 143
 144 #ifdef CONFIG_X86_LOCAL_APIC
 145
 146 static bool reserve_pmc_hardware(void)
 147 {
 148         int i;
 149
 150         for (i = 0; i < x86_pmu.num_counters; i++) {
 151                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 152                         goto perfctr_fail;
 153         }
 154
 155         for (i = 0; i < x86_pmu.num_counters; i++) {
 156                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 157                         goto eventsel_fail;
 158         }
 159
 160         return true;
 161
 162 eventsel_fail:
 163         for (i--; i >= 0; i--)
 164                 release_evntsel_nmi(x86_pmu_config_addr(i));
 165
 166         i = x86_pmu.num_counters;
 167
 168 perfctr_fail:
 169         for (i--; i >= 0; i--)
 170                 release_perfctr_nmi(x86_pmu_event_addr(i));
 171
 172         return false;
 173 }
 174
 175 static void release_pmc_hardware(void)
 176 {
 177         int i;
 178
 179         for (i = 0; i < x86_pmu.num_counters; i++) {
 180                 release_perfctr_nmi(x86_pmu_event_addr(i));
 181                 release_evntsel_nmi(x86_pmu_config_addr(i));
 182         }
 183 }
 184
 185 #else
 186
 187 static bool reserve_pmc_hardware(void) { return true; }
 188 static void release_pmc_hardware(void) {}
 189
 190 #endif
 191
 192 static bool check_hw_exists(void)
 193 {
 194         u64 val, val_fail = -1, val_new= ~0;
 195         int i, reg, reg_fail = -1, ret = 0;
 196         int bios_fail = 0;
 197         int reg_safe = -1;
 198
 199         /*
 200          * Check to see if the BIOS enabled any of the counters, if so
 201          * complain and bail.
 202          */
 203         for (i = 0; i < x86_pmu.num_counters; i++) {
 204                 reg = x86_pmu_config_addr(i);
 205                 ret = rdmsrl_safe(reg, &val);
 206                 if (ret)
 207                         goto msr_fail;
 208                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 209                         bios_fail = 1;
 210                         val_fail = val;
 211                         reg_fail = reg;
 212                 } else {
 213                         reg_safe = i;
 214                 }
 215         }
 216
 217         if (x86_pmu.num_counters_fixed) {
 218                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 219                 ret = rdmsrl_safe(reg, &val);
 220                 if (ret)
 221                         goto msr_fail;
 222                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 223                         if (val & (0x03 << i*4)) {
 224                                 bios_fail = 1;
 225                                 val_fail = val;
 226                                 reg_fail = reg;
 227                         }
 228                 }
 229         }
 230
 231         /*
 232          * If all the counters are enabled, the below test will always
 233          * fail.  The tools will also become useless in this scenario.
 234          * Just fail and disable the hardware counters.
 235          */
 236
 237         if (reg_safe == -1) {
 238                 reg = reg_safe;
 239                 goto msr_fail;
 240         }
 241
 242         /*
 243          * Read the current value, change it and read it back to see if it
 244          * matches, this is needed to detect certain hardware emulators
 245          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 246          */
 247         reg = x86_pmu_event_addr(reg_safe);
 248         if (rdmsrl_safe(reg, &val))
 249                 goto msr_fail;
 250         val ^= 0xffffUL;
 251         ret = wrmsrl_safe(reg, val);
 252         ret |= rdmsrl_safe(reg, &val_new);
 253         if (ret || val != val_new)
 254                 goto msr_fail;
 255
 256         /*
 257          * We still allow the PMU driver to operate:
 258          */
 259         if (bios_fail) {
 260                 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
 261                 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
 262                               reg_fail, val_fail);
 263         }
 264
 265         return true;
 266
 267 msr_fail:
 268         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
 269                 pr_cont("PMU not available due to virtualization, using software events only.\n");
 270         } else {
 271                 pr_cont("Broken PMU hardware detected, using software events only.\n");
 272                 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
 273                        reg, val_new);
 274         }
 275
 276         return false;
 277 }
 278
 279 static void hw_perf_event_destroy(struct perf_event *event)
 280 {
 281         x86_release_hardware();
 282         atomic_dec(&active_events);
 283 }
 284
 285 void hw_perf_lbr_event_destroy(struct perf_event *event)
 286 {
 287         hw_perf_event_destroy(event);
 288
 289         /* undo the lbr/bts event accounting */
 290         x86_del_exclusive(x86_lbr_exclusive_lbr);
 291 }
 292
 293 static inline int x86_pmu_initialized(void)
 294 {
 295         return x86_pmu.handle_irq != NULL;
 296 }
 297
 298 static inline int
 299 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 300 {
 301         struct perf_event_attr *attr = &event->attr;
 302         unsigned int cache_type, cache_op, cache_result;
 303         u64 config, val;
 304
 305         config = attr->config;
 306
 307         cache_type = (config >> 0) & 0xff;
 308         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 309                 return -EINVAL;
 310         cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
 311
 312         cache_op = (config >>  8) & 0xff;
 313         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 314                 return -EINVAL;
 315         cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
 316
 317         cache_result = (config >> 16) & 0xff;
 318         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 319                 return -EINVAL;
 320         cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
 321
 322         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 323
 324         if (val == 0)
 325                 return -ENOENT;
 326
 327         if (val == -1)
 328                 return -EINVAL;
 329
 330         hwc->config |= val;
 331         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 332         return x86_pmu_extra_regs(val, event);
 333 }
 334
 335 int x86_reserve_hardware(void)
 336 {
 337         int err = 0;
 338
 339         if (!atomic_inc_not_zero(&pmc_refcount)) {
 340                 mutex_lock(&pmc_reserve_mutex);
 341                 if (atomic_read(&pmc_refcount) == 0) {
 342                         if (!reserve_pmc_hardware())
 343                                 err = -EBUSY;
 344                         else
 345                                 reserve_ds_buffers();
 346                 }
 347                 if (!err)
 348                         atomic_inc(&pmc_refcount);
 349                 mutex_unlock(&pmc_reserve_mutex);
 350         }
 351
 352         return err;
 353 }
 354
 355 void x86_release_hardware(void)
 356 {
 357         if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
 358                 release_pmc_hardware();
 359                 release_ds_buffers();
 360                 mutex_unlock(&pmc_reserve_mutex);
 361         }
 362 }
 363
 364 /*
 365  * Check if we can create event of a certain type (that no conflicting events
 366  * are present).
 367  */
 368 int x86_add_exclusive(unsigned int what)
 369 {
 370         int i;
 371
 372         /*
 373          * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
 374          * LBR and BTS are still mutually exclusive.
 375          */
 376         if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
 377                 goto out;
 378
 379         if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
 380                 mutex_lock(&pmc_reserve_mutex);
 381                 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
 382                         if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 383                                 goto fail_unlock;
 384                 }
 385                 atomic_inc(&x86_pmu.lbr_exclusive[what]);
 386                 mutex_unlock(&pmc_reserve_mutex);
 387         }
 388
 389 out:
 390         atomic_inc(&active_events);
 391         return 0;
 392
 393 fail_unlock:
 394         mutex_unlock(&pmc_reserve_mutex);
 395         return -EBUSY;
 396 }
 397
 398 void x86_del_exclusive(unsigned int what)
 399 {
 400         atomic_dec(&active_events);
 401
 402         /*
 403          * See the comment in x86_add_exclusive().
 404          */
 405         if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
 406                 return;
 407
 408         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 409 }
 410
 411 int x86_setup_perfctr(struct perf_event *event)
 412 {
 413         struct perf_event_attr *attr = &event->attr;
 414         struct hw_perf_event *hwc = &event->hw;
 415         u64 config;
 416
 417         if (!is_sampling_event(event)) {
 418                 hwc->sample_period = x86_pmu.max_period;
 419                 hwc->last_period = hwc->sample_period;
 420                 local64_set(&hwc->period_left, hwc->sample_period);
 421         }
 422
 423         if (attr->type == PERF_TYPE_RAW)
 424                 return x86_pmu_extra_regs(event->attr.config, event);
 425
 426         if (attr->type == PERF_TYPE_HW_CACHE)
 427                 return set_ext_hw_attr(hwc, event);
 428
 429         if (attr->config >= x86_pmu.max_events)
 430                 return -EINVAL;
 431
 432         attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
 433
 434         /*
 435          * The generic map:
 436          */
 437         config = x86_pmu.event_map(attr->config);
 438
 439         if (config == 0)
 440                 return -ENOENT;
 441
 442         if (config == -1LL)
 443                 return -EINVAL;
 444
 445         hwc->config |= config;
 446
 447         return 0;
 448 }
 449
 450 /*
 451  * check that branch_sample_type is compatible with
 452  * settings needed for precise_ip > 1 which implies
 453  * using the LBR to capture ALL taken branches at the
 454  * priv levels of the measurement
 455  */
 456 static inline int precise_br_compat(struct perf_event *event)
 457 {
 458         u64 m = event->attr.branch_sample_type;
 459         u64 b = 0;
 460
 461         /* must capture all branches */
 462         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 463                 return 0;
 464
 465         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 466
 467         if (!event->attr.exclude_user)
 468                 b |= PERF_SAMPLE_BRANCH_USER;
 469
 470         if (!event->attr.exclude_kernel)
 471                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 472
 473         /*
 474          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 475          */
 476
 477         return m == b;
 478 }
 479
 480 int x86_pmu_hw_config(struct perf_event *event)
 481 {
 482         if (event->attr.precise_ip) {
 483                 int precise = 0;
 484
 485                 /* Support for constant skid */
 486                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 487                         precise++;
 488
 489                         /* Support for IP fixup */
 490                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 491                                 precise++;
 492
 493                         if (x86_pmu.pebs_prec_dist)
 494                                 precise++;
 495                 }
 496
 497                 if (event->attr.precise_ip > precise)
 498                         return -EOPNOTSUPP;
 499
 500                 /* There's no sense in having PEBS for non sampling events: */
 501                 if (!is_sampling_event(event))
 502                         return -EINVAL;
 503         }
 504         /*
 505          * check that PEBS LBR correction does not conflict with
 506          * whatever the user is asking with attr->branch_sample_type
 507          */
 508         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 509                 u64 *br_type = &event->attr.branch_sample_type;
 510
 511                 if (has_branch_stack(event)) {
 512                         if (!precise_br_compat(event))
 513                                 return -EOPNOTSUPP;
 514
 515                         /* branch_sample_type is compatible */
 516
 517                 } else {
 518                         /*
 519                          * user did not specify  branch_sample_type
 520                          *
 521                          * For PEBS fixups, we capture all
 522                          * the branches at the priv level of the
 523                          * event.
 524                          */
 525                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 526
 527                         if (!event->attr.exclude_user)
 528                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 529
 530                         if (!event->attr.exclude_kernel)
 531                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 532                 }
 533         }
 534
 535         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 536                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 537
 538         /*
 539          * Generate PMC IRQs:
 540          * (keep 'enabled' bit clear for now)
 541          */
 542         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 543
 544         /*
 545          * Count user and OS events unless requested not to
 546          */
 547         if (!event->attr.exclude_user)
 548                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 549         if (!event->attr.exclude_kernel)
 550                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 551
 552         if (event->attr.type == PERF_TYPE_RAW)
 553                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 554
 555         if (event->attr.sample_period && x86_pmu.limit_period) {
 556                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 557                                 event->attr.sample_period)
 558                         return -EINVAL;
 559         }
 560
 561         return x86_setup_perfctr(event);
 562 }
 563
 564 /*
 565  * Setup the hardware configuration for a given attr_type
 566  */
 567 static int __x86_pmu_event_init(struct perf_event *event)
 568 {
 569         int err;
 570
 571         if (!x86_pmu_initialized())
 572                 return -ENODEV;
 573
 574         err = x86_reserve_hardware();
 575         if (err)
 576                 return err;
 577
 578         atomic_inc(&active_events);
 579         event->destroy = hw_perf_event_destroy;
 580
 581         event->hw.idx = -1;
 582         event->hw.last_cpu = -1;
 583         event->hw.last_tag = ~0ULL;
 584
 585         /* mark unused */
 586         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 587         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 588
 589         return x86_pmu.hw_config(event);
 590 }
 591
 592 void x86_pmu_disable_all(void)
 593 {
 594         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 595         int idx;
 596
 597         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 598                 u64 val;
 599
 600                 if (!test_bit(idx, cpuc->active_mask))
 601                         continue;
 602                 rdmsrl(x86_pmu_config_addr(idx), val);
 603                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 604                         continue;
 605                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 606                 wrmsrl(x86_pmu_config_addr(idx), val);
 607         }
 608 }
 609
 610 /*
 611  * There may be PMI landing after enabled=0. The PMI hitting could be before or
 612  * after disable_all.
 613  *
 614  * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 615  * It will not be re-enabled in the NMI handler again, because enabled=0. After
 616  * handling the NMI, disable_all will be called, which will not change the
 617  * state either. If PMI hits after disable_all, the PMU is already disabled
 618  * before entering NMI handler. The NMI handler will not change the state
 619  * either.
 620  *
 621  * So either situation is harmless.
 622  */
 623 static void x86_pmu_disable(struct pmu *pmu)
 624 {
 625         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 626
 627         if (!x86_pmu_initialized())
 628                 return;
 629
 630         if (!cpuc->enabled)
 631                 return;
 632
 633         cpuc->n_added = 0;
 634         cpuc->enabled = 0;
 635         barrier();
 636
 637         x86_pmu.disable_all();
 638 }
 639
 640 void x86_pmu_enable_all(int added)
 641 {
 642         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 643         int idx;
 644
 645         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 646                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 647
 648                 if (!test_bit(idx, cpuc->active_mask))
 649                         continue;
 650
 651                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 652         }
 653 }
 654
 655 static struct pmu pmu;
 656
 657 static inline int is_x86_event(struct perf_event *event)
 658 {
 659         return event->pmu == &pmu;
 660 }
 661
 662 /*
 663  * Event scheduler state:
 664  *
 665  * Assign events iterating over all events and counters, beginning
 666  * with events with least weights first. Keep the current iterator
 667  * state in struct sched_state.
 668  */
 669 struct sched_state {
 670         int     weight;
 671         int     event;          /* event index */
 672         int     counter;        /* counter index */
 673         int     unassigned;     /* number of events to be assigned left */
 674         int     nr_gp;          /* number of GP counters used */
 675         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 676 };
 677
 678 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 679 #define SCHED_STATES_MAX        2
 680
 681 struct perf_sched {
 682         int                     max_weight;
 683         int                     max_events;
 684         int                     max_gp;
 685         int                     saved_states;
 686         struct event_constraint **constraints;
 687         struct sched_state      state;
 688         struct sched_state      saved[SCHED_STATES_MAX];
 689 };
 690
 691 /*
 692  * Initialize interator that runs through all events and counters.
 693  */
 694 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 695                             int num, int wmin, int wmax, int gpmax)
 696 {
 697         int idx;
 698
 699         memset(sched, 0, sizeof(*sched));
 700         sched->max_events       = num;
 701         sched->max_weight       = wmax;
 702         sched->max_gp           = gpmax;
 703         sched->constraints      = constraints;
 704
 705         for (idx = 0; idx < num; idx++) {
 706                 if (constraints[idx]->weight == wmin)
 707                         break;
 708         }
 709
 710         sched->state.event      = idx;          /* start with min weight */
 711         sched->state.weight     = wmin;
 712         sched->state.unassigned = num;
 713 }
 714
 715 static void perf_sched_save_state(struct perf_sched *sched)
 716 {
 717         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 718                 return;
 719
 720         sched->saved[sched->saved_states] = sched->state;
 721         sched->saved_states++;
 722 }
 723
 724 static bool perf_sched_restore_state(struct perf_sched *sched)
 725 {
 726         if (!sched->saved_states)
 727                 return false;
 728
 729         sched->saved_states--;
 730         sched->state = sched->saved[sched->saved_states];
 731
 732         /* continue with next counter: */
 733         clear_bit(sched->state.counter++, sched->state.used);
 734
 735         return true;
 736 }
 737
 738 /*
 739  * Select a counter for the current event to schedule. Return true on
 740  * success.
 741  */
 742 static bool __perf_sched_find_counter(struct perf_sched *sched)
 743 {
 744         struct event_constraint *c;
 745         int idx;
 746
 747         if (!sched->state.unassigned)
 748                 return false;
 749
 750         if (sched->state.event >= sched->max_events)
 751                 return false;
 752
 753         c = sched->constraints[sched->state.event];
 754         /* Prefer fixed purpose counters */
 755         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 756                 idx = INTEL_PMC_IDX_FIXED;
 757                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 758                         if (!__test_and_set_bit(idx, sched->state.used))
 759                                 goto done;
 760                 }
 761         }
 762
 763         /* Grab the first unused counter starting with idx */
 764         idx = sched->state.counter;
 765         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 766                 if (!__test_and_set_bit(idx, sched->state.used)) {
 767                         if (sched->state.nr_gp++ >= sched->max_gp)
 768                                 return false;
 769
 770                         goto done;
 771                 }
 772         }
 773
 774         return false;
 775
 776 done:
 777         sched->state.counter = idx;
 778
 779         if (c->overlap)
 780                 perf_sched_save_state(sched);
 781
 782         return true;
 783 }
 784
 785 static bool perf_sched_find_counter(struct perf_sched *sched)
 786 {
 787         while (!__perf_sched_find_counter(sched)) {
 788                 if (!perf_sched_restore_state(sched))
 789                         return false;
 790         }
 791
 792         return true;
 793 }
 794
 795 /*
 796  * Go through all unassigned events and find the next one to schedule.
 797  * Take events with the least weight first. Return true on success.
 798  */
 799 static bool perf_sched_next_event(struct perf_sched *sched)
 800 {
 801         struct event_constraint *c;
 802
 803         if (!sched->state.unassigned || !--sched->state.unassigned)
 804                 return false;
 805
 806         do {
 807                 /* next event */
 808                 sched->state.event++;
 809                 if (sched->state.event >= sched->max_events) {
 810                         /* next weight */
 811                         sched->state.event = 0;
 812                         sched->state.weight++;
 813                         if (sched->state.weight > sched->max_weight)
 814                                 return false;
 815                 }
 816                 c = sched->constraints[sched->state.event];
 817         } while (c->weight != sched->state.weight);
 818
 819         sched->state.counter = 0;       /* start with first counter */
 820
 821         return true;
 822 }
 823
 824 /*
 825  * Assign a counter for each event.
 826  */
 827 int perf_assign_events(struct event_constraint **constraints, int n,
 828                         int wmin, int wmax, int gpmax, int *assign)
 829 {
 830         struct perf_sched sched;
 831
 832         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 833
 834         do {
 835                 if (!perf_sched_find_counter(&sched))
 836                         break;  /* failed */
 837                 if (assign)
 838                         assign[sched.state.event] = sched.state.counter;
 839         } while (perf_sched_next_event(&sched));
 840
 841         return sched.state.unassigned;
 842 }
 843 EXPORT_SYMBOL_GPL(perf_assign_events);
 844
 845 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 846 {
 847         struct event_constraint *c;
 848         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 849         struct perf_event *e;
 850         int i, wmin, wmax, unsched = 0;
 851         struct hw_perf_event *hwc;
 852
 853         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 854
 855         if (x86_pmu.start_scheduling)
 856                 x86_pmu.start_scheduling(cpuc);
 857
 858         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 859                 cpuc->event_constraint[i] = NULL;
 860                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 861                 cpuc->event_constraint[i] = c;
 862
 863                 wmin = min(wmin, c->weight);
 864                 wmax = max(wmax, c->weight);
 865         }
 866
 867         /*
 868          * fastpath, try to reuse previous register
 869          */
 870         for (i = 0; i < n; i++) {
 871                 hwc = &cpuc->event_list[i]->hw;
 872                 c = cpuc->event_constraint[i];
 873
 874                 /* never assigned */
 875                 if (hwc->idx == -1)
 876                         break;
 877
 878                 /* constraint still honored */
 879                 if (!test_bit(hwc->idx, c->idxmsk))
 880                         break;
 881
 882                 /* not already used */
 883                 if (test_bit(hwc->idx, used_mask))
 884                         break;
 885
 886                 __set_bit(hwc->idx, used_mask);
 887                 if (assign)
 888                         assign[i] = hwc->idx;
 889         }
 890
 891         /* slow path */
 892         if (i != n) {
 893                 int gpmax = x86_pmu.num_counters;
 894
 895                 /*
 896                  * Do not allow scheduling of more than half the available
 897                  * generic counters.
 898                  *
 899                  * This helps avoid counter starvation of sibling thread by
 900                  * ensuring at most half the counters cannot be in exclusive
 901                  * mode. There is no designated counters for the limits. Any
 902                  * N/2 counters can be used. This helps with events with
 903                  * specific counter constraints.
 904                  */
 905                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 906                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 907                         gpmax /= 2;
 908
 909                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 910                                              wmax, gpmax, assign);
 911         }
 912
 913         /*
 914          * In case of success (unsched = 0), mark events as committed,
 915          * so we do not put_constraint() in case new events are added
 916          * and fail to be scheduled
 917          *
 918          * We invoke the lower level commit callback to lock the resource
 919          *
 920          * We do not need to do all of this in case we are called to
 921          * validate an event group (assign == NULL)
 922          */
 923         if (!unsched && assign) {
 924                 for (i = 0; i < n; i++) {
 925                         e = cpuc->event_list[i];
 926                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 927                         if (x86_pmu.commit_scheduling)
 928                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 929                 }
 930         } else {
 931                 for (i = 0; i < n; i++) {
 932                         e = cpuc->event_list[i];
 933                         /*
 934                          * do not put_constraint() on comitted events,
 935                          * because they are good to go
 936                          */
 937                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 938                                 continue;
 939
 940                         /*
 941                          * release events that failed scheduling
 942                          */
 943                         if (x86_pmu.put_event_constraints)
 944                                 x86_pmu.put_event_constraints(cpuc, e);
 945                 }
 946         }
 947
 948         if (x86_pmu.stop_scheduling)
 949                 x86_pmu.stop_scheduling(cpuc);
 950
 951         return unsched ? -EINVAL : 0;
 952 }
 953
 954 /*
 955  * dogrp: true if must collect siblings events (group)
 956  * returns total number of events and error code
 957  */
 958 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 959 {
 960         struct perf_event *event;
 961         int n, max_count;
 962
 963         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 964
 965         /* current number of events already accepted */
 966         n = cpuc->n_events;
 967
 968         if (is_x86_event(leader)) {
 969                 if (n >= max_count)
 970                         return -EINVAL;
 971                 cpuc->event_list[n] = leader;
 972                 n++;
 973         }
 974         if (!dogrp)
 975                 return n;
 976
 977         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 978                 if (!is_x86_event(event) ||
 979                     event->state <= PERF_EVENT_STATE_OFF)
 980                         continue;
 981
 982                 if (n >= max_count)
 983                         return -EINVAL;
 984
 985                 cpuc->event_list[n] = event;
 986                 n++;
 987         }
 988         return n;
 989 }
 990
 991 static inline void x86_assign_hw_event(struct perf_event *event,
 992                                 struct cpu_hw_events *cpuc, int i)
 993 {
 994         struct hw_perf_event *hwc = &event->hw;
 995
 996         hwc->idx = cpuc->assign[i];
 997         hwc->last_cpu = smp_processor_id();
 998         hwc->last_tag = ++cpuc->tags[i];
 999
1000         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
1001                 hwc->config_base = 0;
1002                 hwc->event_base = 0;
1003         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1004                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1005                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1006                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1007         } else {
1008                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1009                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
1010                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1011         }
1012 }
1013
1014 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1015                                         struct cpu_hw_events *cpuc,
1016                                         int i)
1017 {
1018         return hwc->idx == cpuc->assign[i] &&
1019                 hwc->last_cpu == smp_processor_id() &&
1020                 hwc->last_tag == cpuc->tags[i];
1021 }
1022
1023 static void x86_pmu_start(struct perf_event *event, int flags);
1024
1025 static void x86_pmu_enable(struct pmu *pmu)
1026 {
1027         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1028         struct perf_event *event;
1029         struct hw_perf_event *hwc;
1030         int i, added = cpuc->n_added;
1031
1032         if (!x86_pmu_initialized())
1033                 return;
1034
1035         if (cpuc->enabled)
1036                 return;
1037
1038         if (cpuc->n_added) {
1039                 int n_running = cpuc->n_events - cpuc->n_added;
1040                 /*
1041                  * apply assignment obtained either from
1042                  * hw_perf_group_sched_in() or x86_pmu_enable()
1043                  *
1044                  * step1: save events moving to new counters
1045                  */
1046                 for (i = 0; i < n_running; i++) {
1047                         event = cpuc->event_list[i];
1048                         hwc = &event->hw;
1049
1050                         /*
1051                          * we can avoid reprogramming counter if:
1052                          * - assigned same counter as last time
1053                          * - running on same CPU as last time
1054                          * - no other event has used the counter since
1055                          */
1056                         if (hwc->idx == -1 ||
1057                             match_prev_assignment(hwc, cpuc, i))
1058                                 continue;
1059
1060                         /*
1061                          * Ensure we don't accidentally enable a stopped
1062                          * counter simply because we rescheduled.
1063                          */
1064                         if (hwc->state & PERF_HES_STOPPED)
1065                                 hwc->state |= PERF_HES_ARCH;
1066
1067                         x86_pmu_stop(event, PERF_EF_UPDATE);
1068                 }
1069
1070                 /*
1071                  * step2: reprogram moved events into new counters
1072                  */
1073                 for (i = 0; i < cpuc->n_events; i++) {
1074                         event = cpuc->event_list[i];
1075                         hwc = &event->hw;
1076
1077                         if (!match_prev_assignment(hwc, cpuc, i))
1078                                 x86_assign_hw_event(event, cpuc, i);
1079                         else if (i < n_running)
1080                                 continue;
1081
1082                         if (hwc->state & PERF_HES_ARCH)
1083                                 continue;
1084
1085                         x86_pmu_start(event, PERF_EF_RELOAD);
1086                 }
1087                 cpuc->n_added = 0;
1088                 perf_events_lapic_init();
1089         }
1090
1091         cpuc->enabled = 1;
1092         barrier();
1093
1094         x86_pmu.enable_all(added);
1095 }
1096
1097 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1098
1099 /*
1100  * Set the next IRQ period, based on the hwc->period_left value.
1101  * To be called with the event disabled in hw:
1102  */
1103 int x86_perf_event_set_period(struct perf_event *event)
1104 {
1105         struct hw_perf_event *hwc = &event->hw;
1106         s64 left = local64_read(&hwc->period_left);
1107         s64 period = hwc->sample_period;
1108         int ret = 0, idx = hwc->idx;
1109
1110         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1111                 return 0;
1112
1113         /*
1114          * If we are way outside a reasonable range then just skip forward:
1115          */
1116         if (unlikely(left <= -period)) {
1117                 left = period;
1118                 local64_set(&hwc->period_left, left);
1119                 hwc->last_period = period;
1120                 ret = 1;
1121         }
1122
1123         if (unlikely(left <= 0)) {
1124                 left += period;
1125                 local64_set(&hwc->period_left, left);
1126                 hwc->last_period = period;
1127                 ret = 1;
1128         }
1129         /*
1130          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1131          */
1132         if (unlikely(left < 2))
1133                 left = 2;
1134
1135         if (left > x86_pmu.max_period)
1136                 left = x86_pmu.max_period;
1137
1138         if (x86_pmu.limit_period)
1139                 left = x86_pmu.limit_period(event, left);
1140
1141         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1142
1143         /*
1144          * The hw event starts counting from this event offset,
1145          * mark it to be able to extra future deltas:
1146          */
1147         local64_set(&hwc->prev_count, (u64)-left);
1148
1149         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1150
1151         /*
1152          * Due to erratum on certan cpu we need
1153          * a second write to be sure the register
1154          * is updated properly
1155          */
1156         if (x86_pmu.perfctr_second_write) {
1157                 wrmsrl(hwc->event_base,
1158                         (u64)(-left) & x86_pmu.cntval_mask);
1159         }
1160
1161         perf_event_update_userpage(event);
1162
1163         return ret;
1164 }
1165
1166 void x86_pmu_enable_event(struct perf_event *event)
1167 {
1168         if (__this_cpu_read(cpu_hw_events.enabled))
1169                 __x86_pmu_enable_event(&event->hw,
1170                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1171 }
1172
1173 /*
1174  * Add a single event to the PMU.
1175  *
1176  * The event is added to the group of enabled events
1177  * but only if it can be scehduled with existing events.
1178  */
1179 static int x86_pmu_add(struct perf_event *event, int flags)
1180 {
1181         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1182         struct hw_perf_event *hwc;
1183         int assign[X86_PMC_IDX_MAX];
1184         int n, n0, ret;
1185
1186         hwc = &event->hw;
1187
1188         n0 = cpuc->n_events;
1189         ret = n = collect_events(cpuc, event, false);
1190         if (ret < 0)
1191                 goto out;
1192
1193         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1194         if (!(flags & PERF_EF_START))
1195                 hwc->state |= PERF_HES_ARCH;
1196
1197         /*
1198          * If group events scheduling transaction was started,
1199          * skip the schedulability test here, it will be performed
1200          * at commit time (->commit_txn) as a whole.
1201          *
1202          * If commit fails, we'll call ->del() on all events
1203          * for which ->add() was called.
1204          */
1205         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1206                 goto done_collect;
1207
1208         ret = x86_pmu.schedule_events(cpuc, n, assign);
1209         if (ret)
1210                 goto out;
1211         /*
1212          * copy new assignment, now we know it is possible
1213          * will be used by hw_perf_enable()
1214          */
1215         memcpy(cpuc->assign, assign, n*sizeof(int));
1216
1217 done_collect:
1218         /*
1219          * Commit the collect_events() state. See x86_pmu_del() and
1220          * x86_pmu_*_txn().
1221          */
1222         cpuc->n_events = n;
1223         cpuc->n_added += n - n0;
1224         cpuc->n_txn += n - n0;
1225
1226         if (x86_pmu.add) {
1227                 /*
1228                  * This is before x86_pmu_enable() will call x86_pmu_start(),
1229                  * so we enable LBRs before an event needs them etc..
1230                  */
1231                 x86_pmu.add(event);
1232         }
1233
1234         ret = 0;
1235 out:
1236         return ret;
1237 }
1238
1239 static void x86_pmu_start(struct perf_event *event, int flags)
1240 {
1241         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1242         int idx = event->hw.idx;
1243
1244         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1245                 return;
1246
1247         if (WARN_ON_ONCE(idx == -1))
1248                 return;
1249
1250         if (flags & PERF_EF_RELOAD) {
1251                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1252                 x86_perf_event_set_period(event);
1253         }
1254
1255         event->hw.state = 0;
1256
1257         cpuc->events[idx] = event;
1258         __set_bit(idx, cpuc->active_mask);
1259         __set_bit(idx, cpuc->running);
1260         x86_pmu.enable(event);
1261         perf_event_update_userpage(event);
1262 }
1263
1264 void perf_event_print_debug(void)
1265 {
1266         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1267         u64 pebs, debugctl;
1268         struct cpu_hw_events *cpuc;
1269         unsigned long flags;
1270         int cpu, idx;
1271
1272         if (!x86_pmu.num_counters)
1273                 return;
1274
1275         local_irq_save(flags);
1276
1277         cpu = smp_processor_id();
1278         cpuc = &per_cpu(cpu_hw_events, cpu);
1279
1280         if (x86_pmu.version >= 2) {
1281                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1282                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1283                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1284                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1285
1286                 pr_info("\n");
1287                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1288                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1289                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1290                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1291                 if (x86_pmu.pebs_constraints) {
1292                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1293                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1294                 }
1295                 if (x86_pmu.lbr_nr) {
1296                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1297                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1298                 }
1299         }
1300         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1301
1302         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1303                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1304                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1305
1306                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1307
1308                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1309                         cpu, idx, pmc_ctrl);
1310                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1311                         cpu, idx, pmc_count);
1312                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1313                         cpu, idx, prev_left);
1314         }
1315         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1316                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1317
1318                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1319                         cpu, idx, pmc_count);
1320         }
1321         local_irq_restore(flags);
1322 }
1323
1324 void x86_pmu_stop(struct perf_event *event, int flags)
1325 {
1326         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1327         struct hw_perf_event *hwc = &event->hw;
1328
1329         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1330                 x86_pmu.disable(event);
1331                 cpuc->events[hwc->idx] = NULL;
1332                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1333                 hwc->state |= PERF_HES_STOPPED;
1334         }
1335
1336         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1337                 /*
1338                  * Drain the remaining delta count out of a event
1339                  * that we are disabling:
1340                  */
1341                 x86_perf_event_update(event);
1342                 hwc->state |= PERF_HES_UPTODATE;
1343         }
1344 }
1345
1346 static void x86_pmu_del(struct perf_event *event, int flags)
1347 {
1348         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1349         int i;
1350
1351         /*
1352          * event is descheduled
1353          */
1354         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1355
1356         /*
1357          * If we're called during a txn, we only need to undo x86_pmu.add.
1358          * The events never got scheduled and ->cancel_txn will truncate
1359          * the event_list.
1360          *
1361          * XXX assumes any ->del() called during a TXN will only be on
1362          * an event added during that same TXN.
1363          */
1364         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1365                 goto do_del;
1366
1367         /*
1368          * Not a TXN, therefore cleanup properly.
1369          */
1370         x86_pmu_stop(event, PERF_EF_UPDATE);
1371
1372         for (i = 0; i < cpuc->n_events; i++) {
1373                 if (event == cpuc->event_list[i])
1374                         break;
1375         }
1376
1377         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1378                 return;
1379
1380         /* If we have a newly added event; make sure to decrease n_added. */
1381         if (i >= cpuc->n_events - cpuc->n_added)
1382                 --cpuc->n_added;
1383
1384         if (x86_pmu.put_event_constraints)
1385                 x86_pmu.put_event_constraints(cpuc, event);
1386
1387         /* Delete the array entry. */
1388         while (++i < cpuc->n_events) {
1389                 cpuc->event_list[i-1] = cpuc->event_list[i];
1390                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1391         }
1392         --cpuc->n_events;
1393
1394         perf_event_update_userpage(event);
1395
1396 do_del:
1397         if (x86_pmu.del) {
1398                 /*
1399                  * This is after x86_pmu_stop(); so we disable LBRs after any
1400                  * event can need them etc..
1401                  */
1402                 x86_pmu.del(event);
1403         }
1404 }
1405
1406 int x86_pmu_handle_irq(struct pt_regs *regs)
1407 {
1408         struct perf_sample_data data;
1409         struct cpu_hw_events *cpuc;
1410         struct perf_event *event;
1411         int idx, handled = 0;
1412         u64 val;
1413
1414         cpuc = this_cpu_ptr(&cpu_hw_events);
1415
1416         /*
1417          * Some chipsets need to unmask the LVTPC in a particular spot
1418          * inside the nmi handler.  As a result, the unmasking was pushed
1419          * into all the nmi handlers.
1420          *
1421          * This generic handler doesn't seem to have any issues where the
1422          * unmasking occurs so it was left at the top.
1423          */
1424         apic_write(APIC_LVTPC, APIC_DM_NMI);
1425
1426         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1427                 if (!test_bit(idx, cpuc->active_mask)) {
1428                         /*
1429                          * Though we deactivated the counter some cpus
1430                          * might still deliver spurious interrupts still
1431                          * in flight. Catch them:
1432                          */
1433                         if (__test_and_clear_bit(idx, cpuc->running))
1434                                 handled++;
1435                         continue;
1436                 }
1437
1438                 event = cpuc->events[idx];
1439
1440                 val = x86_perf_event_update(event);
1441                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1442                         continue;
1443
1444                 /*
1445                  * event overflow
1446                  */
1447                 handled++;
1448                 perf_sample_data_init(&data, 0, event->hw.last_period);
1449
1450                 if (!x86_perf_event_set_period(event))
1451                         continue;
1452
1453                 if (perf_event_overflow(event, &data, regs))
1454                         x86_pmu_stop(event, 0);
1455         }
1456
1457         if (handled)
1458                 inc_irq_stat(apic_perf_irqs);
1459
1460         return handled;
1461 }
1462
1463 void perf_events_lapic_init(void)
1464 {
1465         if (!x86_pmu.apic || !x86_pmu_initialized())
1466                 return;
1467
1468         /*
1469          * Always use NMI for PMU
1470          */
1471         apic_write(APIC_LVTPC, APIC_DM_NMI);
1472 }
1473
1474 static int
1475 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1476 {
1477         u64 start_clock;
1478         u64 finish_clock;
1479         int ret;
1480
1481         /*
1482          * All PMUs/events that share this PMI handler should make sure to
1483          * increment active_events for their events.
1484          */
1485         if (!atomic_read(&active_events))
1486                 return NMI_DONE;
1487
1488         start_clock = sched_clock();
1489         ret = x86_pmu.handle_irq(regs);
1490         finish_clock = sched_clock();
1491
1492         perf_sample_event_took(finish_clock - start_clock);
1493
1494         return ret;
1495 }
1496 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1497
1498 struct event_constraint emptyconstraint;
1499 struct event_constraint unconstrained;
1500
1501 static int x86_pmu_prepare_cpu(unsigned int cpu)
1502 {
1503         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1504         int i;
1505
1506         for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1507                 cpuc->kfree_on_online[i] = NULL;
1508         if (x86_pmu.cpu_prepare)
1509                 return x86_pmu.cpu_prepare(cpu);
1510         return 0;
1511 }
1512
1513 static int x86_pmu_dead_cpu(unsigned int cpu)
1514 {
1515         if (x86_pmu.cpu_dead)
1516                 x86_pmu.cpu_dead(cpu);
1517         return 0;
1518 }
1519
1520 static int x86_pmu_online_cpu(unsigned int cpu)
1521 {
1522         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1523         int i;
1524
1525         for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1526                 kfree(cpuc->kfree_on_online[i]);
1527                 cpuc->kfree_on_online[i] = NULL;
1528         }
1529         return 0;
1530 }
1531
1532 static int x86_pmu_starting_cpu(unsigned int cpu)
1533 {
1534         if (x86_pmu.cpu_starting)
1535                 x86_pmu.cpu_starting(cpu);
1536         return 0;
1537 }
1538
1539 static int x86_pmu_dying_cpu(unsigned int cpu)
1540 {
1541         if (x86_pmu.cpu_dying)
1542                 x86_pmu.cpu_dying(cpu);
1543         return 0;
1544 }
1545
1546 static void __init pmu_check_apic(void)
1547 {
1548         if (boot_cpu_has(X86_FEATURE_APIC))
1549                 return;
1550
1551         x86_pmu.apic = 0;
1552         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1553         pr_info("no hardware sampling interrupt available.\n");
1554
1555         /*
1556          * If we have a PMU initialized but no APIC
1557          * interrupts, we cannot sample hardware
1558          * events (user-space has to fall back and
1559          * sample via a hrtimer based software event):
1560          */
1561         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1562
1563 }
1564
1565 static struct attribute_group x86_pmu_format_group = {
1566         .name = "format",
1567         .attrs = NULL,
1568 };
1569
1570 /*
1571  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1572  * out of events_attr attributes.
1573  */
1574 static void __init filter_events(struct attribute **attrs)
1575 {
1576         struct device_attribute *d;
1577         struct perf_pmu_events_attr *pmu_attr;
1578         int offset = 0;
1579         int i, j;
1580
1581         for (i = 0; attrs[i]; i++) {
1582                 d = (struct device_attribute *)attrs[i];
1583                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1584                 /* str trumps id */
1585                 if (pmu_attr->event_str)
1586                         continue;
1587                 if (x86_pmu.event_map(i + offset))
1588                         continue;
1589
1590                 for (j = i; attrs[j]; j++)
1591                         attrs[j] = attrs[j + 1];
1592
1593                 /* Check the shifted attr. */
1594                 i--;
1595
1596                 /*
1597                  * event_map() is index based, the attrs array is organized
1598                  * by increasing event index. If we shift the events, then
1599                  * we need to compensate for the event_map(), otherwise
1600                  * we are looking up the wrong event in the map
1601                  */
1602                 offset++;
1603         }
1604 }
1605
1606 /* Merge two pointer arrays */
1607 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1608 {
1609         struct attribute **new;
1610         int j, i;
1611
1612         for (j = 0; a[j]; j++)
1613                 ;
1614         for (i = 0; b[i]; i++)
1615                 j++;
1616         j++;
1617
1618         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1619         if (!new)
1620                 return NULL;
1621
1622         j = 0;
1623         for (i = 0; a[i]; i++)
1624                 new[j++] = a[i];
1625         for (i = 0; b[i]; i++)
1626                 new[j++] = b[i];
1627         new[j] = NULL;
1628
1629         return new;
1630 }
1631
1632 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1633 {
1634         struct perf_pmu_events_attr *pmu_attr = \
1635                 container_of(attr, struct perf_pmu_events_attr, attr);
1636         u64 config = x86_pmu.event_map(pmu_attr->id);
1637
1638         /* string trumps id */
1639         if (pmu_attr->event_str)
1640                 return sprintf(page, "%s", pmu_attr->event_str);
1641
1642         return x86_pmu.events_sysfs_show(page, config);
1643 }
1644 EXPORT_SYMBOL_GPL(events_sysfs_show);
1645
1646 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1647                           char *page)
1648 {
1649         struct perf_pmu_events_ht_attr *pmu_attr =
1650                 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1651
1652         /*
1653          * Report conditional events depending on Hyper-Threading.
1654          *
1655          * This is overly conservative as usually the HT special
1656          * handling is not needed if the other CPU thread is idle.
1657          *
1658          * Note this does not (and cannot) handle the case when thread
1659          * siblings are invisible, for example with virtualization
1660          * if they are owned by some other guest.  The user tool
1661          * has to re-read when a thread sibling gets onlined later.
1662          */
1663         return sprintf(page, "%s",
1664                         topology_max_smt_threads() > 1 ?
1665                         pmu_attr->event_str_ht :
1666                         pmu_attr->event_str_noht);
1667 }
1668
1669 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1670 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1671 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1672 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1673 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1674 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1675 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1676 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1677 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1678 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1679
1680 static struct attribute *empty_attrs;
1681
1682 static struct attribute *events_attr[] = {
1683         EVENT_PTR(CPU_CYCLES),
1684         EVENT_PTR(INSTRUCTIONS),
1685         EVENT_PTR(CACHE_REFERENCES),
1686         EVENT_PTR(CACHE_MISSES),
1687         EVENT_PTR(BRANCH_INSTRUCTIONS),
1688         EVENT_PTR(BRANCH_MISSES),
1689         EVENT_PTR(BUS_CYCLES),
1690         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1691         EVENT_PTR(STALLED_CYCLES_BACKEND),
1692         EVENT_PTR(REF_CPU_CYCLES),
1693         NULL,
1694 };
1695
1696 static struct attribute_group x86_pmu_events_group = {
1697         .name = "events",
1698         .attrs = events_attr,
1699 };
1700
1701 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1702 {
1703         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1704         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1705         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1706         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1707         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1708         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1709         ssize_t ret;
1710
1711         /*
1712         * We have whole page size to spend and just little data
1713         * to write, so we can safely use sprintf.
1714         */
1715         ret = sprintf(page, "event=0x%02llx", event);
1716
1717         if (umask)
1718                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1719
1720         if (edge)
1721                 ret += sprintf(page + ret, ",edge");
1722
1723         if (pc)
1724                 ret += sprintf(page + ret, ",pc");
1725
1726         if (any)
1727                 ret += sprintf(page + ret, ",any");
1728
1729         if (inv)
1730                 ret += sprintf(page + ret, ",inv");
1731
1732         if (cmask)
1733                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1734
1735         ret += sprintf(page + ret, "\n");
1736
1737         return ret;
1738 }
1739
1740 static int __init init_hw_perf_events(void)
1741 {
1742         struct x86_pmu_quirk *quirk;
1743         int err;
1744
1745         pr_info("Performance Events: ");
1746
1747         switch (boot_cpu_data.x86_vendor) {
1748         case X86_VENDOR_INTEL:
1749                 err = intel_pmu_init();
1750                 break;
1751         case X86_VENDOR_AMD:
1752                 err = amd_pmu_init();
1753                 break;
1754         default:
1755                 err = -ENOTSUPP;
1756         }
1757         if (err != 0) {
1758                 pr_cont("no PMU driver, software events only.\n");
1759                 return 0;
1760         }
1761
1762         pmu_check_apic();
1763
1764         /* sanity check that the hardware exists or is emulated */
1765         if (!check_hw_exists())
1766                 return 0;
1767
1768         pr_cont("%s PMU driver.\n", x86_pmu.name);
1769
1770         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1771
1772         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1773                 quirk->func();
1774
1775         if (!x86_pmu.intel_ctrl)
1776                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1777
1778         perf_events_lapic_init();
1779         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1780
1781         unconstrained = (struct event_constraint)
1782                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1783                                    0, x86_pmu.num_counters, 0, 0);
1784
1785         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1786
1787         if (x86_pmu.event_attrs)
1788                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1789
1790         if (!x86_pmu.events_sysfs_show)
1791                 x86_pmu_events_group.attrs = &empty_attrs;
1792         else
1793                 filter_events(x86_pmu_events_group.attrs);
1794
1795         if (x86_pmu.cpu_events) {
1796                 struct attribute **tmp;
1797
1798                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1799                 if (!WARN_ON(!tmp))
1800                         x86_pmu_events_group.attrs = tmp;
1801         }
1802
1803         pr_info("... version:                %d\n",     x86_pmu.version);
1804         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1805         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1806         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1807         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1808         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1809         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1810
1811         /*
1812          * Install callbacks. Core will call them for each online
1813          * cpu.
1814          */
1815         err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "PERF_X86_PREPARE",
1816                                 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1817         if (err)
1818                 return err;
1819
1820         err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1821                                 "AP_PERF_X86_STARTING", x86_pmu_starting_cpu,
1822                                 x86_pmu_dying_cpu);
1823         if (err)
1824                 goto out;
1825
1826         err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "AP_PERF_X86_ONLINE",
1827                                 x86_pmu_online_cpu, NULL);
1828         if (err)
1829                 goto out1;
1830
1831         err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1832         if (err)
1833                 goto out2;
1834
1835         return 0;
1836
1837 out2:
1838         cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1839 out1:
1840         cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1841 out:
1842         cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1843         return err;
1844 }
1845 early_initcall(init_hw_perf_events);
1846
1847 static inline void x86_pmu_read(struct perf_event *event)
1848 {
1849         x86_perf_event_update(event);
1850 }
1851
1852 /*
1853  * Start group events scheduling transaction
1854  * Set the flag to make pmu::enable() not perform the
1855  * schedulability test, it will be performed at commit time
1856  *
1857  * We only support PERF_PMU_TXN_ADD transactions. Save the
1858  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1859  * transactions.
1860  */
1861 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1862 {
1863         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1864
1865         WARN_ON_ONCE(cpuc->txn_flags);          /* txn already in flight */
1866
1867         cpuc->txn_flags = txn_flags;
1868         if (txn_flags & ~PERF_PMU_TXN_ADD)
1869                 return;
1870
1871         perf_pmu_disable(pmu);
1872         __this_cpu_write(cpu_hw_events.n_txn, 0);
1873 }
1874
1875 /*
1876  * Stop group events scheduling transaction
1877  * Clear the flag and pmu::enable() will perform the
1878  * schedulability test.
1879  */
1880 static void x86_pmu_cancel_txn(struct pmu *pmu)
1881 {
1882         unsigned int txn_flags;
1883         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1884
1885         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1886
1887         txn_flags = cpuc->txn_flags;
1888         cpuc->txn_flags = 0;
1889         if (txn_flags & ~PERF_PMU_TXN_ADD)
1890                 return;
1891
1892         /*
1893          * Truncate collected array by the number of events added in this
1894          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1895          */
1896         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1897         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1898         perf_pmu_enable(pmu);
1899 }
1900
1901 /*
1902  * Commit group events scheduling transaction
1903  * Perform the group schedulability test as a whole
1904  * Return 0 if success
1905  *
1906  * Does not cancel the transaction on failure; expects the caller to do this.
1907  */
1908 static int x86_pmu_commit_txn(struct pmu *pmu)
1909 {
1910         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1911         int assign[X86_PMC_IDX_MAX];
1912         int n, ret;
1913
1914         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1915
1916         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1917                 cpuc->txn_flags = 0;
1918                 return 0;
1919         }
1920
1921         n = cpuc->n_events;
1922
1923         if (!x86_pmu_initialized())
1924                 return -EAGAIN;
1925
1926         ret = x86_pmu.schedule_events(cpuc, n, assign);
1927         if (ret)
1928                 return ret;
1929
1930         /*
1931          * copy new assignment, now we know it is possible
1932          * will be used by hw_perf_enable()
1933          */
1934         memcpy(cpuc->assign, assign, n*sizeof(int));
1935
1936         cpuc->txn_flags = 0;
1937         perf_pmu_enable(pmu);
1938         return 0;
1939 }
1940 /*
1941  * a fake_cpuc is used to validate event groups. Due to
1942  * the extra reg logic, we need to also allocate a fake
1943  * per_core and per_cpu structure. Otherwise, group events
1944  * using extra reg may conflict without the kernel being
1945  * able to catch this when the last event gets added to
1946  * the group.
1947  */
1948 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1949 {
1950         intel_cpuc_finish(cpuc);
1951         kfree(cpuc);
1952 }
1953
1954 static struct cpu_hw_events *allocate_fake_cpuc(void)
1955 {
1956         struct cpu_hw_events *cpuc;
1957         int cpu = raw_smp_processor_id();
1958
1959         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1960         if (!cpuc)
1961                 return ERR_PTR(-ENOMEM);
1962         cpuc->is_fake = 1;
1963
1964         if (intel_cpuc_prepare(cpuc, cpu))
1965                 goto error;
1966
1967         return cpuc;
1968 error:
1969         free_fake_cpuc(cpuc);
1970         return ERR_PTR(-ENOMEM);
1971 }
1972
1973 /*
1974  * validate that we can schedule this event
1975  */
1976 static int validate_event(struct perf_event *event)
1977 {
1978         struct cpu_hw_events *fake_cpuc;
1979         struct event_constraint *c;
1980         int ret = 0;
1981
1982         fake_cpuc = allocate_fake_cpuc();
1983         if (IS_ERR(fake_cpuc))
1984                 return PTR_ERR(fake_cpuc);
1985
1986         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1987
1988         if (!c || !c->weight)
1989                 ret = -EINVAL;
1990
1991         if (x86_pmu.put_event_constraints)
1992                 x86_pmu.put_event_constraints(fake_cpuc, event);
1993
1994         free_fake_cpuc(fake_cpuc);
1995
1996         return ret;
1997 }
1998
1999 /*
2000  * validate a single event group
2001  *
2002  * validation include:
2003  *      - check events are compatible which each other
2004  *      - events do not compete for the same counter
2005  *      - number of events <= number of counters
2006  *
2007  * validation ensures the group can be loaded onto the
2008  * PMU if it was the only group available.
2009  */
2010 static int validate_group(struct perf_event *event)
2011 {
2012         struct perf_event *leader = event->group_leader;
2013         struct cpu_hw_events *fake_cpuc;
2014         int ret = -EINVAL, n;
2015
2016         fake_cpuc = allocate_fake_cpuc();
2017         if (IS_ERR(fake_cpuc))
2018                 return PTR_ERR(fake_cpuc);
2019         /*
2020          * the event is not yet connected with its
2021          * siblings therefore we must first collect
2022          * existing siblings, then add the new event
2023          * before we can simulate the scheduling
2024          */
2025         n = collect_events(fake_cpuc, leader, true);
2026         if (n < 0)
2027                 goto out;
2028
2029         fake_cpuc->n_events = n;
2030         n = collect_events(fake_cpuc, event, false);
2031         if (n < 0)
2032                 goto out;
2033
2034         fake_cpuc->n_events = n;
2035
2036         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2037
2038 out:
2039         free_fake_cpuc(fake_cpuc);
2040         return ret;
2041 }
2042
2043 static int x86_pmu_event_init(struct perf_event *event)
2044 {
2045         struct pmu *tmp;
2046         int err;
2047
2048         switch (event->attr.type) {
2049         case PERF_TYPE_RAW:
2050         case PERF_TYPE_HARDWARE:
2051         case PERF_TYPE_HW_CACHE:
2052                 break;
2053
2054         default:
2055                 return -ENOENT;
2056         }
2057
2058         err = __x86_pmu_event_init(event);
2059         if (!err) {
2060                 /*
2061                  * we temporarily connect event to its pmu
2062                  * such that validate_group() can classify
2063                  * it as an x86 event using is_x86_event()
2064                  */
2065                 tmp = event->pmu;
2066                 event->pmu = &pmu;
2067
2068                 if (event->group_leader != event)
2069                         err = validate_group(event);
2070                 else
2071                         err = validate_event(event);
2072
2073                 event->pmu = tmp;
2074         }
2075         if (err) {
2076                 if (event->destroy)
2077                         event->destroy(event);
2078                 event->destroy = NULL;
2079         }
2080
2081         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
2082                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2083
2084         return err;
2085 }
2086
2087 static void refresh_pce(void *ignored)
2088 {
2089         if (current->active_mm)
2090                 load_mm_cr4(current->active_mm);
2091 }
2092
2093 static void x86_pmu_event_mapped(struct perf_event *event)
2094 {
2095         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2096                 return;
2097
2098         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
2099                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2100 }
2101
2102 static void x86_pmu_event_unmapped(struct perf_event *event)
2103 {
2104         if (!current->mm)
2105                 return;
2106
2107         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2108                 return;
2109
2110         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
2111                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2112 }
2113
2114 static int x86_pmu_event_idx(struct perf_event *event)
2115 {
2116         int idx = event->hw.idx;
2117
2118         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2119                 return 0;
2120
2121         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2122                 idx -= INTEL_PMC_IDX_FIXED;
2123                 idx |= 1 << 30;
2124         }
2125
2126         return idx + 1;
2127 }
2128
2129 static ssize_t get_attr_rdpmc(struct device *cdev,
2130                               struct device_attribute *attr,
2131                               char *buf)
2132 {
2133         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2134 }
2135
2136 static ssize_t set_attr_rdpmc(struct device *cdev,
2137                               struct device_attribute *attr,
2138                               const char *buf, size_t count)
2139 {
2140         unsigned long val;
2141         ssize_t ret;
2142
2143         ret = kstrtoul(buf, 0, &val);
2144         if (ret)
2145                 return ret;
2146
2147         if (val > 2)
2148                 return -EINVAL;
2149
2150         if (x86_pmu.attr_rdpmc_broken)
2151                 return -ENOTSUPP;
2152
2153         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2154                 /*
2155                  * Changing into or out of always available, aka
2156                  * perf-event-bypassing mode.  This path is extremely slow,
2157                  * but only root can trigger it, so it's okay.
2158                  */
2159                 if (val == 2)
2160                         static_key_slow_inc(&rdpmc_always_available);
2161                 else
2162                         static_key_slow_dec(&rdpmc_always_available);
2163                 on_each_cpu(refresh_pce, NULL, 1);
2164         }
2165
2166         x86_pmu.attr_rdpmc = val;
2167
2168         return count;
2169 }
2170
2171 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2172
2173 static struct attribute *x86_pmu_attrs[] = {
2174         &dev_attr_rdpmc.attr,
2175         NULL,
2176 };
2177
2178 static struct attribute_group x86_pmu_attr_group = {
2179         .attrs = x86_pmu_attrs,
2180 };
2181
2182 static const struct attribute_group *x86_pmu_attr_groups[] = {
2183         &x86_pmu_attr_group,
2184         &x86_pmu_format_group,
2185         &x86_pmu_events_group,
2186         NULL,
2187 };
2188
2189 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2190 {
2191         if (x86_pmu.sched_task)
2192                 x86_pmu.sched_task(ctx, sched_in);
2193 }
2194
2195 void perf_check_microcode(void)
2196 {
2197         if (x86_pmu.check_microcode)
2198                 x86_pmu.check_microcode();
2199 }
2200 EXPORT_SYMBOL_GPL(perf_check_microcode);
2201
2202 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2203 {
2204         if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2205                 return -EINVAL;
2206
2207         if (value && x86_pmu.limit_period) {
2208                 if (x86_pmu.limit_period(event, value) > value)
2209                         return -EINVAL;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static struct pmu pmu = {
2216         .pmu_enable             = x86_pmu_enable,
2217         .pmu_disable            = x86_pmu_disable,
2218
2219         .attr_groups            = x86_pmu_attr_groups,
2220
2221         .event_init             = x86_pmu_event_init,
2222
2223         .event_mapped           = x86_pmu_event_mapped,
2224         .event_unmapped         = x86_pmu_event_unmapped,
2225
2226         .add                    = x86_pmu_add,
2227         .del                    = x86_pmu_del,
2228         .start                  = x86_pmu_start,
2229         .stop                   = x86_pmu_stop,
2230         .read                   = x86_pmu_read,
2231
2232         .start_txn              = x86_pmu_start_txn,
2233         .cancel_txn             = x86_pmu_cancel_txn,
2234         .commit_txn             = x86_pmu_commit_txn,
2235
2236         .event_idx              = x86_pmu_event_idx,
2237         .sched_task             = x86_pmu_sched_task,
2238         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2239         .check_period           = x86_pmu_check_period,
2240 };
2241
2242 void arch_perf_update_userpage(struct perf_event *event,
2243                                struct perf_event_mmap_page *userpg, u64 now)
2244 {
2245         struct cyc2ns_data *data;
2246
2247         userpg->cap_user_time = 0;
2248         userpg->cap_user_time_zero = 0;
2249         userpg->cap_user_rdpmc =
2250                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2251         userpg->pmc_width = x86_pmu.cntval_bits;
2252
2253         if (!sched_clock_stable())
2254                 return;
2255
2256         data = cyc2ns_read_begin();
2257
2258         /*
2259          * Internal timekeeping for enabled/running/stopped times
2260          * is always in the local_clock domain.
2261          */
2262         userpg->cap_user_time = 1;
2263         userpg->time_mult = data->cyc2ns_mul;
2264         userpg->time_shift = data->cyc2ns_shift;
2265         userpg->time_offset = data->cyc2ns_offset - now;
2266
2267         /*
2268          * cap_user_time_zero doesn't make sense when we're using a different
2269          * time base for the records.
2270          */
2271         if (!event->attr.use_clockid) {
2272                 userpg->cap_user_time_zero = 1;
2273                 userpg->time_zero = data->cyc2ns_offset;
2274         }
2275
2276         cyc2ns_read_end(data);
2277 }
2278
2279 void
2280 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2281 {
2282         struct unwind_state state;
2283         unsigned long addr;
2284
2285         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2286                 /* TODO: We don't support guest os callchain now */
2287                 return;
2288         }
2289
2290         if (perf_callchain_store(entry, regs->ip))
2291                 return;
2292
2293         for (unwind_start(&state, current, regs, NULL); !unwind_done(&state);
2294              unwind_next_frame(&state)) {
2295                 addr = unwind_get_return_address(&state);
2296                 if (!addr || perf_callchain_store(entry, addr))
2297                         return;
2298         }
2299 }
2300
2301 static inline int
2302 valid_user_frame(const void __user *fp, unsigned long size)
2303 {
2304         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2305 }
2306
2307 static unsigned long get_segment_base(unsigned int segment)
2308 {
2309         struct desc_struct *desc;
2310         int idx = segment >> 3;
2311
2312         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2313 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2314                 struct ldt_struct *ldt;
2315
2316                 if (idx > LDT_ENTRIES)
2317                         return 0;
2318
2319                 /* IRQs are off, so this synchronizes with smp_store_release */
2320                 ldt = lockless_dereference(current->active_mm->context.ldt);
2321                 if (!ldt || idx > ldt->size)
2322                         return 0;
2323
2324                 desc = &ldt->entries[idx];
2325 #else
2326                 return 0;
2327 #endif
2328         } else {
2329                 if (idx > GDT_ENTRIES)
2330                         return 0;
2331
2332                 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2333         }
2334
2335         return get_desc_base(desc);
2336 }
2337
2338 #ifdef CONFIG_IA32_EMULATION
2339
2340 #include <asm/compat.h>
2341
2342 static inline int
2343 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2344 {
2345         /* 32-bit process in 64-bit kernel. */
2346         unsigned long ss_base, cs_base;
2347         struct stack_frame_ia32 frame;
2348         const void __user *fp;
2349
2350         if (!test_thread_flag(TIF_IA32))
2351                 return 0;
2352
2353         cs_base = get_segment_base(regs->cs);
2354         ss_base = get_segment_base(regs->ss);
2355
2356         fp = compat_ptr(ss_base + regs->bp);
2357         pagefault_disable();
2358         while (entry->nr < entry->max_stack) {
2359                 unsigned long bytes;
2360                 frame.next_frame     = 0;
2361                 frame.return_address = 0;
2362
2363                 if (!valid_user_frame(fp, sizeof(frame)))
2364                         break;
2365
2366                 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2367                 if (bytes != 0)
2368                         break;
2369                 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2370                 if (bytes != 0)
2371                         break;
2372
2373                 perf_callchain_store(entry, cs_base + frame.return_address);
2374                 fp = compat_ptr(ss_base + frame.next_frame);
2375         }
2376         pagefault_enable();
2377         return 1;
2378 }
2379 #else
2380 static inline int
2381 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2382 {
2383     return 0;
2384 }
2385 #endif
2386
2387 void
2388 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2389 {
2390         struct stack_frame frame;
2391         const unsigned long __user *fp;
2392
2393         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2394                 /* TODO: We don't support guest os callchain now */
2395                 return;
2396         }
2397
2398         /*
2399          * We don't know what to do with VM86 stacks.. ignore them for now.
2400          */
2401         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2402                 return;
2403
2404         fp = (unsigned long __user *)regs->bp;
2405
2406         perf_callchain_store(entry, regs->ip);
2407
2408         if (!current->mm)
2409                 return;
2410
2411         if (perf_callchain_user32(regs, entry))
2412                 return;
2413
2414         pagefault_disable();
2415         while (entry->nr < entry->max_stack) {
2416                 unsigned long bytes;
2417
2418                 frame.next_frame             = NULL;
2419                 frame.return_address = 0;
2420
2421                 if (!valid_user_frame(fp, sizeof(frame)))
2422                         break;
2423
2424                 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2425                 if (bytes != 0)
2426                         break;
2427                 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2428                 if (bytes != 0)
2429                         break;
2430
2431                 perf_callchain_store(entry, frame.return_address);
2432                 fp = (void __user *)frame.next_frame;
2433         }
2434         pagefault_enable();
2435 }
2436
2437 /*
2438  * Deal with code segment offsets for the various execution modes:
2439  *
2440  *   VM86 - the good olde 16 bit days, where the linear address is
2441  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2442  *
2443  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2444  *          to figure out what the 32bit base address is.
2445  *
2446  *    X32 - has TIF_X32 set, but is running in x86_64
2447  *
2448  * X86_64 - CS,DS,SS,ES are all zero based.
2449  */
2450 static unsigned long code_segment_base(struct pt_regs *regs)
2451 {
2452         /*
2453          * For IA32 we look at the GDT/LDT segment base to convert the
2454          * effective IP to a linear address.
2455          */
2456
2457 #ifdef CONFIG_X86_32
2458         /*
2459          * If we are in VM86 mode, add the segment offset to convert to a
2460          * linear address.
2461          */
2462         if (regs->flags & X86_VM_MASK)
2463                 return 0x10 * regs->cs;
2464
2465         if (user_mode(regs) && regs->cs != __USER_CS)
2466                 return get_segment_base(regs->cs);
2467 #else
2468         if (user_mode(regs) && !user_64bit_mode(regs) &&
2469             regs->cs != __USER32_CS)
2470                 return get_segment_base(regs->cs);
2471 #endif
2472         return 0;
2473 }
2474
2475 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2476 {
2477         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2478                 return perf_guest_cbs->get_guest_ip();
2479
2480         return regs->ip + code_segment_base(regs);
2481 }
2482
2483 unsigned long perf_misc_flags(struct pt_regs *regs)
2484 {
2485         int misc = 0;
2486
2487         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2488                 if (perf_guest_cbs->is_user_mode())
2489                         misc |= PERF_RECORD_MISC_GUEST_USER;
2490                 else
2491                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2492         } else {
2493                 if (user_mode(regs))
2494                         misc |= PERF_RECORD_MISC_USER;
2495                 else
2496                         misc |= PERF_RECORD_MISC_KERNEL;
2497         }
2498
2499         if (regs->flags & PERF_EFLAGS_EXACT)
2500                 misc |= PERF_RECORD_MISC_EXACT_IP;
2501
2502         return misc;
2503 }
2504
2505 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2506 {
2507         cap->version            = x86_pmu.version;
2508         cap->num_counters_gp    = x86_pmu.num_counters;
2509         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2510         cap->bit_width_gp       = x86_pmu.cntval_bits;
2511         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2512         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2513         cap->events_mask_len    = x86_pmu.events_mask_len;
2514 }
2515 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);