2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
59 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
60 * from just a typename, as opposed to an actual function.
62 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
63 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
68 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
70 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
74 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
76 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
78 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
80 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
83 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
86 u64 __read_mostly hw_cache_event_ids
87 [PERF_COUNT_HW_CACHE_MAX]
88 [PERF_COUNT_HW_CACHE_OP_MAX]
89 [PERF_COUNT_HW_CACHE_RESULT_MAX];
90 u64 __read_mostly hw_cache_extra_regs
91 [PERF_COUNT_HW_CACHE_MAX]
92 [PERF_COUNT_HW_CACHE_OP_MAX]
93 [PERF_COUNT_HW_CACHE_RESULT_MAX];
96 * Propagate event elapsed time into the generic event.
97 * Can only be executed on the CPU where the event is active.
98 * Returns the delta events processed.
100 u64 x86_perf_event_update(struct perf_event *event)
102 struct hw_perf_event *hwc = &event->hw;
103 int shift = 64 - x86_pmu.cntval_bits;
104 u64 prev_raw_count, new_raw_count;
107 if (unlikely(!hwc->event_base))
110 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
111 return x86_pmu.update_topdown_event(event);
114 * Careful: an NMI might modify the previous event value.
116 * Our tactic to handle this is to first atomically read and
117 * exchange a new raw count - then add that new-prev delta
118 * count to the generic event atomically:
121 prev_raw_count = local64_read(&hwc->prev_count);
122 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
124 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
125 new_raw_count) != prev_raw_count)
129 * Now we have the new raw value and have updated the prev
130 * timestamp already. We can now calculate the elapsed delta
131 * (event-)time and add that to the generic event.
133 * Careful, not all hw sign-extends above the physical width
136 delta = (new_raw_count << shift) - (prev_raw_count << shift);
139 local64_add(delta, &event->count);
140 local64_sub(delta, &hwc->period_left);
142 return new_raw_count;
146 * Find and validate any extra registers to set up.
148 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
150 struct hw_perf_event_extra *reg;
151 struct extra_reg *er;
153 reg = &event->hw.extra_reg;
155 if (!x86_pmu.extra_regs)
158 for (er = x86_pmu.extra_regs; er->msr; er++) {
159 if (er->event != (config & er->config_mask))
161 if (event->attr.config1 & ~er->valid_mask)
163 /* Check if the extra msrs can be safely accessed*/
164 if (!er->extra_msr_access)
168 reg->config = event->attr.config1;
175 static atomic_t active_events;
176 static atomic_t pmc_refcount;
177 static DEFINE_MUTEX(pmc_reserve_mutex);
179 #ifdef CONFIG_X86_LOCAL_APIC
181 static bool reserve_pmc_hardware(void)
185 for (i = 0; i < x86_pmu.num_counters; i++) {
186 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
190 for (i = 0; i < x86_pmu.num_counters; i++) {
191 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
198 for (i--; i >= 0; i--)
199 release_evntsel_nmi(x86_pmu_config_addr(i));
201 i = x86_pmu.num_counters;
204 for (i--; i >= 0; i--)
205 release_perfctr_nmi(x86_pmu_event_addr(i));
210 static void release_pmc_hardware(void)
214 for (i = 0; i < x86_pmu.num_counters; i++) {
215 release_perfctr_nmi(x86_pmu_event_addr(i));
216 release_evntsel_nmi(x86_pmu_config_addr(i));
222 static bool reserve_pmc_hardware(void) { return true; }
223 static void release_pmc_hardware(void) {}
227 static bool check_hw_exists(void)
229 u64 val, val_fail = -1, val_new= ~0;
230 int i, reg, reg_fail = -1, ret = 0;
235 * Check to see if the BIOS enabled any of the counters, if so
238 for (i = 0; i < x86_pmu.num_counters; i++) {
239 reg = x86_pmu_config_addr(i);
240 ret = rdmsrl_safe(reg, &val);
243 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
252 if (x86_pmu.num_counters_fixed) {
253 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
254 ret = rdmsrl_safe(reg, &val);
257 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
258 if (val & (0x03 << i*4)) {
267 * If all the counters are enabled, the below test will always
268 * fail. The tools will also become useless in this scenario.
269 * Just fail and disable the hardware counters.
272 if (reg_safe == -1) {
278 * Read the current value, change it and read it back to see if it
279 * matches, this is needed to detect certain hardware emulators
280 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
282 reg = x86_pmu_event_addr(reg_safe);
283 if (rdmsrl_safe(reg, &val))
286 ret = wrmsrl_safe(reg, val);
287 ret |= rdmsrl_safe(reg, &val_new);
288 if (ret || val != val_new)
292 * We still allow the PMU driver to operate:
295 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
296 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
303 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
304 pr_cont("PMU not available due to virtualization, using software events only.\n");
306 pr_cont("Broken PMU hardware detected, using software events only.\n");
307 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
314 static void hw_perf_event_destroy(struct perf_event *event)
316 x86_release_hardware();
317 atomic_dec(&active_events);
320 void hw_perf_lbr_event_destroy(struct perf_event *event)
322 hw_perf_event_destroy(event);
324 /* undo the lbr/bts event accounting */
325 x86_del_exclusive(x86_lbr_exclusive_lbr);
328 static inline int x86_pmu_initialized(void)
330 return x86_pmu.handle_irq != NULL;
334 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
336 struct perf_event_attr *attr = &event->attr;
337 unsigned int cache_type, cache_op, cache_result;
340 config = attr->config;
342 cache_type = (config >> 0) & 0xff;
343 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
345 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
347 cache_op = (config >> 8) & 0xff;
348 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
350 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
352 cache_result = (config >> 16) & 0xff;
353 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
355 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
357 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
366 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
367 return x86_pmu_extra_regs(val, event);
370 int x86_reserve_hardware(void)
374 if (!atomic_inc_not_zero(&pmc_refcount)) {
375 mutex_lock(&pmc_reserve_mutex);
376 if (atomic_read(&pmc_refcount) == 0) {
377 if (!reserve_pmc_hardware()) {
380 reserve_ds_buffers();
381 reserve_lbr_buffers();
385 atomic_inc(&pmc_refcount);
386 mutex_unlock(&pmc_reserve_mutex);
392 void x86_release_hardware(void)
394 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
395 release_pmc_hardware();
396 release_ds_buffers();
397 release_lbr_buffers();
398 mutex_unlock(&pmc_reserve_mutex);
403 * Check if we can create event of a certain type (that no conflicting events
406 int x86_add_exclusive(unsigned int what)
411 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
412 * LBR and BTS are still mutually exclusive.
414 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
417 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
418 mutex_lock(&pmc_reserve_mutex);
419 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
420 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
423 atomic_inc(&x86_pmu.lbr_exclusive[what]);
424 mutex_unlock(&pmc_reserve_mutex);
428 atomic_inc(&active_events);
432 mutex_unlock(&pmc_reserve_mutex);
436 void x86_del_exclusive(unsigned int what)
438 atomic_dec(&active_events);
441 * See the comment in x86_add_exclusive().
443 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
446 atomic_dec(&x86_pmu.lbr_exclusive[what]);
449 int x86_setup_perfctr(struct perf_event *event)
451 struct perf_event_attr *attr = &event->attr;
452 struct hw_perf_event *hwc = &event->hw;
455 if (!is_sampling_event(event)) {
456 hwc->sample_period = x86_pmu.max_period;
457 hwc->last_period = hwc->sample_period;
458 local64_set(&hwc->period_left, hwc->sample_period);
461 if (attr->type == PERF_TYPE_RAW)
462 return x86_pmu_extra_regs(event->attr.config, event);
464 if (attr->type == PERF_TYPE_HW_CACHE)
465 return set_ext_hw_attr(hwc, event);
467 if (attr->config >= x86_pmu.max_events)
470 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
475 config = x86_pmu.event_map(attr->config);
483 hwc->config |= config;
489 * check that branch_sample_type is compatible with
490 * settings needed for precise_ip > 1 which implies
491 * using the LBR to capture ALL taken branches at the
492 * priv levels of the measurement
494 static inline int precise_br_compat(struct perf_event *event)
496 u64 m = event->attr.branch_sample_type;
499 /* must capture all branches */
500 if (!(m & PERF_SAMPLE_BRANCH_ANY))
503 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
505 if (!event->attr.exclude_user)
506 b |= PERF_SAMPLE_BRANCH_USER;
508 if (!event->attr.exclude_kernel)
509 b |= PERF_SAMPLE_BRANCH_KERNEL;
512 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
518 int x86_pmu_max_precise(void)
522 /* Support for constant skid */
523 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
526 /* Support for IP fixup */
527 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
530 if (x86_pmu.pebs_prec_dist)
536 int x86_pmu_hw_config(struct perf_event *event)
538 if (event->attr.precise_ip) {
539 int precise = x86_pmu_max_precise();
541 if (event->attr.precise_ip > precise)
544 /* There's no sense in having PEBS for non sampling events: */
545 if (!is_sampling_event(event))
549 * check that PEBS LBR correction does not conflict with
550 * whatever the user is asking with attr->branch_sample_type
552 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
553 u64 *br_type = &event->attr.branch_sample_type;
555 if (has_branch_stack(event)) {
556 if (!precise_br_compat(event))
559 /* branch_sample_type is compatible */
563 * user did not specify branch_sample_type
565 * For PEBS fixups, we capture all
566 * the branches at the priv level of the
569 *br_type = PERF_SAMPLE_BRANCH_ANY;
571 if (!event->attr.exclude_user)
572 *br_type |= PERF_SAMPLE_BRANCH_USER;
574 if (!event->attr.exclude_kernel)
575 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
579 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
580 event->attach_state |= PERF_ATTACH_TASK_DATA;
584 * (keep 'enabled' bit clear for now)
586 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
589 * Count user and OS events unless requested not to
591 if (!event->attr.exclude_user)
592 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
593 if (!event->attr.exclude_kernel)
594 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
596 if (event->attr.type == PERF_TYPE_RAW)
597 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
599 if (event->attr.sample_period && x86_pmu.limit_period) {
600 if (x86_pmu.limit_period(event, event->attr.sample_period) >
601 event->attr.sample_period)
605 /* sample_regs_user never support XMM registers */
606 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
609 * Besides the general purpose registers, XMM registers may
610 * be collected in PEBS on some platforms, e.g. Icelake
612 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
613 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
616 if (!event->attr.precise_ip)
620 return x86_setup_perfctr(event);
624 * Setup the hardware configuration for a given attr_type
626 static int __x86_pmu_event_init(struct perf_event *event)
630 if (!x86_pmu_initialized())
633 err = x86_reserve_hardware();
637 atomic_inc(&active_events);
638 event->destroy = hw_perf_event_destroy;
641 event->hw.last_cpu = -1;
642 event->hw.last_tag = ~0ULL;
645 event->hw.extra_reg.idx = EXTRA_REG_NONE;
646 event->hw.branch_reg.idx = EXTRA_REG_NONE;
648 return x86_pmu.hw_config(event);
651 void x86_pmu_disable_all(void)
653 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
656 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
657 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
660 if (!test_bit(idx, cpuc->active_mask))
662 rdmsrl(x86_pmu_config_addr(idx), val);
663 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
665 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
666 wrmsrl(x86_pmu_config_addr(idx), val);
667 if (is_counter_pair(hwc))
668 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
673 * There may be PMI landing after enabled=0. The PMI hitting could be before or
676 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
677 * It will not be re-enabled in the NMI handler again, because enabled=0. After
678 * handling the NMI, disable_all will be called, which will not change the
679 * state either. If PMI hits after disable_all, the PMU is already disabled
680 * before entering NMI handler. The NMI handler will not change the state
683 * So either situation is harmless.
685 static void x86_pmu_disable(struct pmu *pmu)
687 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
689 if (!x86_pmu_initialized())
699 static_call(x86_pmu_disable_all)();
702 void x86_pmu_enable_all(int added)
704 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
707 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
708 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
710 if (!test_bit(idx, cpuc->active_mask))
713 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
717 static inline int is_x86_event(struct perf_event *event)
719 return event->pmu == &pmu;
722 struct pmu *x86_get_pmu(unsigned int cpu)
724 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
727 * All CPUs of the hybrid type have been offline.
728 * The x86_get_pmu() should not be invoked.
730 if (WARN_ON_ONCE(!cpuc->pmu))
736 * Event scheduler state:
738 * Assign events iterating over all events and counters, beginning
739 * with events with least weights first. Keep the current iterator
740 * state in struct sched_state.
744 int event; /* event index */
745 int counter; /* counter index */
746 int unassigned; /* number of events to be assigned left */
747 int nr_gp; /* number of GP counters used */
751 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
752 #define SCHED_STATES_MAX 2
759 struct event_constraint **constraints;
760 struct sched_state state;
761 struct sched_state saved[SCHED_STATES_MAX];
765 * Initialize interator that runs through all events and counters.
767 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
768 int num, int wmin, int wmax, int gpmax)
772 memset(sched, 0, sizeof(*sched));
773 sched->max_events = num;
774 sched->max_weight = wmax;
775 sched->max_gp = gpmax;
776 sched->constraints = constraints;
778 for (idx = 0; idx < num; idx++) {
779 if (constraints[idx]->weight == wmin)
783 sched->state.event = idx; /* start with min weight */
784 sched->state.weight = wmin;
785 sched->state.unassigned = num;
788 static void perf_sched_save_state(struct perf_sched *sched)
790 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
793 sched->saved[sched->saved_states] = sched->state;
794 sched->saved_states++;
797 static bool perf_sched_restore_state(struct perf_sched *sched)
799 if (!sched->saved_states)
802 sched->saved_states--;
803 sched->state = sched->saved[sched->saved_states];
805 /* this assignment didn't work out */
806 /* XXX broken vs EVENT_PAIR */
807 sched->state.used &= ~BIT_ULL(sched->state.counter);
809 /* try the next one */
810 sched->state.counter++;
816 * Select a counter for the current event to schedule. Return true on
819 static bool __perf_sched_find_counter(struct perf_sched *sched)
821 struct event_constraint *c;
824 if (!sched->state.unassigned)
827 if (sched->state.event >= sched->max_events)
830 c = sched->constraints[sched->state.event];
831 /* Prefer fixed purpose counters */
832 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
833 idx = INTEL_PMC_IDX_FIXED;
834 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
835 u64 mask = BIT_ULL(idx);
837 if (sched->state.used & mask)
840 sched->state.used |= mask;
845 /* Grab the first unused counter starting with idx */
846 idx = sched->state.counter;
847 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
848 u64 mask = BIT_ULL(idx);
850 if (c->flags & PERF_X86_EVENT_PAIR)
853 if (sched->state.used & mask)
856 if (sched->state.nr_gp++ >= sched->max_gp)
859 sched->state.used |= mask;
866 sched->state.counter = idx;
869 perf_sched_save_state(sched);
874 static bool perf_sched_find_counter(struct perf_sched *sched)
876 while (!__perf_sched_find_counter(sched)) {
877 if (!perf_sched_restore_state(sched))
885 * Go through all unassigned events and find the next one to schedule.
886 * Take events with the least weight first. Return true on success.
888 static bool perf_sched_next_event(struct perf_sched *sched)
890 struct event_constraint *c;
892 if (!sched->state.unassigned || !--sched->state.unassigned)
897 sched->state.event++;
898 if (sched->state.event >= sched->max_events) {
900 sched->state.event = 0;
901 sched->state.weight++;
902 if (sched->state.weight > sched->max_weight)
905 c = sched->constraints[sched->state.event];
906 } while (c->weight != sched->state.weight);
908 sched->state.counter = 0; /* start with first counter */
914 * Assign a counter for each event.
916 int perf_assign_events(struct event_constraint **constraints, int n,
917 int wmin, int wmax, int gpmax, int *assign)
919 struct perf_sched sched;
921 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
924 if (!perf_sched_find_counter(&sched))
927 assign[sched.state.event] = sched.state.counter;
928 } while (perf_sched_next_event(&sched));
930 return sched.state.unassigned;
932 EXPORT_SYMBOL_GPL(perf_assign_events);
934 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
936 struct event_constraint *c;
937 struct perf_event *e;
938 int n0, i, wmin, wmax, unsched = 0;
939 struct hw_perf_event *hwc;
943 * Compute the number of events already present; see x86_pmu_add(),
944 * validate_group() and x86_pmu_commit_txn(). For the former two
945 * cpuc->n_events hasn't been updated yet, while for the latter
946 * cpuc->n_txn contains the number of events added in the current
950 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
953 static_call_cond(x86_pmu_start_scheduling)(cpuc);
955 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
956 c = cpuc->event_constraint[i];
959 * Previously scheduled events should have a cached constraint,
960 * while new events should not have one.
962 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
965 * Request constraints for new events; or for those events that
966 * have a dynamic constraint -- for those the constraint can
967 * change due to external factors (sibling state, allow_tfa).
969 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
970 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
971 cpuc->event_constraint[i] = c;
974 wmin = min(wmin, c->weight);
975 wmax = max(wmax, c->weight);
979 * fastpath, try to reuse previous register
981 for (i = 0; i < n; i++) {
984 hwc = &cpuc->event_list[i]->hw;
985 c = cpuc->event_constraint[i];
991 /* constraint still honored */
992 if (!test_bit(hwc->idx, c->idxmsk))
995 mask = BIT_ULL(hwc->idx);
996 if (is_counter_pair(hwc))
999 /* not already used */
1000 if (used_mask & mask)
1006 assign[i] = hwc->idx;
1011 int gpmax = x86_pmu.num_counters;
1014 * Do not allow scheduling of more than half the available
1017 * This helps avoid counter starvation of sibling thread by
1018 * ensuring at most half the counters cannot be in exclusive
1019 * mode. There is no designated counters for the limits. Any
1020 * N/2 counters can be used. This helps with events with
1021 * specific counter constraints.
1023 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1024 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1028 * Reduce the amount of available counters to allow fitting
1029 * the extra Merge events needed by large increment events.
1031 if (x86_pmu.flags & PMU_FL_PAIR) {
1032 gpmax = x86_pmu.num_counters - cpuc->n_pair;
1033 WARN_ON(gpmax <= 0);
1036 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1037 wmax, gpmax, assign);
1041 * In case of success (unsched = 0), mark events as committed,
1042 * so we do not put_constraint() in case new events are added
1043 * and fail to be scheduled
1045 * We invoke the lower level commit callback to lock the resource
1047 * We do not need to do all of this in case we are called to
1048 * validate an event group (assign == NULL)
1050 if (!unsched && assign) {
1051 for (i = 0; i < n; i++) {
1052 e = cpuc->event_list[i];
1053 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1056 for (i = n0; i < n; i++) {
1057 e = cpuc->event_list[i];
1060 * release events that failed scheduling
1062 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1064 cpuc->event_constraint[i] = NULL;
1068 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1070 return unsched ? -EINVAL : 0;
1073 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1074 struct perf_event *event)
1076 if (is_metric_event(event)) {
1077 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1080 cpuc->n_txn_metric++;
1086 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1087 struct perf_event *event)
1089 if (is_metric_event(event))
1093 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1094 int max_count, int n)
1097 if (x86_pmu.intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1100 if (n >= max_count + cpuc->n_metric)
1103 cpuc->event_list[n] = event;
1104 if (is_counter_pair(&event->hw)) {
1113 * dogrp: true if must collect siblings events (group)
1114 * returns total number of events and error code
1116 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1118 struct perf_event *event;
1121 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1123 /* current number of events already accepted */
1125 if (!cpuc->n_events)
1126 cpuc->pebs_output = 0;
1128 if (!cpuc->is_fake && leader->attr.precise_ip) {
1130 * For PEBS->PT, if !aux_event, the group leader (PT) went
1131 * away, the group was broken down and this singleton event
1132 * can't schedule any more.
1134 if (is_pebs_pt(leader) && !leader->aux_event)
1138 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1140 if (cpuc->pebs_output &&
1141 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1144 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1147 if (is_x86_event(leader)) {
1148 if (collect_event(cpuc, leader, max_count, n))
1156 for_each_sibling_event(event, leader) {
1157 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1160 if (collect_event(cpuc, event, max_count, n))
1168 static inline void x86_assign_hw_event(struct perf_event *event,
1169 struct cpu_hw_events *cpuc, int i)
1171 struct hw_perf_event *hwc = &event->hw;
1174 idx = hwc->idx = cpuc->assign[i];
1175 hwc->last_cpu = smp_processor_id();
1176 hwc->last_tag = ++cpuc->tags[i];
1179 case INTEL_PMC_IDX_FIXED_BTS:
1180 case INTEL_PMC_IDX_FIXED_VLBR:
1181 hwc->config_base = 0;
1182 hwc->event_base = 0;
1185 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1186 /* All the metric events are mapped onto the fixed counter 3. */
1187 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1189 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1190 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1191 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1192 (idx - INTEL_PMC_IDX_FIXED);
1193 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1194 INTEL_PMC_FIXED_RDPMC_BASE;
1198 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1199 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1200 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1206 * x86_perf_rdpmc_index - Return PMC counter used for event
1207 * @event: the perf_event to which the PMC counter was assigned
1209 * The counter assigned to this performance event may change if interrupts
1210 * are enabled. This counter should thus never be used while interrupts are
1211 * enabled. Before this function is used to obtain the assigned counter the
1212 * event should be checked for validity using, for example,
1213 * perf_event_read_local(), within the same interrupt disabled section in
1214 * which this counter is planned to be used.
1216 * Return: The index of the performance monitoring counter assigned to
1219 int x86_perf_rdpmc_index(struct perf_event *event)
1221 lockdep_assert_irqs_disabled();
1223 return event->hw.event_base_rdpmc;
1226 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1227 struct cpu_hw_events *cpuc,
1230 return hwc->idx == cpuc->assign[i] &&
1231 hwc->last_cpu == smp_processor_id() &&
1232 hwc->last_tag == cpuc->tags[i];
1235 static void x86_pmu_start(struct perf_event *event, int flags);
1237 static void x86_pmu_enable(struct pmu *pmu)
1239 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1240 struct perf_event *event;
1241 struct hw_perf_event *hwc;
1242 int i, added = cpuc->n_added;
1244 if (!x86_pmu_initialized())
1250 if (cpuc->n_added) {
1251 int n_running = cpuc->n_events - cpuc->n_added;
1253 * apply assignment obtained either from
1254 * hw_perf_group_sched_in() or x86_pmu_enable()
1256 * step1: save events moving to new counters
1258 for (i = 0; i < n_running; i++) {
1259 event = cpuc->event_list[i];
1263 * we can avoid reprogramming counter if:
1264 * - assigned same counter as last time
1265 * - running on same CPU as last time
1266 * - no other event has used the counter since
1268 if (hwc->idx == -1 ||
1269 match_prev_assignment(hwc, cpuc, i))
1273 * Ensure we don't accidentally enable a stopped
1274 * counter simply because we rescheduled.
1276 if (hwc->state & PERF_HES_STOPPED)
1277 hwc->state |= PERF_HES_ARCH;
1279 x86_pmu_stop(event, PERF_EF_UPDATE);
1283 * step2: reprogram moved events into new counters
1285 for (i = 0; i < cpuc->n_events; i++) {
1286 event = cpuc->event_list[i];
1289 if (!match_prev_assignment(hwc, cpuc, i))
1290 x86_assign_hw_event(event, cpuc, i);
1291 else if (i < n_running)
1294 if (hwc->state & PERF_HES_ARCH)
1297 x86_pmu_start(event, PERF_EF_RELOAD);
1300 perf_events_lapic_init();
1306 static_call(x86_pmu_enable_all)(added);
1309 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1312 * Set the next IRQ period, based on the hwc->period_left value.
1313 * To be called with the event disabled in hw:
1315 int x86_perf_event_set_period(struct perf_event *event)
1317 struct hw_perf_event *hwc = &event->hw;
1318 s64 left = local64_read(&hwc->period_left);
1319 s64 period = hwc->sample_period;
1320 int ret = 0, idx = hwc->idx;
1322 if (unlikely(!hwc->event_base))
1325 if (unlikely(is_topdown_count(event)) &&
1326 x86_pmu.set_topdown_event_period)
1327 return x86_pmu.set_topdown_event_period(event);
1330 * If we are way outside a reasonable range then just skip forward:
1332 if (unlikely(left <= -period)) {
1334 local64_set(&hwc->period_left, left);
1335 hwc->last_period = period;
1339 if (unlikely(left <= 0)) {
1341 local64_set(&hwc->period_left, left);
1342 hwc->last_period = period;
1346 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1348 if (unlikely(left < 2))
1351 if (left > x86_pmu.max_period)
1352 left = x86_pmu.max_period;
1354 if (x86_pmu.limit_period)
1355 left = x86_pmu.limit_period(event, left);
1357 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1360 * The hw event starts counting from this event offset,
1361 * mark it to be able to extra future deltas:
1363 local64_set(&hwc->prev_count, (u64)-left);
1365 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1368 * Sign extend the Merge event counter's upper 16 bits since
1369 * we currently declare a 48-bit counter width
1371 if (is_counter_pair(hwc))
1372 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1375 * Due to erratum on certan cpu we need
1376 * a second write to be sure the register
1377 * is updated properly
1379 if (x86_pmu.perfctr_second_write) {
1380 wrmsrl(hwc->event_base,
1381 (u64)(-left) & x86_pmu.cntval_mask);
1384 perf_event_update_userpage(event);
1389 void x86_pmu_enable_event(struct perf_event *event)
1391 if (__this_cpu_read(cpu_hw_events.enabled))
1392 __x86_pmu_enable_event(&event->hw,
1393 ARCH_PERFMON_EVENTSEL_ENABLE);
1397 * Add a single event to the PMU.
1399 * The event is added to the group of enabled events
1400 * but only if it can be scheduled with existing events.
1402 static int x86_pmu_add(struct perf_event *event, int flags)
1404 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1405 struct hw_perf_event *hwc;
1406 int assign[X86_PMC_IDX_MAX];
1411 n0 = cpuc->n_events;
1412 ret = n = collect_events(cpuc, event, false);
1416 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1417 if (!(flags & PERF_EF_START))
1418 hwc->state |= PERF_HES_ARCH;
1421 * If group events scheduling transaction was started,
1422 * skip the schedulability test here, it will be performed
1423 * at commit time (->commit_txn) as a whole.
1425 * If commit fails, we'll call ->del() on all events
1426 * for which ->add() was called.
1428 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1431 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1435 * copy new assignment, now we know it is possible
1436 * will be used by hw_perf_enable()
1438 memcpy(cpuc->assign, assign, n*sizeof(int));
1442 * Commit the collect_events() state. See x86_pmu_del() and
1446 cpuc->n_added += n - n0;
1447 cpuc->n_txn += n - n0;
1450 * This is before x86_pmu_enable() will call x86_pmu_start(),
1451 * so we enable LBRs before an event needs them etc..
1453 static_call_cond(x86_pmu_add)(event);
1460 static void x86_pmu_start(struct perf_event *event, int flags)
1462 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1463 int idx = event->hw.idx;
1465 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1468 if (WARN_ON_ONCE(idx == -1))
1471 if (flags & PERF_EF_RELOAD) {
1472 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1473 x86_perf_event_set_period(event);
1476 event->hw.state = 0;
1478 cpuc->events[idx] = event;
1479 __set_bit(idx, cpuc->active_mask);
1480 __set_bit(idx, cpuc->running);
1481 static_call(x86_pmu_enable)(event);
1482 perf_event_update_userpage(event);
1485 void perf_event_print_debug(void)
1487 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1489 struct cpu_hw_events *cpuc;
1490 unsigned long flags;
1493 if (!x86_pmu.num_counters)
1496 local_irq_save(flags);
1498 cpu = smp_processor_id();
1499 cpuc = &per_cpu(cpu_hw_events, cpu);
1501 if (x86_pmu.version >= 2) {
1502 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1503 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1504 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1505 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1508 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1509 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1510 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1511 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1512 if (x86_pmu.pebs_constraints) {
1513 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1514 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1516 if (x86_pmu.lbr_nr) {
1517 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1518 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1521 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1523 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1524 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1525 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1527 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1529 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1530 cpu, idx, pmc_ctrl);
1531 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1532 cpu, idx, pmc_count);
1533 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1534 cpu, idx, prev_left);
1536 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1537 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1539 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1540 cpu, idx, pmc_count);
1542 local_irq_restore(flags);
1545 void x86_pmu_stop(struct perf_event *event, int flags)
1547 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1548 struct hw_perf_event *hwc = &event->hw;
1550 if (test_bit(hwc->idx, cpuc->active_mask)) {
1551 static_call(x86_pmu_disable)(event);
1552 __clear_bit(hwc->idx, cpuc->active_mask);
1553 cpuc->events[hwc->idx] = NULL;
1554 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1555 hwc->state |= PERF_HES_STOPPED;
1558 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1560 * Drain the remaining delta count out of a event
1561 * that we are disabling:
1563 x86_perf_event_update(event);
1564 hwc->state |= PERF_HES_UPTODATE;
1568 static void x86_pmu_del(struct perf_event *event, int flags)
1570 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1574 * If we're called during a txn, we only need to undo x86_pmu.add.
1575 * The events never got scheduled and ->cancel_txn will truncate
1578 * XXX assumes any ->del() called during a TXN will only be on
1579 * an event added during that same TXN.
1581 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1585 * Not a TXN, therefore cleanup properly.
1587 x86_pmu_stop(event, PERF_EF_UPDATE);
1589 for (i = 0; i < cpuc->n_events; i++) {
1590 if (event == cpuc->event_list[i])
1594 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1597 /* If we have a newly added event; make sure to decrease n_added. */
1598 if (i >= cpuc->n_events - cpuc->n_added)
1601 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1603 /* Delete the array entry. */
1604 while (++i < cpuc->n_events) {
1605 cpuc->event_list[i-1] = cpuc->event_list[i];
1606 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1608 cpuc->event_constraint[i-1] = NULL;
1610 if (x86_pmu.intel_cap.perf_metrics)
1611 del_nr_metric_event(cpuc, event);
1613 perf_event_update_userpage(event);
1618 * This is after x86_pmu_stop(); so we disable LBRs after any
1619 * event can need them etc..
1621 static_call_cond(x86_pmu_del)(event);
1624 int x86_pmu_handle_irq(struct pt_regs *regs)
1626 struct perf_sample_data data;
1627 struct cpu_hw_events *cpuc;
1628 struct perf_event *event;
1629 int idx, handled = 0;
1632 cpuc = this_cpu_ptr(&cpu_hw_events);
1635 * Some chipsets need to unmask the LVTPC in a particular spot
1636 * inside the nmi handler. As a result, the unmasking was pushed
1637 * into all the nmi handlers.
1639 * This generic handler doesn't seem to have any issues where the
1640 * unmasking occurs so it was left at the top.
1642 apic_write(APIC_LVTPC, APIC_DM_NMI);
1644 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1645 if (!test_bit(idx, cpuc->active_mask))
1648 event = cpuc->events[idx];
1650 val = x86_perf_event_update(event);
1651 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1658 perf_sample_data_init(&data, 0, event->hw.last_period);
1660 if (!x86_perf_event_set_period(event))
1663 if (perf_event_overflow(event, &data, regs))
1664 x86_pmu_stop(event, 0);
1668 inc_irq_stat(apic_perf_irqs);
1673 void perf_events_lapic_init(void)
1675 if (!x86_pmu.apic || !x86_pmu_initialized())
1679 * Always use NMI for PMU
1681 apic_write(APIC_LVTPC, APIC_DM_NMI);
1685 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1692 * All PMUs/events that share this PMI handler should make sure to
1693 * increment active_events for their events.
1695 if (!atomic_read(&active_events))
1698 start_clock = sched_clock();
1699 ret = static_call(x86_pmu_handle_irq)(regs);
1700 finish_clock = sched_clock();
1702 perf_sample_event_took(finish_clock - start_clock);
1706 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1708 struct event_constraint emptyconstraint;
1709 struct event_constraint unconstrained;
1711 static int x86_pmu_prepare_cpu(unsigned int cpu)
1713 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1716 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1717 cpuc->kfree_on_online[i] = NULL;
1718 if (x86_pmu.cpu_prepare)
1719 return x86_pmu.cpu_prepare(cpu);
1723 static int x86_pmu_dead_cpu(unsigned int cpu)
1725 if (x86_pmu.cpu_dead)
1726 x86_pmu.cpu_dead(cpu);
1730 static int x86_pmu_online_cpu(unsigned int cpu)
1732 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1735 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1736 kfree(cpuc->kfree_on_online[i]);
1737 cpuc->kfree_on_online[i] = NULL;
1742 static int x86_pmu_starting_cpu(unsigned int cpu)
1744 if (x86_pmu.cpu_starting)
1745 x86_pmu.cpu_starting(cpu);
1749 static int x86_pmu_dying_cpu(unsigned int cpu)
1751 if (x86_pmu.cpu_dying)
1752 x86_pmu.cpu_dying(cpu);
1756 static void __init pmu_check_apic(void)
1758 if (boot_cpu_has(X86_FEATURE_APIC))
1762 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1763 pr_info("no hardware sampling interrupt available.\n");
1766 * If we have a PMU initialized but no APIC
1767 * interrupts, we cannot sample hardware
1768 * events (user-space has to fall back and
1769 * sample via a hrtimer based software event):
1771 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1775 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1780 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1782 struct perf_pmu_events_attr *pmu_attr =
1783 container_of(attr, struct perf_pmu_events_attr, attr);
1786 if (pmu_attr->id < x86_pmu.max_events)
1787 config = x86_pmu.event_map(pmu_attr->id);
1789 /* string trumps id */
1790 if (pmu_attr->event_str)
1791 return sprintf(page, "%s", pmu_attr->event_str);
1793 return x86_pmu.events_sysfs_show(page, config);
1795 EXPORT_SYMBOL_GPL(events_sysfs_show);
1797 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1800 struct perf_pmu_events_ht_attr *pmu_attr =
1801 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1804 * Report conditional events depending on Hyper-Threading.
1806 * This is overly conservative as usually the HT special
1807 * handling is not needed if the other CPU thread is idle.
1809 * Note this does not (and cannot) handle the case when thread
1810 * siblings are invisible, for example with virtualization
1811 * if they are owned by some other guest. The user tool
1812 * has to re-read when a thread sibling gets onlined later.
1814 return sprintf(page, "%s",
1815 topology_max_smt_threads() > 1 ?
1816 pmu_attr->event_str_ht :
1817 pmu_attr->event_str_noht);
1820 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1821 EVENT_ATTR(instructions, INSTRUCTIONS );
1822 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1823 EVENT_ATTR(cache-misses, CACHE_MISSES );
1824 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1825 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1826 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1827 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1828 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1829 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1831 static struct attribute *empty_attrs;
1833 static struct attribute *events_attr[] = {
1834 EVENT_PTR(CPU_CYCLES),
1835 EVENT_PTR(INSTRUCTIONS),
1836 EVENT_PTR(CACHE_REFERENCES),
1837 EVENT_PTR(CACHE_MISSES),
1838 EVENT_PTR(BRANCH_INSTRUCTIONS),
1839 EVENT_PTR(BRANCH_MISSES),
1840 EVENT_PTR(BUS_CYCLES),
1841 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1842 EVENT_PTR(STALLED_CYCLES_BACKEND),
1843 EVENT_PTR(REF_CPU_CYCLES),
1848 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1849 * out of events_attr attributes.
1852 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1854 struct perf_pmu_events_attr *pmu_attr;
1856 if (idx >= x86_pmu.max_events)
1859 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1861 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1864 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1866 .attrs = events_attr,
1867 .is_visible = is_visible,
1870 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1872 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1873 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1874 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1875 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1876 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1877 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1881 * We have whole page size to spend and just little data
1882 * to write, so we can safely use sprintf.
1884 ret = sprintf(page, "event=0x%02llx", event);
1887 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1890 ret += sprintf(page + ret, ",edge");
1893 ret += sprintf(page + ret, ",pc");
1896 ret += sprintf(page + ret, ",any");
1899 ret += sprintf(page + ret, ",inv");
1902 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1904 ret += sprintf(page + ret, "\n");
1909 static struct attribute_group x86_pmu_attr_group;
1910 static struct attribute_group x86_pmu_caps_group;
1912 static void x86_pmu_static_call_update(void)
1914 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
1915 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
1916 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
1917 static_call_update(x86_pmu_enable, x86_pmu.enable);
1918 static_call_update(x86_pmu_disable, x86_pmu.disable);
1920 static_call_update(x86_pmu_add, x86_pmu.add);
1921 static_call_update(x86_pmu_del, x86_pmu.del);
1922 static_call_update(x86_pmu_read, x86_pmu.read);
1924 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
1925 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
1926 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
1928 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
1929 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
1930 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
1932 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
1933 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
1935 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
1936 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
1939 static void _x86_pmu_read(struct perf_event *event)
1941 x86_perf_event_update(event);
1944 static int __init init_hw_perf_events(void)
1946 struct x86_pmu_quirk *quirk;
1949 pr_info("Performance Events: ");
1951 switch (boot_cpu_data.x86_vendor) {
1952 case X86_VENDOR_INTEL:
1953 err = intel_pmu_init();
1955 case X86_VENDOR_AMD:
1956 err = amd_pmu_init();
1958 case X86_VENDOR_HYGON:
1959 err = amd_pmu_init();
1960 x86_pmu.name = "HYGON";
1962 case X86_VENDOR_ZHAOXIN:
1963 case X86_VENDOR_CENTAUR:
1964 err = zhaoxin_pmu_init();
1970 pr_cont("no PMU driver, software events only.\n");
1976 /* sanity check that the hardware exists or is emulated */
1977 if (!check_hw_exists())
1980 pr_cont("%s PMU driver.\n", x86_pmu.name);
1982 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1984 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1987 if (!x86_pmu.intel_ctrl)
1988 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1990 perf_events_lapic_init();
1991 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1993 unconstrained = (struct event_constraint)
1994 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1995 0, x86_pmu.num_counters, 0, 0);
1997 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1999 if (!x86_pmu.events_sysfs_show)
2000 x86_pmu_events_group.attrs = &empty_attrs;
2002 pmu.attr_update = x86_pmu.attr_update;
2004 pr_info("... version: %d\n", x86_pmu.version);
2005 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2006 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
2007 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2008 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2009 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
2010 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
2013 x86_pmu.read = _x86_pmu_read;
2015 x86_pmu_static_call_update();
2018 * Install callbacks. Core will call them for each online
2021 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2022 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2026 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2027 "perf/x86:starting", x86_pmu_starting_cpu,
2032 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2033 x86_pmu_online_cpu, NULL);
2037 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2044 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2046 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2048 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2051 early_initcall(init_hw_perf_events);
2053 static void x86_pmu_read(struct perf_event *event)
2055 static_call(x86_pmu_read)(event);
2059 * Start group events scheduling transaction
2060 * Set the flag to make pmu::enable() not perform the
2061 * schedulability test, it will be performed at commit time
2063 * We only support PERF_PMU_TXN_ADD transactions. Save the
2064 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2067 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2069 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2071 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2073 cpuc->txn_flags = txn_flags;
2074 if (txn_flags & ~PERF_PMU_TXN_ADD)
2077 perf_pmu_disable(pmu);
2078 __this_cpu_write(cpu_hw_events.n_txn, 0);
2079 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2080 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2084 * Stop group events scheduling transaction
2085 * Clear the flag and pmu::enable() will perform the
2086 * schedulability test.
2088 static void x86_pmu_cancel_txn(struct pmu *pmu)
2090 unsigned int txn_flags;
2091 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2093 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2095 txn_flags = cpuc->txn_flags;
2096 cpuc->txn_flags = 0;
2097 if (txn_flags & ~PERF_PMU_TXN_ADD)
2101 * Truncate collected array by the number of events added in this
2102 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2104 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2105 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2106 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2107 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2108 perf_pmu_enable(pmu);
2112 * Commit group events scheduling transaction
2113 * Perform the group schedulability test as a whole
2114 * Return 0 if success
2116 * Does not cancel the transaction on failure; expects the caller to do this.
2118 static int x86_pmu_commit_txn(struct pmu *pmu)
2120 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2121 int assign[X86_PMC_IDX_MAX];
2124 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2126 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2127 cpuc->txn_flags = 0;
2133 if (!x86_pmu_initialized())
2136 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2141 * copy new assignment, now we know it is possible
2142 * will be used by hw_perf_enable()
2144 memcpy(cpuc->assign, assign, n*sizeof(int));
2146 cpuc->txn_flags = 0;
2147 perf_pmu_enable(pmu);
2151 * a fake_cpuc is used to validate event groups. Due to
2152 * the extra reg logic, we need to also allocate a fake
2153 * per_core and per_cpu structure. Otherwise, group events
2154 * using extra reg may conflict without the kernel being
2155 * able to catch this when the last event gets added to
2158 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2160 intel_cpuc_finish(cpuc);
2164 static struct cpu_hw_events *allocate_fake_cpuc(void)
2166 struct cpu_hw_events *cpuc;
2167 int cpu = raw_smp_processor_id();
2169 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2171 return ERR_PTR(-ENOMEM);
2174 if (intel_cpuc_prepare(cpuc, cpu))
2179 free_fake_cpuc(cpuc);
2180 return ERR_PTR(-ENOMEM);
2184 * validate that we can schedule this event
2186 static int validate_event(struct perf_event *event)
2188 struct cpu_hw_events *fake_cpuc;
2189 struct event_constraint *c;
2192 fake_cpuc = allocate_fake_cpuc();
2193 if (IS_ERR(fake_cpuc))
2194 return PTR_ERR(fake_cpuc);
2196 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2198 if (!c || !c->weight)
2201 if (x86_pmu.put_event_constraints)
2202 x86_pmu.put_event_constraints(fake_cpuc, event);
2204 free_fake_cpuc(fake_cpuc);
2210 * validate a single event group
2212 * validation include:
2213 * - check events are compatible which each other
2214 * - events do not compete for the same counter
2215 * - number of events <= number of counters
2217 * validation ensures the group can be loaded onto the
2218 * PMU if it was the only group available.
2220 static int validate_group(struct perf_event *event)
2222 struct perf_event *leader = event->group_leader;
2223 struct cpu_hw_events *fake_cpuc;
2224 int ret = -EINVAL, n;
2226 fake_cpuc = allocate_fake_cpuc();
2227 if (IS_ERR(fake_cpuc))
2228 return PTR_ERR(fake_cpuc);
2230 * the event is not yet connected with its
2231 * siblings therefore we must first collect
2232 * existing siblings, then add the new event
2233 * before we can simulate the scheduling
2235 n = collect_events(fake_cpuc, leader, true);
2239 fake_cpuc->n_events = n;
2240 n = collect_events(fake_cpuc, event, false);
2244 fake_cpuc->n_events = 0;
2245 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2248 free_fake_cpuc(fake_cpuc);
2252 static int x86_pmu_event_init(struct perf_event *event)
2257 switch (event->attr.type) {
2259 case PERF_TYPE_HARDWARE:
2260 case PERF_TYPE_HW_CACHE:
2267 err = __x86_pmu_event_init(event);
2270 * we temporarily connect event to its pmu
2271 * such that validate_group() can classify
2272 * it as an x86 event using is_x86_event()
2277 if (event->group_leader != event)
2278 err = validate_group(event);
2280 err = validate_event(event);
2286 event->destroy(event);
2287 event->destroy = NULL;
2290 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2291 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2292 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2297 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2299 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2303 * This function relies on not being called concurrently in two
2304 * tasks in the same mm. Otherwise one task could observe
2305 * perf_rdpmc_allowed > 1 and return all the way back to
2306 * userspace with CR4.PCE clear while another task is still
2307 * doing on_each_cpu_mask() to propagate CR4.PCE.
2309 * For now, this can't happen because all callers hold mmap_lock
2310 * for write. If this changes, we'll need a different solution.
2312 mmap_assert_write_locked(mm);
2314 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2315 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2318 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2321 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2324 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2325 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2328 static int x86_pmu_event_idx(struct perf_event *event)
2330 struct hw_perf_event *hwc = &event->hw;
2332 if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2335 if (is_metric_idx(hwc->idx))
2336 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2338 return hwc->event_base_rdpmc + 1;
2341 static ssize_t get_attr_rdpmc(struct device *cdev,
2342 struct device_attribute *attr,
2345 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2348 static ssize_t set_attr_rdpmc(struct device *cdev,
2349 struct device_attribute *attr,
2350 const char *buf, size_t count)
2355 ret = kstrtoul(buf, 0, &val);
2362 if (x86_pmu.attr_rdpmc_broken)
2365 if (val != x86_pmu.attr_rdpmc) {
2367 * Changing into or out of never available or always available,
2368 * aka perf-event-bypassing mode. This path is extremely slow,
2369 * but only root can trigger it, so it's okay.
2372 static_branch_inc(&rdpmc_never_available_key);
2373 else if (x86_pmu.attr_rdpmc == 0)
2374 static_branch_dec(&rdpmc_never_available_key);
2377 static_branch_inc(&rdpmc_always_available_key);
2378 else if (x86_pmu.attr_rdpmc == 2)
2379 static_branch_dec(&rdpmc_always_available_key);
2381 on_each_cpu(cr4_update_pce, NULL, 1);
2382 x86_pmu.attr_rdpmc = val;
2388 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2390 static struct attribute *x86_pmu_attrs[] = {
2391 &dev_attr_rdpmc.attr,
2395 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2396 .attrs = x86_pmu_attrs,
2399 static ssize_t max_precise_show(struct device *cdev,
2400 struct device_attribute *attr,
2403 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2406 static DEVICE_ATTR_RO(max_precise);
2408 static struct attribute *x86_pmu_caps_attrs[] = {
2409 &dev_attr_max_precise.attr,
2413 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2415 .attrs = x86_pmu_caps_attrs,
2418 static const struct attribute_group *x86_pmu_attr_groups[] = {
2419 &x86_pmu_attr_group,
2420 &x86_pmu_format_group,
2421 &x86_pmu_events_group,
2422 &x86_pmu_caps_group,
2426 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2428 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2431 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2432 struct perf_event_context *next)
2434 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2437 void perf_check_microcode(void)
2439 if (x86_pmu.check_microcode)
2440 x86_pmu.check_microcode();
2443 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2445 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2448 if (value && x86_pmu.limit_period) {
2449 if (x86_pmu.limit_period(event, value) > value)
2456 static int x86_pmu_aux_output_match(struct perf_event *event)
2458 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2461 if (x86_pmu.aux_output_match)
2462 return x86_pmu.aux_output_match(event);
2467 static struct pmu pmu = {
2468 .pmu_enable = x86_pmu_enable,
2469 .pmu_disable = x86_pmu_disable,
2471 .attr_groups = x86_pmu_attr_groups,
2473 .event_init = x86_pmu_event_init,
2475 .event_mapped = x86_pmu_event_mapped,
2476 .event_unmapped = x86_pmu_event_unmapped,
2480 .start = x86_pmu_start,
2481 .stop = x86_pmu_stop,
2482 .read = x86_pmu_read,
2484 .start_txn = x86_pmu_start_txn,
2485 .cancel_txn = x86_pmu_cancel_txn,
2486 .commit_txn = x86_pmu_commit_txn,
2488 .event_idx = x86_pmu_event_idx,
2489 .sched_task = x86_pmu_sched_task,
2490 .swap_task_ctx = x86_pmu_swap_task_ctx,
2491 .check_period = x86_pmu_check_period,
2493 .aux_output_match = x86_pmu_aux_output_match,
2496 void arch_perf_update_userpage(struct perf_event *event,
2497 struct perf_event_mmap_page *userpg, u64 now)
2499 struct cyc2ns_data data;
2502 userpg->cap_user_time = 0;
2503 userpg->cap_user_time_zero = 0;
2504 userpg->cap_user_rdpmc =
2505 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2506 userpg->pmc_width = x86_pmu.cntval_bits;
2508 if (!using_native_sched_clock() || !sched_clock_stable())
2511 cyc2ns_read_begin(&data);
2513 offset = data.cyc2ns_offset + __sched_clock_offset;
2516 * Internal timekeeping for enabled/running/stopped times
2517 * is always in the local_clock domain.
2519 userpg->cap_user_time = 1;
2520 userpg->time_mult = data.cyc2ns_mul;
2521 userpg->time_shift = data.cyc2ns_shift;
2522 userpg->time_offset = offset - now;
2525 * cap_user_time_zero doesn't make sense when we're using a different
2526 * time base for the records.
2528 if (!event->attr.use_clockid) {
2529 userpg->cap_user_time_zero = 1;
2530 userpg->time_zero = offset;
2537 * Determine whether the regs were taken from an irq/exception handler rather
2538 * than from perf_arch_fetch_caller_regs().
2540 static bool perf_hw_regs(struct pt_regs *regs)
2542 return regs->flags & X86_EFLAGS_FIXED;
2546 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2548 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2549 struct unwind_state state;
2552 if (guest_cbs && guest_cbs->is_in_guest()) {
2553 /* TODO: We don't support guest os callchain now */
2557 if (perf_callchain_store(entry, regs->ip))
2560 if (perf_hw_regs(regs))
2561 unwind_start(&state, current, regs, NULL);
2563 unwind_start(&state, current, NULL, (void *)regs->sp);
2565 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2566 addr = unwind_get_return_address(&state);
2567 if (!addr || perf_callchain_store(entry, addr))
2573 valid_user_frame(const void __user *fp, unsigned long size)
2575 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2578 static unsigned long get_segment_base(unsigned int segment)
2580 struct desc_struct *desc;
2581 unsigned int idx = segment >> 3;
2583 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2584 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2585 struct ldt_struct *ldt;
2587 /* IRQs are off, so this synchronizes with smp_store_release */
2588 ldt = READ_ONCE(current->active_mm->context.ldt);
2589 if (!ldt || idx >= ldt->nr_entries)
2592 desc = &ldt->entries[idx];
2597 if (idx >= GDT_ENTRIES)
2600 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2603 return get_desc_base(desc);
2606 #ifdef CONFIG_IA32_EMULATION
2608 #include <linux/compat.h>
2611 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2613 /* 32-bit process in 64-bit kernel. */
2614 unsigned long ss_base, cs_base;
2615 struct stack_frame_ia32 frame;
2616 const struct stack_frame_ia32 __user *fp;
2618 if (!test_thread_flag(TIF_IA32))
2621 cs_base = get_segment_base(regs->cs);
2622 ss_base = get_segment_base(regs->ss);
2624 fp = compat_ptr(ss_base + regs->bp);
2625 pagefault_disable();
2626 while (entry->nr < entry->max_stack) {
2627 if (!valid_user_frame(fp, sizeof(frame)))
2630 if (__get_user(frame.next_frame, &fp->next_frame))
2632 if (__get_user(frame.return_address, &fp->return_address))
2635 perf_callchain_store(entry, cs_base + frame.return_address);
2636 fp = compat_ptr(ss_base + frame.next_frame);
2643 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2650 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2652 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2653 struct stack_frame frame;
2654 const struct stack_frame __user *fp;
2656 if (guest_cbs && guest_cbs->is_in_guest()) {
2657 /* TODO: We don't support guest os callchain now */
2662 * We don't know what to do with VM86 stacks.. ignore them for now.
2664 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2667 fp = (void __user *)regs->bp;
2669 perf_callchain_store(entry, regs->ip);
2671 if (!nmi_uaccess_okay())
2674 if (perf_callchain_user32(regs, entry))
2677 pagefault_disable();
2678 while (entry->nr < entry->max_stack) {
2679 if (!valid_user_frame(fp, sizeof(frame)))
2682 if (__get_user(frame.next_frame, &fp->next_frame))
2684 if (__get_user(frame.return_address, &fp->return_address))
2687 perf_callchain_store(entry, frame.return_address);
2688 fp = (void __user *)frame.next_frame;
2694 * Deal with code segment offsets for the various execution modes:
2696 * VM86 - the good olde 16 bit days, where the linear address is
2697 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2699 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2700 * to figure out what the 32bit base address is.
2702 * X32 - has TIF_X32 set, but is running in x86_64
2704 * X86_64 - CS,DS,SS,ES are all zero based.
2706 static unsigned long code_segment_base(struct pt_regs *regs)
2709 * For IA32 we look at the GDT/LDT segment base to convert the
2710 * effective IP to a linear address.
2713 #ifdef CONFIG_X86_32
2715 * If we are in VM86 mode, add the segment offset to convert to a
2718 if (regs->flags & X86_VM_MASK)
2719 return 0x10 * regs->cs;
2721 if (user_mode(regs) && regs->cs != __USER_CS)
2722 return get_segment_base(regs->cs);
2724 if (user_mode(regs) && !user_64bit_mode(regs) &&
2725 regs->cs != __USER32_CS)
2726 return get_segment_base(regs->cs);
2731 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2733 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2735 if (guest_cbs && guest_cbs->is_in_guest())
2736 return guest_cbs->get_guest_ip();
2738 return regs->ip + code_segment_base(regs);
2741 unsigned long perf_misc_flags(struct pt_regs *regs)
2743 struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
2746 if (guest_cbs && guest_cbs->is_in_guest()) {
2747 if (guest_cbs->is_user_mode())
2748 misc |= PERF_RECORD_MISC_GUEST_USER;
2750 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2752 if (user_mode(regs))
2753 misc |= PERF_RECORD_MISC_USER;
2755 misc |= PERF_RECORD_MISC_KERNEL;
2758 if (regs->flags & PERF_EFLAGS_EXACT)
2759 misc |= PERF_RECORD_MISC_EXACT_IP;
2764 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2766 cap->version = x86_pmu.version;
2767 cap->num_counters_gp = x86_pmu.num_counters;
2768 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2769 cap->bit_width_gp = x86_pmu.cntval_bits;
2770 cap->bit_width_fixed = x86_pmu.cntval_bits;
2771 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2772 cap->events_mask_len = x86_pmu.events_mask_len;
2774 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);